Make Marvell AmadaXP timer driver more generic
Store pointers to SoC specific functions in mv_timer_config structure and determine proper config in runtime based on compatible string from FDT. Compatible string for ArmadaXP timers is changed to match Linux FDT. Armada 38x uses generic Cortex-A9 timer and separate watchdog drivers, so it does not need to be supported by timer driver. Submitted by: Rafal Kozik <rk@semihalf.com> Reviewed by: manu Obtained from: Semihalf Sponsored by: Stormshield Differential Revision: https://reviews.freebsd.org/D14741
This commit is contained in:
Marcin Wojtas
parent
d100eecfc4
commit
72dbc3aca8
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=331961
@ -46,6 +46,7 @@ __FBSDID("$FreeBSD$");
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#include <machine/bus.h>
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#include <machine/cpu.h>
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#include <machine/intr.h>
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#include <machine/machdep.h>
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#include <arm/mv/mvreg.h>
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#include <arm/mv/mvvar.h>
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@ -60,17 +61,19 @@ __FBSDID("$FreeBSD$");
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#define MV_WDT 0x2
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#define MV_NONE 0x0
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#if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X)
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#define MV_CLOCK_SRC 25000000 /* Timers' 25MHz mode */
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#else
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#define MV_CLOCK_SRC get_tclk()
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#endif
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#define MV_CLOCK_SRC_ARMV7 25000000 /* Timers' 25MHz mode */
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#if defined(SOC_MV_ARMADA38X)
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#define WATCHDOG_TIMER 4
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#else
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#define WATCHDOG_TIMER 2
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#endif
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#define WATCHDOG_TIMER_ARMV5 2
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typedef void (*mv_watchdog_enable_t)(void);
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typedef void (*mv_watchdog_disable_t)(void);
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struct mv_timer_config {
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enum soc_family soc_family;
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mv_watchdog_enable_t watchdog_enable;
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mv_watchdog_disable_t watchdog_disable;
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unsigned int clock_src;
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};
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struct mv_timer_softc {
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struct resource * timer_res[2];
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@ -79,6 +82,7 @@ struct mv_timer_softc {
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struct mtx timer_mtx;
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struct eventtimer et;
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boolean_t has_wdt;
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struct mv_timer_config* config;
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};
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static struct resource_spec mv_timer_spec[] = {
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@ -89,8 +93,9 @@ static struct resource_spec mv_timer_spec[] = {
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/* Interrupt is not required by MV_WDT devices */
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static struct ofw_compat_data mv_timer_compat[] = {
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{"marvell,armada-380-timer", MV_NONE },
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{"marvell,armada-xp-timer", MV_TMR | MV_WDT },
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{"mrvl,timer", MV_TMR | MV_WDT },
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{"marvell,armada-380-wdt", MV_WDT },
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{NULL, MV_NONE }
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};
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@ -108,14 +113,42 @@ static void mv_set_timer_control(uint32_t);
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static uint32_t mv_get_timer(uint32_t);
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static void mv_set_timer(uint32_t, uint32_t);
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static void mv_set_timer_rel(uint32_t, uint32_t);
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static void mv_watchdog_enable(void);
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static void mv_watchdog_disable(void);
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static void mv_watchdog_event(void *, unsigned int, int *);
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static int mv_timer_start(struct eventtimer *et,
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sbintime_t first, sbintime_t period);
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static int mv_timer_stop(struct eventtimer *et);
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static void mv_setup_timers(void);
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static void mv_watchdog_enable_armv5(void);
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static void mv_watchdog_enable_armadaxp(void);
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static void mv_watchdog_disable_armv5(void);
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static void mv_watchdog_disable_armadaxp(void);
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#ifdef PLATFORM
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void mv_delay(int usec, void* arg);
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#endif
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static struct mv_timer_config timer_armadaxp_config =
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{
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MV_SOC_ARMADA_XP,
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&mv_watchdog_enable_armadaxp,
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&mv_watchdog_disable_armadaxp,
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MV_CLOCK_SRC_ARMV7,
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};
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static struct mv_timer_config timer_armv5_config =
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{
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MV_SOC_ARMV5,
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&mv_watchdog_enable_armv5,
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&mv_watchdog_disable_armv5,
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0,
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};
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static struct ofw_compat_data mv_timer_soc_config[] = {
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{"marvell,armada-xp-timer", (uintptr_t)&timer_armadaxp_config },
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{"mrvl,timer", (uintptr_t)&timer_armv5_config },
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{NULL, (uintptr_t)NULL },
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};
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static struct timecounter mv_timer_timecounter = {
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.tc_get_timecount = mv_timer_get_timecount,
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.tc_name = "CPUTimer1",
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@ -144,9 +177,7 @@ mv_timer_attach(device_t dev)
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int error;
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void *ihl;
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struct mv_timer_softc *sc;
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#if !defined(SOC_MV_ARMADAXP) && !defined(SOC_MV_ARMADA38X)
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uint32_t irq_cause, irq_mask;
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#endif
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if (timer_softc != NULL)
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return (ENXIO);
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@ -154,6 +185,12 @@ mv_timer_attach(device_t dev)
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sc = (struct mv_timer_softc *)device_get_softc(dev);
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timer_softc = sc;
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sc->config = (struct mv_timer_config*)
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ofw_bus_search_compatible(dev, mv_timer_soc_config)->ocd_data;
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if (sc->config->clock_src == 0)
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sc->config->clock_src = get_tclk();
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error = bus_alloc_resources(dev, mv_timer_spec, sc->timer_res);
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if (error) {
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device_printf(dev, "could not allocate resources\n");
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@ -163,13 +200,13 @@ mv_timer_attach(device_t dev)
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sc->timer_bst = rman_get_bustag(sc->timer_res[0]);
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sc->timer_bsh = rman_get_bushandle(sc->timer_res[0]);
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sc->has_wdt = ofw_bus_has_prop(dev, "mrvl,has-wdt") ||
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ofw_bus_is_compatible(dev, "marvell,armada-380-wdt");
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sc->has_wdt = ofw_bus_has_prop(dev, "mrvl,has-wdt");
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mtx_init(&timer_softc->timer_mtx, "watchdog", NULL, MTX_DEF);
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if (sc->has_wdt) {
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mv_watchdog_disable();
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if (sc->config->watchdog_disable)
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sc->config->watchdog_disable();
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EVENTHANDLER_REGISTER(watchdog_list, mv_watchdog_event, sc, 0);
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}
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@ -192,30 +229,33 @@ mv_timer_attach(device_t dev)
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}
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mv_setup_timers();
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#if !defined(SOC_MV_ARMADAXP) && !defined(SOC_MV_ARMADA38X)
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irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE);
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irq_cause &= IRQ_TIMER0_CLR;
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if (sc->config->soc_family != MV_SOC_ARMADA_XP ) {
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irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE);
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irq_cause &= IRQ_TIMER0_CLR;
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write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause);
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irq_mask = read_cpu_ctrl(BRIDGE_IRQ_MASK);
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irq_mask |= IRQ_TIMER0_MASK;
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irq_mask &= ~IRQ_TIMER1_MASK;
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write_cpu_ctrl(BRIDGE_IRQ_MASK, irq_mask);
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#endif
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write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause);
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irq_mask = read_cpu_ctrl(BRIDGE_IRQ_MASK);
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irq_mask |= IRQ_TIMER0_MASK;
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irq_mask &= ~IRQ_TIMER1_MASK;
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write_cpu_ctrl(BRIDGE_IRQ_MASK, irq_mask);
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}
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sc->et.et_name = "CPUTimer0";
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sc->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT;
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sc->et.et_quality = 1000;
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sc->et.et_frequency = MV_CLOCK_SRC;
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sc->et.et_frequency = sc->config->clock_src;
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sc->et.et_min_period = (0x00000002LLU << 32) / sc->et.et_frequency;
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sc->et.et_max_period = (0xfffffffeLLU << 32) / sc->et.et_frequency;
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sc->et.et_start = mv_timer_start;
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sc->et.et_stop = mv_timer_stop;
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sc->et.et_priv = sc;
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et_register(&sc->et);
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mv_timer_timecounter.tc_frequency = MV_CLOCK_SRC;
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mv_timer_timecounter.tc_frequency = sc->config->clock_src;
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tc_init(&mv_timer_timecounter);
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#ifdef PLATFORM
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arm_set_delay(mv_delay, NULL);
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#endif
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return (0);
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}
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@ -260,8 +300,13 @@ mv_timer_get_timecount(struct timecounter *tc)
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return (INITIAL_TIMECOUNTER - mv_get_timer(1));
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}
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#ifdef PLATFORM
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void
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mv_delay(int usec, void* arg)
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#else
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void
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DELAY(int usec)
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#endif
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{
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uint32_t val, val_temp;
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int32_t nticks;
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@ -275,7 +320,7 @@ DELAY(int usec)
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TSENTER();
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val = mv_get_timer(1);
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nticks = ((MV_CLOCK_SRC / 1000000 + 1) * usec);
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nticks = ((timer_softc->config->clock_src / 1000000 + 1) * usec);
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while (nticks > 0) {
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val_temp = mv_get_timer(1);
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@ -330,26 +375,14 @@ mv_set_timer_rel(uint32_t timer, uint32_t val)
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}
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static void
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mv_watchdog_enable(void)
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mv_watchdog_enable_armv5(void)
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{
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uint32_t val, irq_cause;
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#if !defined(SOC_MV_ARMADAXP) && !defined(SOC_MV_ARMADA38X)
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uint32_t irq_mask;
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#endif
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uint32_t val, irq_cause, irq_mask;
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irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE);
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irq_cause &= IRQ_TIMER_WD_CLR;
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write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause);
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#if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X)
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val = read_cpu_mp_clocks(WD_RSTOUTn_MASK);
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val |= (WD_GLOBAL_MASK | WD_CPU0_MASK);
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write_cpu_mp_clocks(WD_RSTOUTn_MASK, val);
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val = read_cpu_misc(RSTOUTn_MASK);
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val &= ~RSTOUTn_MASK_WD;
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write_cpu_misc(RSTOUTn_MASK, val);
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#else
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irq_mask = read_cpu_ctrl(BRIDGE_IRQ_MASK);
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irq_mask |= IRQ_TIMER_WD_MASK;
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write_cpu_ctrl(BRIDGE_IRQ_MASK, irq_mask);
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@ -357,44 +390,43 @@ mv_watchdog_enable(void)
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val = read_cpu_ctrl(RSTOUTn_MASK);
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val |= WD_RST_OUT_EN;
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write_cpu_ctrl(RSTOUTn_MASK, val);
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#endif
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val = mv_get_timer_control();
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#if defined(SOC_MV_ARMADA38X)
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val |= CPU_TIMER_WD_EN | CPU_TIMER_WD_AUTO | CPU_TIMER_WD_25MHZ_EN;
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#elif defined(SOC_MV_ARMADAXP)
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val |= CPU_TIMER2_EN | CPU_TIMER2_AUTO | CPU_TIMER_WD_25MHZ_EN;
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#else
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val |= CPU_TIMER2_EN | CPU_TIMER2_AUTO;
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#endif
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mv_set_timer_control(val);
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}
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static void
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mv_watchdog_disable(void)
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mv_watchdog_enable_armadaxp(void)
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{
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uint32_t val, irq_cause;
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#if !defined(SOC_MV_ARMADAXP) && !defined(SOC_MV_ARMADA38X)
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uint32_t irq_mask;
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#endif
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uint32_t irq_cause, val;
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val = mv_get_timer_control();
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#if defined(SOC_MV_ARMADA38X)
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val &= ~(CPU_TIMER_WD_EN | CPU_TIMER_WD_AUTO);
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#else
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val &= ~(CPU_TIMER2_EN | CPU_TIMER2_AUTO);
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#endif
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mv_set_timer_control(val);
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irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE);
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irq_cause &= IRQ_TIMER_WD_CLR;
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write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause);
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#if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X)
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val = read_cpu_mp_clocks(WD_RSTOUTn_MASK);
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val &= ~(WD_GLOBAL_MASK | WD_CPU0_MASK);
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val |= (WD_GLOBAL_MASK | WD_CPU0_MASK);
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write_cpu_mp_clocks(WD_RSTOUTn_MASK, val);
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val = read_cpu_misc(RSTOUTn_MASK);
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val |= RSTOUTn_MASK_WD;
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write_cpu_misc(RSTOUTn_MASK, RSTOUTn_MASK_WD);
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#else
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val &= ~RSTOUTn_MASK_WD;
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write_cpu_misc(RSTOUTn_MASK, val);
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val = mv_get_timer_control();
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val |= CPU_TIMER2_EN | CPU_TIMER2_AUTO | CPU_TIMER_WD_25MHZ_EN;
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mv_set_timer_control(val);
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}
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static void
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mv_watchdog_disable_armv5(void)
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{
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uint32_t val, irq_cause,irq_mask;
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val = mv_get_timer_control();
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val &= ~(CPU_TIMER2_EN | CPU_TIMER2_AUTO);
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mv_set_timer_control(val);
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val = read_cpu_ctrl(RSTOUTn_MASK);
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val &= ~WD_RST_OUT_EN;
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write_cpu_ctrl(RSTOUTn_MASK, val);
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@ -402,13 +434,33 @@ mv_watchdog_disable(void)
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irq_mask = read_cpu_ctrl(BRIDGE_IRQ_MASK);
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irq_mask &= ~(IRQ_TIMER_WD_MASK);
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write_cpu_ctrl(BRIDGE_IRQ_MASK, irq_mask);
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#endif
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irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE);
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irq_cause &= IRQ_TIMER_WD_CLR;
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write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause);
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}
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static void
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mv_watchdog_disable_armadaxp(void)
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{
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uint32_t val, irq_cause;
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val = read_cpu_mp_clocks(WD_RSTOUTn_MASK);
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val &= ~(WD_GLOBAL_MASK | WD_CPU0_MASK);
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write_cpu_mp_clocks(WD_RSTOUTn_MASK, val);
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val = read_cpu_misc(RSTOUTn_MASK);
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val |= RSTOUTn_MASK_WD;
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write_cpu_misc(RSTOUTn_MASK, RSTOUTn_MASK_WD);
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irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE);
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irq_cause &= IRQ_TIMER_WD_CLR;
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write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause);
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val = mv_get_timer_control();
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val &= ~(CPU_TIMER2_EN | CPU_TIMER2_AUTO);
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mv_set_timer_control(val);
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}
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/*
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* Watchdog event handler.
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@ -420,20 +472,23 @@ mv_watchdog_event(void *arg, unsigned int cmd, int *error)
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uint64_t ticks;
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mtx_lock(&timer_softc->timer_mtx);
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if (cmd == 0)
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mv_watchdog_disable();
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else {
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if (cmd == 0) {
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if (timer_softc->config->watchdog_disable != NULL)
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timer_softc->config->watchdog_disable();
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} else {
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/*
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* Watchdog timeout is in nanosecs, calculation according to
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* watchdog(9)
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*/
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ns = (uint64_t)1 << (cmd & WD_INTERVAL);
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ticks = (uint64_t)(ns * MV_CLOCK_SRC) / 1000000000;
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if (ticks > MAX_WATCHDOG_TICKS)
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mv_watchdog_disable();
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else {
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mv_set_timer(WATCHDOG_TIMER, ticks);
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mv_watchdog_enable();
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ticks = (uint64_t)(ns * timer_softc->config->clock_src) / 1000000000;
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if (ticks > MAX_WATCHDOG_TICKS) {
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if (timer_softc->config->watchdog_disable != NULL)
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timer_softc->config->watchdog_disable();
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} else {
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mv_set_timer(WATCHDOG_TIMER_ARMV5, ticks);
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if (timer_softc->config->watchdog_enable != NULL)
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timer_softc->config->watchdog_enable();
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*error = 0;
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}
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}
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@ -491,10 +546,12 @@ mv_setup_timers(void)
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val = mv_get_timer_control();
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val &= ~(CPU_TIMER0_EN | CPU_TIMER0_AUTO);
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val |= CPU_TIMER1_EN | CPU_TIMER1_AUTO;
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#if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X)
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/* Enable 25MHz mode */
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val |= CPU_TIMER0_25MHZ_EN | CPU_TIMER1_25MHZ_EN;
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#endif
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if (timer_softc->config->soc_family == MV_SOC_ARMADA_XP) {
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/* Enable 25MHz mode */
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val |= CPU_TIMER0_25MHZ_EN | CPU_TIMER1_25MHZ_EN;
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}
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mv_set_timer_control(val);
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timers_initialized = 1;
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}
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@ -85,7 +85,7 @@
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};
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timer@21840 {
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compatible = "mrvl,timer";
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compatible = "marvell,armada-xp-timer";
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reg = <0x21840 0x30>;
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interrupts = <5>;
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interrupt-parent = <&MPIC>;
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