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arm: allwinner: clk: Use the new frac clock

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Some clocks used the NM type but this clock is for the ones with the
formula "clk = clkin / n / m" and not "clk = clkin * n / m"
Use the new frac clock for them.
This commit is contained in:
Emmanuel Vadot 2019-05-23 17:36:19 +00:00
parent 3b85cf6b3f
commit 747ef14e61
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=348181
4 changed files with 39 additions and 37 deletions
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8
sys/arm/allwinner/clkng/ccu_a10.c
View File

@ -212,7 +212,7 @@ NKMP_CLK(pll_core_clk,
0, 0, /* lock */
AW_CLK_HAS_GATE); /* flags */
NM_CLK_WITH_FRAC(pll_video0_clk,
FRAC_CLK(pll_video0_clk,
CLK_PLL_VIDEO0, /* id */
"pll_video0", pll_parents, /* name, parents */
0x10, /* offset */
@ -231,7 +231,7 @@ FIXED_CLK(pll_video0_2x_clk,
1, /* div */
0); /* flags */
NM_CLK_WITH_FRAC(pll_video1_clk,
FRAC_CLK(pll_video1_clk,
CLK_PLL_VIDEO1, /* id */
"pll_video1", pll_parents, /* name, parents */
0x30, /* offset */
@ -537,8 +537,8 @@ static struct aw_ccung_clk a10_ccu_clks[] = {
{ .type = AW_CLK_NM, .clk.nm = &ahb_clk},
{ .type = AW_CLK_NM, .clk.nm = &apb0_clk},
{ .type = AW_CLK_NM, .clk.nm = &apb1_clk},
{ .type = AW_CLK_NM, .clk.nm = &pll_video0_clk},
{ .type = AW_CLK_NM, .clk.nm = &pll_video1_clk},
{ .type = AW_CLK_FRAC, .clk.frac = &pll_video0_clk},
{ .type = AW_CLK_FRAC, .clk.frac = &pll_video1_clk},
{ .type = AW_CLK_NM, .clk.nm = &nand_clk},
{ .type = AW_CLK_NM, .clk.nm = &ms_clk},
{ .type = AW_CLK_NM, .clk.nm = &mmc0_clk},

24
sys/arm/allwinner/clkng/ccu_a31.c
View File

@ -293,7 +293,7 @@ FIXED_CLK(pll_audio_8x_clk,
1, /* div */
0); /* flags */
NM_CLK_WITH_FRAC(pll_video0_clk,
FRAC_CLK(pll_video0_clk,
CLK_PLL_VIDEO0, /* id */
"pll_video0", pll_parents, /* name, parents */
0x10, /* offset */
@ -314,7 +314,7 @@ FIXED_CLK(pll_video0_2x_clk,
1, /* div */
0); /* flags */
NM_CLK_WITH_FRAC(pll_ve_clk,
FRAC_CLK(pll_ve_clk,
CLK_PLL_VE, /* id */
"pll_ve", pll_parents, /* name, parents */
0x18, /* offset */
@ -360,7 +360,7 @@ FIXED_CLK(pll_periph_2x_clk,
1, /* div */
0); /* flags */
NM_CLK_WITH_FRAC(pll_video1_clk,
FRAC_CLK(pll_video1_clk,
CLK_PLL_VIDEO1, /* id */
"pll_video1", pll_parents, /* name, parents */
0x30, /* offset */
@ -381,7 +381,7 @@ FIXED_CLK(pll_video1_2x_clk,
1, /* div */
0); /* flags */
NM_CLK_WITH_FRAC(pll_gpu_clk,
FRAC_CLK(pll_gpu_clk,
CLK_PLL_GPU, /* id */
"pll_gpu", pll_parents, /* name, parents */
0x38, /* offset */
@ -405,7 +405,7 @@ NKMP_CLK(pll_mipi_clk,
28, 1000, /* lock */
AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK); /* flags */
NM_CLK_WITH_FRAC(pll9_clk,
FRAC_CLK(pll9_clk,
CLK_PLL9, /* id */
"pll9", pll_parents, /* name, parents */
0x44, /* offset */
@ -416,7 +416,7 @@ NM_CLK_WITH_FRAC(pll9_clk,
270000000, 297000000, /* freq0, freq1 */
24, 25); /* mode sel, freq sel */
NM_CLK_WITH_FRAC(pll10_clk,
FRAC_CLK(pll10_clk,
CLK_PLL10, /* id */
"pll10", pll_parents, /* name, parents */
0x48, /* offset */
@ -869,12 +869,12 @@ static struct aw_ccung_clk a31_ccu_clks[] = {
{ .type = AW_CLK_NKMP, .clk.nkmp = &pll_periph_clk},
{ .type = AW_CLK_NKMP, .clk.nkmp = &pll_ddr_clk},
{ .type = AW_CLK_NKMP, .clk.nkmp = &pll_mipi_clk},
{ .type = AW_CLK_NM, .clk.nm = &pll_video0_clk},
{ .type = AW_CLK_NM, .clk.nm = &pll_ve_clk},
{ .type = AW_CLK_NM, .clk.nm = &pll_video1_clk},
{ .type = AW_CLK_NM, .clk.nm = &pll_gpu_clk},
{ .type = AW_CLK_NM, .clk.nm = &pll9_clk},
{ .type = AW_CLK_NM, .clk.nm = &pll10_clk},
{ .type = AW_CLK_FRAC, .clk.frac = &pll_video0_clk},
{ .type = AW_CLK_FRAC, .clk.frac = &pll_ve_clk},
{ .type = AW_CLK_FRAC, .clk.frac = &pll_video1_clk},
{ .type = AW_CLK_FRAC, .clk.frac = &pll_gpu_clk},
{ .type = AW_CLK_FRAC, .clk.frac = &pll9_clk},
{ .type = AW_CLK_FRAC, .clk.frac = &pll10_clk},
{ .type = AW_CLK_NM, .clk.nm = &apb2_clk},
{ .type = AW_CLK_NM, .clk.nm = &nand0_clk},
{ .type = AW_CLK_NM, .clk.nm = &nand1_clk},

28
sys/arm/allwinner/clkng/ccu_a64.c
View File

@ -279,7 +279,7 @@ FIXED_CLK(pll_audio_8x_clk,
0); /* flags */
static const char *pll_video0_parents[] = {"osc24M"};
NM_CLK_WITH_FRAC(pll_video0_clk,
FRAC_CLK(pll_video0_clk,
CLK_PLL_VIDEO0, /* id */
"pll_video0", pll_video0_parents, /* name, parents */
0x10, /* offset */
@ -300,7 +300,7 @@ FIXED_CLK(pll_video0_2x_clk,
0); /* flags */
static const char *pll_ve_parents[] = {"osc24M"};
NM_CLK_WITH_FRAC(pll_ve_clk,
FRAC_CLK(pll_ve_clk,
CLK_PLL_VE, /* id */
"pll_ve", pll_ve_parents, /* name, parents */
0x18, /* offset */
@ -370,7 +370,7 @@ FIXED_CLK(pll_periph1_clk,
0); /* flags */
static const char *pll_video1_parents[] = {"osc24M"};
NM_CLK_WITH_FRAC(pll_video1_clk,
FRAC_CLK(pll_video1_clk,
CLK_PLL_VIDEO1, /* id */
"pll_video1", pll_video1_parents, /* name, parents */
0x30, /* offset */
@ -382,7 +382,7 @@ NM_CLK_WITH_FRAC(pll_video1_clk,
24, 25); /* mode sel, freq sel */
static const char *pll_gpu_parents[] = {"osc24M"};
NM_CLK_WITH_FRAC(pll_gpu_clk,
FRAC_CLK(pll_gpu_clk,
CLK_PLL_GPU, /* id */
"pll_gpu", pll_gpu_parents, /* name, parents */
0x38, /* offset */
@ -396,7 +396,7 @@ NM_CLK_WITH_FRAC(pll_gpu_clk,
/* PLL MIPI is missing */
static const char *pll_hsic_parents[] = {"osc24M"};
NM_CLK_WITH_FRAC(pll_hsic_clk,
FRAC_CLK(pll_hsic_clk,
CLK_PLL_HSIC, /* id */
"pll_hsic", pll_hsic_parents, /* name, parents */
0x44, /* offset */
@ -408,7 +408,7 @@ NM_CLK_WITH_FRAC(pll_hsic_clk,
24, 25); /* mode sel, freq sel */
static const char *pll_de_parents[] = {"osc24M"};
NM_CLK_WITH_FRAC(pll_de_clk,
FRAC_CLK(pll_de_clk,
CLK_PLL_DE, /* id */
"pll_de", pll_de_parents, /* name, parents */
0x48, /* offset */
@ -723,16 +723,18 @@ NM_CLK(gpu_clk,
static struct aw_ccung_clk a64_ccu_clks[] = {
{ .type = AW_CLK_NKMP, .clk.nkmp = &pll_cpux_clk},
{ .type = AW_CLK_NKMP, .clk.nkmp = &pll_audio_clk},
{ .type = AW_CLK_FRAC, .clk.frac = &pll_video0_clk},
{ .type = AW_CLK_FRAC, .clk.frac = &pll_ve_clk},
{ .type = AW_CLK_NKMP, .clk.nkmp = &pll_ddr0_clk},
{ .type = AW_CLK_NKMP, .clk.nkmp = &pll_periph0_2x_clk},
{ .type = AW_CLK_NKMP, .clk.nkmp = &pll_periph1_2x_clk},
{ .type = AW_CLK_NKMP, .clk.nkmp = &pll_ddr0_clk},
{ .type = AW_CLK_FRAC, .clk.frac = &pll_video1_clk},
{ .type = AW_CLK_FRAC, .clk.frac = &pll_gpu_clk},
/* PLL_MIPI */
{ .type = AW_CLK_FRAC, .clk.frac = &pll_hsic_clk},
{ .type = AW_CLK_FRAC, .clk.frac = &pll_de_clk},
{ .type = AW_CLK_NKMP, .clk.nkmp = &pll_ddr1_clk},
{ .type = AW_CLK_NM, .clk.nm = &pll_video0_clk},
{ .type = AW_CLK_NM, .clk.nm = &pll_video1_clk},
{ .type = AW_CLK_NM, .clk.nm = &pll_ve_clk},
{ .type = AW_CLK_NM, .clk.nm = &pll_gpu_clk},
{ .type = AW_CLK_NM, .clk.nm = &pll_de_clk},
{ .type = AW_CLK_NM, .clk.nm = &pll_hsic_clk},
{ .type = AW_CLK_NM, .clk.nm = &apb2_clk},
{ .type = AW_CLK_NM, .clk.nm = &nand_clk},
{ .type = AW_CLK_NM, .clk.nm = &mmc0_clk},

16
sys/arm/allwinner/clkng/ccu_h3.c
View File

@ -297,7 +297,7 @@ FIXED_CLK(pll_audio_8x_clk,
0); /* flags */
static const char *pll_video_parents[] = {"osc24M"};
NM_CLK_WITH_FRAC(pll_video_clk,
FRAC_CLK(pll_video_clk,
CLK_PLL_VIDEO, /* id */
"pll_video", pll_video_parents, /* name, parents */
0x10, /* offset */
@ -309,7 +309,7 @@ NM_CLK_WITH_FRAC(pll_video_clk,
24, 25); /* mode sel, freq sel */
static const char *pll_ve_parents[] = {"osc24M"};
NM_CLK_WITH_FRAC(pll_ve_clk,
FRAC_CLK(pll_ve_clk,
CLK_PLL_VE, /* id */
"pll_ve", pll_ve_parents, /* name, parents */
0x18, /* offset */
@ -357,7 +357,7 @@ FIXED_CLK(pll_periph0_2x_clk,
0); /* flags */
static const char *pll_gpu_parents[] = {"osc24M"};
NM_CLK_WITH_FRAC(pll_gpu_clk,
FRAC_CLK(pll_gpu_clk,
CLK_PLL_GPU, /* id */
"pll_gpu", pll_gpu_parents, /* name, parents */
0x38, /* offset */
@ -382,7 +382,7 @@ NKMP_CLK(pll_periph1_clk,
AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK); /* flags */
static const char *pll_de_parents[] = {"osc24M"};
NM_CLK_WITH_FRAC(pll_de_clk,
FRAC_CLK(pll_de_clk,
CLK_PLL_DE, /* id */
"pll_de", pll_de_parents, /* name, parents */
0x48, /* offset */
@ -684,10 +684,10 @@ static struct aw_ccung_clk h3_ccu_clks[] = {
{ .type = AW_CLK_NKMP, .clk.nkmp = &pll_periph0_clk},
{ .type = AW_CLK_NKMP, .clk.nkmp = &pll_periph1_clk},
{ .type = AW_CLK_NKMP, .clk.nkmp = &pll_ddr_clk},
{ .type = AW_CLK_NM, .clk.nm = &pll_video_clk},
{ .type = AW_CLK_NM, .clk.nm = &pll_ve_clk},
{ .type = AW_CLK_NM, .clk.nm = &pll_gpu_clk},
{ .type = AW_CLK_NM, .clk.nm = &pll_de_clk},
{ .type = AW_CLK_FRAC, .clk.frac = &pll_video_clk},
{ .type = AW_CLK_FRAC, .clk.frac = &pll_ve_clk},
{ .type = AW_CLK_FRAC, .clk.frac = &pll_gpu_clk},
{ .type = AW_CLK_FRAC, .clk.frac = &pll_de_clk},
{ .type = AW_CLK_NM, .clk.nm = &apb2_clk},
{ .type = AW_CLK_NM, .clk.nm = &nand_clk},
{ .type = AW_CLK_NM, .clk.nm = &mmc0_clk},