Add a PCI bridge for the Freescale PCIe Root Complex
Summary: The Freescale PCIe Root Complex shows up as a Processor class device, PowerPC subclass, so the generic PCI code ignores it for a bridge. This adds support for it. As part of this, update the Freescale PCI hostbridge driver, to allow probing beyond the root complex, instead of only allowing "proper" PCI-PCI bridges. Reviewers: #powerpc, marcel, nwhitehorn Reviewed By: nwhitehorn Subscribers: imp Differential Revision: https://reviews.freebsd.org/D2442 Relnotes: yes
This commit is contained in:
Justin Hibbits
parent
74de7730b7
commit
809923ca02
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=282783
@ -138,6 +138,7 @@ powerpc/mpc85xx/mpc85xx.c optional mpc85xx
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powerpc/mpc85xx/mpc85xx_gpio.c optional mpc85xx gpio
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powerpc/mpc85xx/platform_mpc85xx.c optional mpc85xx
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powerpc/mpc85xx/pci_mpc85xx.c optional pci mpc85xx
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powerpc/mpc85xx/pci_mpc85xx_pcib.c optional pci mpc85xx
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powerpc/ofw/ofw_machdep.c standard
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powerpc/ofw/ofw_pci.c optional pci
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powerpc/ofw/ofw_pcibus.c optional pci
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@ -442,16 +442,7 @@ pcib_probe_windows(struct pcib_softc *sc)
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dev = sc->dev;
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if (pci_clear_pcib) {
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pci_write_config(dev, PCIR_IOBASEL_1, 0xff, 1);
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pci_write_config(dev, PCIR_IOBASEH_1, 0xffff, 2);
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pci_write_config(dev, PCIR_IOLIMITL_1, 0, 1);
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pci_write_config(dev, PCIR_IOLIMITH_1, 0, 2);
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pci_write_config(dev, PCIR_MEMBASE_1, 0xffff, 2);
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pci_write_config(dev, PCIR_MEMLIMIT_1, 0, 2);
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pci_write_config(dev, PCIR_PMBASEL_1, 0xffff, 2);
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pci_write_config(dev, PCIR_PMBASEH_1, 0xffffffff, 4);
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pci_write_config(dev, PCIR_PMLIMITL_1, 0, 2);
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pci_write_config(dev, PCIR_PMLIMITH_1, 0, 4);
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pcib_bridge_init(dev);
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}
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/* Determine if the I/O port window is implemented. */
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@ -1115,6 +1106,21 @@ pcib_resume(device_t dev)
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return (bus_generic_resume(dev));
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}
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void
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pcib_bridge_init(device_t dev)
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{
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pci_write_config(dev, PCIR_IOBASEL_1, 0xff, 1);
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pci_write_config(dev, PCIR_IOBASEH_1, 0xffff, 2);
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pci_write_config(dev, PCIR_IOLIMITL_1, 0, 1);
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pci_write_config(dev, PCIR_IOLIMITH_1, 0, 2);
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pci_write_config(dev, PCIR_MEMBASE_1, 0xffff, 2);
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pci_write_config(dev, PCIR_MEMLIMIT_1, 0, 2);
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pci_write_config(dev, PCIR_PMBASEL_1, 0xffff, 2);
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pci_write_config(dev, PCIR_PMBASEH_1, 0xffffffff, 4);
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pci_write_config(dev, PCIR_PMLIMITL_1, 0, 2);
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pci_write_config(dev, PCIR_PMLIMITH_1, 0, 4);
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}
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int
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pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
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{
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@ -145,6 +145,7 @@ void pcib_setup_secbus(device_t dev, struct pcib_secbus *bus,
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#endif
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int pcib_attach(device_t dev);
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void pcib_attach_common(device_t dev);
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void pcib_bridge_init(device_t dev);
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#ifdef NEW_PCIB
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const char *pcib_child_name(device_t child);
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#endif
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@ -570,10 +570,19 @@ fsl_pcib_init(struct fsl_pcib_softc *sc, int bus, int maxslot)
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subclass = fsl_pcib_read_config(sc->sc_dev, bus, slot,
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func, PCIR_SUBCLASS, 1);
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/*
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* The PCI Root Complex comes up as a Processor/PowerPC,
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* but is a bridge.
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*/
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/* Allow only proper PCI-PCI briges */
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if (class != PCIC_BRIDGE)
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if (class != PCIC_BRIDGE && class != PCIC_PROCESSOR)
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continue;
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if (subclass != PCIS_BRIDGE_PCI)
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if (subclass != PCIS_BRIDGE_PCI &&
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subclass != PCIS_PROCESSOR_POWERPC)
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continue;
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if (subclass == PCIS_PROCESSOR_POWERPC &&
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hdrtype != PCIM_HDRTYPE_BRIDGE)
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continue;
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secbus++;
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@ -825,4 +834,3 @@ fsl_pcib_decode_win(phandle_t node, struct fsl_pcib_softc *sc)
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return (0);
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}
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104
sys/powerpc/mpc85xx/pci_mpc85xx_pcib.c
Normal file
104
sys/powerpc/mpc85xx/pci_mpc85xx_pcib.c
Normal file
@ -0,0 +1,104 @@
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/*-
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* Copyright 2015 Justin Hibbits
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* From: FreeBSD: src/sys/powerpc/mpc85xx/pci_ocp.c,v 1.9 2010/03/23 23:46:28 marcel
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/ktr.h>
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#include <sys/sockio.h>
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#include <sys/mbuf.h>
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#include <sys/malloc.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/socket.h>
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#include <sys/queue.h>
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#include <sys/bus.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/rman.h>
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#include <sys/endian.h>
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#include <vm/vm.h>
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#include <vm/pmap.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcib_private.h>
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#include "pcib_if.h"
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static int
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fsl_pcib_rc_probe(device_t dev)
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{
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printf("Probe called\n");
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if (pci_get_vendor(dev) != 0x1957)
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return (ENXIO);
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if (pci_get_progif(dev) != 0)
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return (ENXIO);
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if (pci_get_class(dev) != PCIC_PROCESSOR)
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return (ENXIO);
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if (pci_get_subclass(dev) != PCIS_PROCESSOR_POWERPC)
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return (ENXIO);
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return (BUS_PROBE_DEFAULT);
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}
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static int
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fsl_pcib_rc_attach(device_t dev)
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{
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struct pcib_softc *sc;
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device_t child;
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pcib_bridge_init(dev);
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pcib_attach_common(dev);
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sc = device_get_softc(dev);
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if (sc->bus.sec != 0) {
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child = device_add_child(dev, "pci", -1);
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if (child != NULL)
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return (bus_generic_attach(dev));
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}
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return (0);
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}
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static device_method_t fsl_pcib_rc_methods[] = {
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DEVMETHOD(device_probe, fsl_pcib_rc_probe),
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DEVMETHOD(device_attach, fsl_pcib_rc_attach),
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DEVMETHOD_END
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};
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static devclass_t fsl_pcib_rc_devclass;
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DEFINE_CLASS_1(pcib, fsl_pcib_rc_driver, fsl_pcib_rc_methods,
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sizeof(struct pcib_softc), pcib_driver);
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DRIVER_MODULE(rcpcib, pci, fsl_pcib_rc_driver, fsl_pcib_rc_devclass, 0, 0);
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