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arm64: Update the ID_AA64PFR1_EL1 fields

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While here move to decimal for the _op and _CR definitions to be used
by a future macro to define the register when the assembler doesn't
know about it.

Sponsored by:	Arm Ltd
Differential Revision:	https://reviews.freebsd.org/D40896
This commit is contained in:
Andrew Turner 2023-07-06 15:40:01 +01:00
parent 0766dde9b5
commit 8c111e5b37
2 changed files with 86 additions and 11 deletions
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51
sys/arm64/arm64/identcpu.c
View File

@ -1453,10 +1453,47 @@ static const struct mrs_field id_aa64pfr0_fields[] = {
/* ID_AA64PFR1_EL1 */
static const struct mrs_field_value id_aa64pfr1_nmi[] = {
MRS_FIELD_VALUE_NONE_IMPL(ID_AA64PFR1, NMI, NONE, IMPL),
MRS_FIELD_VALUE_END,
};
static const struct mrs_field_value id_aa64pfr1_csv2_frac[] = {
MRS_FIELD_VALUE(ID_AA64PFR1_CSV2_frac_p0, ""),
MRS_FIELD_VALUE(ID_AA64PFR1_CSV2_frac_p1, "CSV2 p1"),
MRS_FIELD_VALUE(ID_AA64PFR1_CSV2_frac_p2, "CSV2 p2"),
MRS_FIELD_VALUE_END,
};
static const struct mrs_field_value id_aa64pfr1_rndr_trap[] = {
MRS_FIELD_VALUE_NONE_IMPL(ID_AA64PFR1, RNDR_trap, NONE, IMPL),
MRS_FIELD_VALUE_END,
};
static const struct mrs_field_value id_aa64pfr1_sme[] = {
MRS_FIELD_VALUE(ID_AA64PFR1_SME_NONE, ""),
MRS_FIELD_VALUE(ID_AA64PFR1_SME_SME, "SME"),
MRS_FIELD_VALUE(ID_AA64PFR1_SME_SME2, "SME2"),
MRS_FIELD_VALUE_END,
};
static const struct mrs_field_value id_aa64pfr1_mpam_frac[] = {
MRS_FIELD_VALUE(ID_AA64PFR1_MPAM_frac_p0, ""),
MRS_FIELD_VALUE(ID_AA64PFR1_MPAM_frac_p1, "MPAM p1"),
MRS_FIELD_VALUE_END,
};
static const struct mrs_field_value id_aa64pfr1_ras_frac[] = {
MRS_FIELD_VALUE(ID_AA64PFR1_RAS_frac_p0, ""),
MRS_FIELD_VALUE(ID_AA64PFR1_RAS_frac_p1, "RAS p1"),
MRS_FIELD_VALUE_END,
};
static const struct mrs_field_value id_aa64pfr1_mte[] = {
MRS_FIELD_VALUE(ID_AA64PFR1_MTE_NONE, ""),
MRS_FIELD_VALUE(ID_AA64PFR1_MTE_IMPL_EL0, "MTE EL0"),
MRS_FIELD_VALUE(ID_AA64PFR1_MTE_IMPL, "MTE"),
MRS_FIELD_VALUE(ID_AA64PFR1_MTE_MTE, "MTE"),
MRS_FIELD_VALUE(ID_AA64PFR1_MTE_MTE2, "MTE2"),
MRS_FIELD_VALUE(ID_AA64PFR1_MTE_MTE3, "MTE3"),
MRS_FIELD_VALUE_END,
};
@ -1487,6 +1524,16 @@ static const struct mrs_field_hwcap id_aa64pfr1_bt_caps[] = {
#endif
static const struct mrs_field id_aa64pfr1_fields[] = {
MRS_FIELD(ID_AA64PFR1, NMI, false, MRS_EXACT, id_aa64pfr1_nmi),
MRS_FIELD(ID_AA64PFR1, CSV2_frac, false, MRS_EXACT,
id_aa64pfr1_csv2_frac),
MRS_FIELD(ID_AA64PFR1, RNDR_trap, false, MRS_EXACT,
id_aa64pfr1_rndr_trap),
MRS_FIELD(ID_AA64PFR1, SME, false, MRS_EXACT, id_aa64pfr1_sme),
MRS_FIELD(ID_AA64PFR1, MPAM_frac, false, MRS_EXACT,
id_aa64pfr1_mpam_frac),
MRS_FIELD(ID_AA64PFR1, RAS_frac, false, MRS_EXACT,
id_aa64pfr1_ras_frac),
MRS_FIELD(ID_AA64PFR1, MTE, false, MRS_EXACT, id_aa64pfr1_mte),
MRS_FIELD_HWCAP(ID_AA64PFR1, SSBS, false, MRS_LOWER, id_aa64pfr1_ssbs,
id_aa64pfr1_ssbs_caps),

46
sys/arm64/include/armreg.h
View File

@ -1202,11 +1202,11 @@
/* ID_AA64PFR1_EL1 */
#define ID_AA64PFR1_EL1 MRS_REG(ID_AA64PFR1_EL1)
#define ID_AA64PFR1_EL1_op0 0x3
#define ID_AA64PFR1_EL1_op1 0x0
#define ID_AA64PFR1_EL1_CRn 0x0
#define ID_AA64PFR1_EL1_CRm 0x4
#define ID_AA64PFR1_EL1_op2 0x1
#define ID_AA64PFR1_EL1_op0 3
#define ID_AA64PFR1_EL1_op1 0
#define ID_AA64PFR1_EL1_CRn 0
#define ID_AA64PFR1_EL1_CRm 4
#define ID_AA64PFR1_EL1_op2 1
#define ID_AA64PFR1_BT_SHIFT 0
#define ID_AA64PFR1_BT_MASK (UL(0xf) << ID_AA64PFR1_BT_SHIFT)
#define ID_AA64PFR1_BT_VAL(x) ((x) & ID_AA64PFR1_BT_MASK)
@ -1222,13 +1222,41 @@
#define ID_AA64PFR1_MTE_MASK (UL(0xf) << ID_AA64PFR1_MTE_SHIFT)
#define ID_AA64PFR1_MTE_VAL(x) ((x) & ID_AA64PFR1_MTE_MASK)
#define ID_AA64PFR1_MTE_NONE (UL(0x0) << ID_AA64PFR1_MTE_SHIFT)
#define ID_AA64PFR1_MTE_IMPL_EL0 (UL(0x1) << ID_AA64PFR1_MTE_SHIFT)
#define ID_AA64PFR1_MTE_IMPL (UL(0x2) << ID_AA64PFR1_MTE_SHIFT)
#define ID_AA64PFR1_MTE_MTE (UL(0x1) << ID_AA64PFR1_MTE_SHIFT)
#define ID_AA64PFR1_MTE_MTE2 (UL(0x2) << ID_AA64PFR1_MTE_SHIFT)
#define ID_AA64PFR1_MTE_MTE3 (UL(0x3) << ID_AA64PFR1_MTE_SHIFT)
#define ID_AA64PFR1_RAS_frac_SHIFT 12
#define ID_AA64PFR1_RAS_frac_MASK (UL(0xf) << ID_AA64PFR1_RAS_frac_SHIFT)
#define ID_AA64PFR1_RAS_frac_VAL(x) ((x) & ID_AA64PFR1_RAS_frac_MASK)
#define ID_AA64PFR1_RAS_frac_V1 (UL(0x0) << ID_AA64PFR1_RAS_frac_SHIFT)
#define ID_AA64PFR1_RAS_frac_V2 (UL(0x1) << ID_AA64PFR1_RAS_frac_SHIFT)
#define ID_AA64PFR1_RAS_frac_p0 (UL(0x0) << ID_AA64PFR1_RAS_frac_SHIFT)
#define ID_AA64PFR1_RAS_frac_p1 (UL(0x1) << ID_AA64PFR1_RAS_frac_SHIFT)
#define ID_AA64PFR1_MPAM_frac_SHIFT 16
#define ID_AA64PFR1_MPAM_frac_MASK (UL(0xf) << ID_AA64PFR1_MPAM_frac_SHIFT)
#define ID_AA64PFR1_MPAM_frac_VAL(x) ((x) & ID_AA64PFR1_MPAM_frac_MASK)
#define ID_AA64PFR1_MPAM_frac_p0 (UL(0x0) << ID_AA64PFR1_MPAM_frac_SHIFT)
#define ID_AA64PFR1_MPAM_frac_p1 (UL(0x1) << ID_AA64PFR1_MPAM_frac_SHIFT)
#define ID_AA64PFR1_SME_SHIFT 24
#define ID_AA64PFR1_SME_MASK (UL(0xf) << ID_AA64PFR1_SME_SHIFT)
#define ID_AA64PFR1_SME_VAL(x) ((x) & ID_AA64PFR1_SME_MASK)
#define ID_AA64PFR1_SME_NONE (UL(0x0) << ID_AA64PFR1_SME_SHIFT)
#define ID_AA64PFR1_SME_SME (UL(0x1) << ID_AA64PFR1_SME_SHIFT)
#define ID_AA64PFR1_SME_SME2 (UL(0x2) << ID_AA64PFR1_SME_SHIFT)
#define ID_AA64PFR1_RNDR_trap_SHIFT 28
#define ID_AA64PFR1_RNDR_trap_MASK (UL(0xf) << ID_AA64PFR1_RNDR_trap_SHIFT)
#define ID_AA64PFR1_RNDR_trap_VAL(x) ((x) & ID_AA64PFR1_RNDR_trap_MASK)
#define ID_AA64PFR1_RNDR_trap_NONE (UL(0x0) << ID_AA64PFR1_RNDR_trap_SHIFT)
#define ID_AA64PFR1_RNDR_trap_IMPL (UL(0x1) << ID_AA64PFR1_RNDR_trap_SHIFT)
#define ID_AA64PFR1_CSV2_frac_SHIFT 32
#define ID_AA64PFR1_CSV2_frac_MASK (UL(0xf) << ID_AA64PFR1_CSV2_frac_SHIFT)
#define ID_AA64PFR1_CSV2_frac_VAL(x) ((x) & ID_AA64PFR1_CSV2_frac_MASK)
#define ID_AA64PFR1_CSV2_frac_p0 (UL(0x0) << ID_AA64PFR1_CSV2_frac_SHIFT)
#define ID_AA64PFR1_CSV2_frac_p1 (UL(0x1) << ID_AA64PFR1_CSV2_frac_SHIFT)
#define ID_AA64PFR1_CSV2_frac_p2 (UL(0x2) << ID_AA64PFR1_CSV2_frac_SHIFT)
#define ID_AA64PFR1_NMI_SHIFT 36
#define ID_AA64PFR1_NMI_MASK (UL(0xf) << ID_AA64PFR1_NMI_SHIFT)
#define ID_AA64PFR1_NMI_VAL(x) ((x) & ID_AA64PFR1_NMI_MASK)
#define ID_AA64PFR1_NMI_NONE (UL(0x0) << ID_AA64PFR1_NMI_SHIFT)
#define ID_AA64PFR1_NMI_IMPL (UL(0x1) << ID_AA64PFR1_NMI_SHIFT)
/* ID_AA64ZFR0_EL1 */
#define ID_AA64ZFR0_EL1 MRS_REG(ID_AA64ZFR0_EL1)