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Import device-tree files from Linux 5.16

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Sponsored by:   Beckhoff Automation GmbH & Co. KG
This commit is contained in:
Emmanuel Vadot 2022-08-10 14:27:16 +02:00
commit 8cc087a1ee
1173 changed files with 69985 additions and 6792 deletions
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20
sys/contrib/device-tree/Bindings/Makefile
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@ -9,6 +9,11 @@ DT_SCHEMA_MIN_VERSION = 2021.2.1
PHONY += check_dtschema_version
check_dtschema_version:
@which $(DT_DOC_CHECKER) >/dev/null || \
{ echo "Error: '$(DT_DOC_CHECKER)' not found!" >&2; \
echo "Ensure dtschema python package is installed and in your PATH." >&2; \
echo "Current PATH is:" >&2; \
echo "$$PATH" >&2; false; }
@{ echo $(DT_SCHEMA_MIN_VERSION); \
$(DT_DOC_CHECKER) --version 2>/dev/null || echo 0; } | sort -Vc >/dev/null || \
{ echo "ERROR: dtschema minimum version is v$(DT_SCHEMA_MIN_VERSION)" >&2; false; }
@ -22,13 +27,20 @@ $(obj)/%.example.dts: $(src)/%.yaml check_dtschema_version FORCE
# Use full schemas when checking %.example.dts
DT_TMP_SCHEMA := $(obj)/processed-schema-examples.json
find_cmd = find $(srctree)/$(src) \( -name '*.yaml' ! \
find_all_cmd = find $(srctree)/$(src) \( -name '*.yaml' ! \
-name 'processed-schema*' ! \
-name '*.example.dt.yaml' \)
ifeq ($(DT_SCHEMA_FILES),)
find_cmd = $(find_all_cmd)
else
find_cmd = echo $(addprefix $(srctree)/, $(DT_SCHEMA_FILES))
endif
quiet_cmd_yamllint = LINT $(src)
cmd_yamllint = ($(find_cmd) | \
xargs $(DT_SCHEMA_LINT) -f parsable -c $(srctree)/$(src)/.yamllint >&2) || true
xargs -n200 -P$$(nproc) \
$(DT_SCHEMA_LINT) -f parsable -c $(srctree)/$(src)/.yamllint >&2) || true
quiet_cmd_chk_bindings = CHKDT $@
cmd_chk_bindings = ($(find_cmd) | \
@ -38,7 +50,7 @@ quiet_cmd_mk_schema = SCHEMA $@
cmd_mk_schema = f=$$(mktemp) ; \
$(if $(DT_MK_SCHEMA_FLAGS), \
printf '%s\n' $(real-prereqs), \
$(find_cmd)) > $$f ; \
$(find_all_cmd)) > $$f ; \
$(DT_MK_SCHEMA) -j $(DT_MK_SCHEMA_FLAGS) @$$f > $@ ; \
rm -f $$f
@ -48,7 +60,7 @@ define rule_chkdt
$(call cmd,mk_schema)
endef
DT_DOCS = $(patsubst $(srctree)/%,%,$(shell $(find_cmd)))
DT_DOCS = $(patsubst $(srctree)/%,%,$(shell $(find_all_cmd)))
override DTC_FLAGS := \
-Wno-avoid_unnecessary_addr_size \

3
sys/contrib/device-tree/Bindings/arm/amlogic.yaml
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@ -86,6 +86,7 @@ properties:
- enum:
- amlogic,p281
- oranth,tx3-mini
- jethome,jethub-j80
- const: amlogic,s905w
- const: amlogic,meson-gxl
@ -133,6 +134,7 @@ properties:
items:
- enum:
- amlogic,s400
- jethome,jethub-j100
- const: amlogic,a113d
- const: amlogic,meson-axg
@ -141,6 +143,7 @@ properties:
- enum:
- amediatech,x96-max
- amlogic,u200
- radxa,zero
- seirobotics,sei510
- const: amlogic,g12a

216
sys/contrib/device-tree/Bindings/arm/arm,cci-400.yaml Normal file
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@ -0,0 +1,216 @@
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/arm,cci-400.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ARM CCI Cache Coherent Interconnect Device Tree Binding
maintainers:
- Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
description: >
ARM multi-cluster systems maintain intra-cluster coherency through a cache
coherent interconnect (CCI) that is capable of monitoring bus transactions
and manage coherency, TLB invalidations and memory barriers.
It allows snooping and distributed virtual memory message broadcast across
clusters, through memory mapped interface, with a global control register
space and multiple sets of interface control registers, one per slave
interface.
properties:
$nodename:
pattern: "^cci(@[0-9a-f]+)?$"
compatible:
enum:
- arm,cci-400
- arm,cci-500
- arm,cci-550
reg:
maxItems: 1
description: >
Specifies base physical address of CCI control registers common to all
interfaces.
"#address-cells": true
"#size-cells": true
ranges: true
patternProperties:
"^slave-if@[0-9a-f]+$":
type: object
properties:
compatible:
const: arm,cci-400-ctrl-if
interface-type:
enum:
- ace
- ace-lite
reg:
maxItems: 1
required:
- compatible
- interface-type
- reg
additionalProperties: false
"^pmu@[0-9a-f]+$":
type: object
properties:
compatible:
oneOf:
- const: arm,cci-400-pmu,r0
- const: arm,cci-400-pmu,r1
- const: arm,cci-400-pmu
deprecated: true
description: >
Permitted only where OS has secure access to CCI registers
- const: arm,cci-500-pmu,r0
- const: arm,cci-550-pmu,r0
interrupts:
minItems: 1
maxItems: 8
description: >
List of counter overflow interrupts, one per counter. The interrupts
must be specified starting with the cycle counter overflow interrupt,
followed by counter0 overflow interrupt, counter1 overflow
interrupt,... ,counterN overflow interrupt.
The CCI PMU has an interrupt signal for each counter. The number of
interrupts must be equal to the number of counters.
reg:
maxItems: 1
required:
- compatible
- interrupts
- reg
additionalProperties: false
required:
- "#address-cells"
- "#size-cells"
- compatible
- ranges
- reg
additionalProperties: false
examples:
- |
/ {
#address-cells = <2>;
#size-cells = <2>;
compatible = "arm,vexpress,v2p-ca15_a7", "arm,vexpress";
model = "V2P-CA15_CA7";
arm,hbi = <0x249>;
interrupt-parent = <&gic>;
/*
* This CCI node corresponds to a CCI component whose control
* registers sits at address 0x000000002c090000.
*
* CCI slave interface @0x000000002c091000 is connected to dma
* controller dma0.
*
* CCI slave interface @0x000000002c094000 is connected to CPUs
* {CPU0, CPU1};
*
* CCI slave interface @0x000000002c095000 is connected to CPUs
* {CPU2, CPU3};
*/
cpus {
#size-cells = <0>;
#address-cells = <1>;
CPU0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a15";
cci-control-port = <&cci_control1>;
reg = <0x0>;
};
CPU1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a15";
cci-control-port = <&cci_control1>;
reg = <0x1>;
};
CPU2: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a7";
cci-control-port = <&cci_control2>;
reg = <0x100>;
};
CPU3: cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a7";
cci-control-port = <&cci_control2>;
reg = <0x101>;
};
};
dma0: dma@3000000 {
/* compatible = "arm,pl330", "arm,primecell"; */
cci-control-port = <&cci_control0>;
reg = <0x0 0x3000000 0x0 0x1000>;
interrupts = <10>;
#dma-cells = <1>;
#dma-channels = <8>;
#dma-requests = <32>;
};
cci@2c090000 {
compatible = "arm,cci-400";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x0 0x2c090000 0 0x1000>;
ranges = <0x0 0x0 0x2c090000 0x10000>;
cci_control0: slave-if@1000 {
compatible = "arm,cci-400-ctrl-if";
interface-type = "ace-lite";
reg = <0x1000 0x1000>;
};
cci_control1: slave-if@4000 {
compatible = "arm,cci-400-ctrl-if";
interface-type = "ace";
reg = <0x4000 0x1000>;
};
cci_control2: slave-if@5000 {
compatible = "arm,cci-400-ctrl-if";
interface-type = "ace";
reg = <0x5000 0x1000>;
};
pmu@9000 {
compatible = "arm,cci-400-pmu";
reg = <0x9000 0x5000>;
interrupts = <0 101 4>,
<0 102 4>,
<0 103 4>,
<0 104 4>,
<0 105 4>;
};
};
};
...

46
sys/contrib/device-tree/Bindings/arm/arm,vexpress-juno.yaml
View File

@ -119,22 +119,6 @@ properties:
- const: arm,foundation-aarch64
- const: arm,vexpress
arm,hbi:
$ref: '/schemas/types.yaml#/definitions/uint32'
description: This indicates the ARM HBI (Hardware Board ID), this is
ARM's unique board model ID, visible on the PCB's silkscreen.
arm,vexpress,site:
description: As Versatile Express can be configured in number of physically
different setups, the device tree should describe platform topology.
For this reason the root node and main motherboard node must define this
property, describing the physical location of the children nodes.
0 means motherboard site, while 1 and 2 are daughterboard sites, and
0xf means "sisterboard" which is the site containing the main CPU tile.
$ref: '/schemas/types.yaml#/definitions/uint32'
minimum: 0
maximum: 15
arm,vexpress,position:
description: When daughterboards are stacked on one site, their position
in the stack be be described this attribute.
@ -154,9 +138,9 @@ patternProperties:
description: Static Memory Bus (SMB) node, if this exists it describes
the connection between the motherboard and any tiles. Sometimes the
compatible is placed directly under this node, sometimes it is placed
in a subnode named "motherboard". Sometimes the compatible includes
in a subnode named "motherboard-bus". Sometimes the compatible includes
"arm,vexpress,v2?-p1" sometimes (on software models) is is just
"simple-bus". If the compatible is placed in the "motherboard" node,
"simple-bus". If the compatible is placed in the "motherboard-bus" node,
it is stricter and always has two compatibles.
type: object
$ref: '/schemas/simple-bus.yaml'
@ -170,7 +154,9 @@ patternProperties:
- arm,vexpress,v2p-p1
- const: simple-bus
- const: simple-bus
motherboard:
patternProperties:
'^motherboard-bus@':
type: object
description: The motherboard description provides a single "motherboard"
node using 2 address cells corresponding to the Static Memory Bus
@ -183,6 +169,8 @@ patternProperties:
const: 2
"#size-cells":
const: 1
ranges: true
compatible:
items:
- enum:
@ -196,8 +184,28 @@ patternProperties:
- rs1
- rs2
arm,hbi:
$ref: '/schemas/types.yaml#/definitions/uint32'
description: This indicates the ARM HBI (Hardware Board ID), this is
ARM's unique board model ID, visible on the PCB's silkscreen.
arm,vexpress,site:
description: As Versatile Express can be configured in number of physically
different setups, the device tree should describe platform topology.
For this reason the root node and main motherboard node must define this
property, describing the physical location of the children nodes.
0 means motherboard site, while 1 and 2 are daughterboard sites, and
0xf means "sisterboard" which is the site containing the main CPU tile.
$ref: '/schemas/types.yaml#/definitions/uint32'
minimum: 0
maximum: 15
required:
- compatible
additionalProperties:
type: object
required:
- compatible

24
sys/contrib/device-tree/Bindings/arm/atmel-at91.yaml
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@ -126,6 +126,18 @@ properties:
- const: atmel,sama5d3
- const: atmel,sama5
- description: CalAmp LMU5000 board
items:
- const: calamp,lmu5000
- const: atmel,at91sam9g20
- const: atmel,at91sam9
- description: Exegin Q5xR5 board
items:
- const: exegin,q5xr5
- const: atmel,at91sam9g20
- const: atmel,at91sam9
- items:
- enum:
- atmel,sama5d31
@ -150,6 +162,18 @@ properties:
- const: microchip,sama7g5
- const: microchip,sama7
- description: Microchip LAN9662 PCB8291 Evaluation Board.
items:
- const: microchip,lan9662-pcb8291
- const: microchip,lan9662
- const: microchip,lan966
- description: Microchip LAN9668 PCB8290 Evaluation Board.
items:
- const: microchip,lan9668-pcb8290
- const: microchip,lan9668
- const: microchip,lan966
- items:
- enum:
- atmel,sams70j19

1
sys/contrib/device-tree/Bindings/arm/bcm/bcm2835.yaml
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@ -19,6 +19,7 @@ properties:
items:
- enum:
- raspberrypi,400
- raspberrypi,4-compute-module
- raspberrypi,4-model-b
- const: brcm,bcm2711

65
sys/contrib/device-tree/Bindings/arm/bcm/brcm,nsp.yaml
View File

@ -22,16 +22,61 @@ properties:
$nodename:
const: '/'
compatible:
items:
- enum:
- brcm,bcm58522
- brcm,bcm58525
- brcm,bcm58535
- brcm,bcm58622
- brcm,bcm58623
- brcm,bcm58625
- brcm,bcm88312
- const: brcm,nsp
oneOf:
- description: BCM58522 based boards
items:
- enum:
- brcm,bcm958522er
- const: brcm,bcm58522
- const: brcm,nsp
- description: BCM58525 based boards
items:
- enum:
- brcm,bcm958525er
- brcm,bcm958525xmc
- const: brcm,bcm58525
- const: brcm,nsp
- description: BCM58535 based boards
items:
- const: brcm,bcm58535
- const: brcm,nsp
- description: BCM58622 based boards
items:
- enum:
- brcm,bcm958622hr
- const: brcm,bcm58622
- const: brcm,nsp
- description: BCM58623 based boards
items:
- enum:
- brcm,bcm958623hr
- const: brcm,bcm58623
- const: brcm,nsp
- description: BCM58625 based boards
items:
- enum:
- brcm,bcm958625hr
- brcm,bcm958625k
- meraki,mx64
- meraki,mx64-a0
- meraki,mx64w
- meraki,mx64w-a0
- meraki,mx65
- meraki,mx65w
- const: brcm,bcm58625
- const: brcm,nsp
- description: BCM88312 based boards
items:
- enum:
- brcm,bcm988312hr
- const: brcm,bcm88312
- const: brcm,nsp
additionalProperties: true

38
sys/contrib/device-tree/Bindings/arm/cci-control-port.yaml Normal file
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@ -0,0 +1,38 @@
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/cci-control-port.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: CCI Interconnect Bus Masters binding
maintainers:
- Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
description: |
Masters in the device tree connected to a CCI port (inclusive of CPUs
and their cpu nodes).
select: true
properties:
cci-control-port:
$ref: /schemas/types.yaml#/definitions/phandle
additionalProperties: true
examples:
- |
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
compatible = "arm,cortex-a15";
device_type = "cpu";
cci-control-port = <&cci_control1>;
reg = <0>;
};
};
...

5
sys/contrib/device-tree/Bindings/arm/coresight.txt
View File

@ -127,6 +127,11 @@ its hardware characteristcs.
* arm,scatter-gather: boolean. Indicates that the TMC-ETR can safely
use the SG mode on this system.
* arm,max-burst-size: The maximum burst size initiated by TMC on the
AXI master interface. The burst size can be in the range [0..15],
the setting supports one data transfer per burst up to a maximum of
16 data transfers per burst.
* Optional property for CATU :
* interrupts : Exactly one SPI may be listed for reporting the address
error

10
sys/contrib/device-tree/Bindings/arm/cpus.yaml
View File

@ -171,6 +171,8 @@ properties:
- qcom,kryo385
- qcom,kryo468
- qcom,kryo485
- qcom,kryo560
- qcom,kryo570
- qcom,kryo685
- qcom,scorpion
@ -209,6 +211,9 @@ properties:
- qcom,gcc-msm8660
- qcom,kpss-acc-v1
- qcom,kpss-acc-v2
- qcom,msm8226-smp
# Only valid on ARM 32-bit, see above for ARM v8 64-bit
- qcom,msm8916-smp
- renesas,apmu
- renesas,r9a06g032-smp
- rockchip,rk3036-smp
@ -240,6 +245,8 @@ properties:
DMIPS/MHz, relative to highest capacity-dmips-mhz
in the system.
cci-control-port: true
dynamic-power-coefficient:
$ref: '/schemas/types.yaml#/definitions/uint32'
description:
@ -293,7 +300,8 @@ properties:
Specifies the ACC* node associated with this CPU.
Required for systems that have an "enable-method" property
value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2"
value of "qcom,kpss-acc-v1", "qcom,kpss-acc-v2", "qcom,msm8226-smp" or
"qcom,msm8916-smp".
* arm/msm/qcom,kpss-acc.txt

46
sys/contrib/device-tree/Bindings/arm/firmware/tlm,trusted-foundations.yaml Normal file
View File

@ -0,0 +1,46 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/arm/firmware/tlm,trusted-foundations.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Trusted Foundations
description: |
Boards that use the Trusted Foundations secure monitor can signal its
presence by declaring a node compatible under the /firmware/ node
maintainers:
- Stephen Warren <swarren@nvidia.com>
properties:
$nodename:
const: trusted-foundations
compatible:
const: tlm,trusted-foundations
tlm,version-major:
$ref: /schemas/types.yaml#/definitions/uint32
description: major version number of Trusted Foundations firmware
tlm,version-minor:
$ref: /schemas/types.yaml#/definitions/uint32
description: minor version number of Trusted Foundations firmware
required:
- compatible
- tlm,version-major
- tlm,version-minor
additionalProperties: false
examples:
- |
firmware {
trusted-foundations {
compatible = "tlm,trusted-foundations";
tlm,version-major = <2>;
tlm,version-minor = <8>;
};
};

99
sys/contrib/device-tree/Bindings/arm/fsl.yaml
View File

@ -235,7 +235,7 @@ properties:
- technexion,imx6q-pico-pi # TechNexion i.MX6Q Pico-Pi
- technologic,imx6q-ts4900
- technologic,imx6q-ts7970
- toradex,apalis_imx6q # Apalis iMX6 Module
- toradex,apalis_imx6q # Apalis iMX6 Modules
- udoo,imx6q-udoo # Udoo i.MX6 Quad Board
- uniwest,imx6q-evi # Uniwest Evi
- variscite,dt6customboard
@ -314,18 +314,12 @@ properties:
- const: phytec,imx6q-pfla02 # PHYTEC phyFLEX-i.MX6 Quad
- const: fsl,imx6q
- description: i.MX6Q Boards with Toradex Apalis iMX6Q/D Module
- description: i.MX6Q Boards with Toradex Apalis iMX6Q/D Modules
items:
- enum:
- toradex,apalis_imx6q-ixora # Apalis iMX6Q/D Module on Ixora Carrier Board
- toradex,apalis_imx6q-eval # Apalis iMX6Q/D Module on Apalis Evaluation Board
- const: toradex,apalis_imx6q
- const: fsl,imx6q
- description: i.MX6Q Toradex Apalis iMX6Q/D Module on Ixora Carrier Board V1.1
items:
- const: toradex,apalis_imx6q-ixora-v1.1
- const: toradex,apalis_imx6q-ixora
- toradex,apalis_imx6q-ixora # Apalis iMX6Q/D Module on Ixora Carrier Board
- toradex,apalis_imx6q-ixora-v1.1 # Apalis iMX6Q/D Module on Ixora V1.1 Carrier Board
- toradex,apalis_imx6q-eval # Apalis iMX6Q/D Module on Apalis Evaluation Board
- const: toradex,apalis_imx6q
- const: fsl,imx6q
@ -393,6 +387,8 @@ properties:
- technexion,imx6dl-pico-pi # TechNexion i.MX6DL Pico-Pi
- technologic,imx6dl-ts4900
- technologic,imx6dl-ts7970
- toradex,colibri_imx6dl # Colibri iMX6 Modules
- toradex,colibri_imx6dl-v1_1 # Colibri iMX6 V1.1 Modules
- udoo,imx6dl-udoo # Udoo i.MX6 Dual-lite Board
- vdl,lanmcu # Van der Laan LANMCU board
- wand,imx6dl-wandboard # Wandboard i.MX6 Dual Lite Board
@ -466,20 +462,18 @@ properties:
- const: phytec,imx6dl-pfla02 # PHYTEC phyFLEX-i.MX6 Quad
- const: fsl,imx6dl
- description: i.MX6DL Toradex Colibri iMX6 Module on Colibri
Evaluation Board V3
- description: i.MX6DL Boards with Toradex Colibri iMX6DL/S Modules
items:
- const: toradex,colibri_imx6dl-eval-v3
- const: toradex,colibri_imx6dl # Colibri iMX6 Module
- enum:
- toradex,colibri_imx6dl-eval-v3 # Colibri iMX6DL/S Module on Colibri Evaluation Board V3
- const: toradex,colibri_imx6dl # Colibri iMX6DL/S Module
- const: fsl,imx6dl
- description: i.MX6DL Toradex Colibri iMX6 Module V1.1 on Colibri
Evaluation Board V3
- description: i.MX6DL Boards with Toradex Colibri iMX6DL/S V1.1 Modules
items:
- const: toradex,colibri_imx6dl-v1_1-eval-v3
- const: toradex,colibri_imx6dl-v1_1 # Colibri iMX6 Module V1.1
- const: toradex,colibri_imx6dl-eval-v3
- const: toradex,colibri_imx6dl # Colibri iMX6 Module
- enum:
- toradex,colibri_imx6dl-v1_1-eval-v3 # Colibri iMX6DL/S V1.1 M. on Colibri Evaluation Board V3
- const: toradex,colibri_imx6dl-v1_1 # Colibri iMX6DL/S V1.1 Module
- const: fsl,imx6dl
- description: i.MX6S DHCOM DRC02 Board
@ -494,6 +488,7 @@ properties:
- fsl,imx6sl-evk # i.MX6 SoloLite EVK Board
- kobo,tolino-shine2hd
- kobo,tolino-shine3
- kobo,tolino-vision5
- revotics,imx6sl-warp # Revotics WaRP Board
- const: fsl,imx6sl
@ -502,6 +497,7 @@ properties:
- enum:
- fsl,imx6sll-evk
- kobo,clarahd
- kobo,librah2o
- const: fsl,imx6sll
- description: i.MX6SX based Boards
@ -586,8 +582,9 @@ properties:
- fsl,imx6ull-14x14-evk # i.MX6 UltraLiteLite 14x14 EVK Board
- kontron,imx6ull-n6411-som # Kontron N6411 SOM
- myir,imx6ull-mys-6ulx-eval # MYiR Tech iMX6ULL Evaluation Board
- toradex,colibri-imx6ull-eval # Colibri iMX6ULL Module on Colibri Eval Board
- toradex,colibri-imx6ull-wifi-eval # Colibri iMX6ULL Wi-Fi / BT Module on Colibri Eval Board
- toradex,colibri-imx6ull # Colibri iMX6ULL Modules
- toradex,colibri-imx6ull-emmc # Colibri iMX6ULL 1GB (eMMC) Module
- toradex,colibri-imx6ull-wifi # Colibri iMX6ULL Wi-Fi / BT Modules
- const: fsl,imx6ull
- description: i.MX6ULL Armadeus Systems OPOS6ULDev Board
@ -605,6 +602,27 @@ properties:
- const: phytec,imx6ull-pcl063 # PHYTEC phyCORE-i.MX 6ULL
- const: fsl,imx6ull
- description: i.MX6ULL Boards with Toradex Colibri iMX6ULL Modules
items:
- enum:
- toradex,colibri-imx6ull-eval # Colibri iMX6ULL Module on Colibri Evaluation Board
- const: toradex,colibri-imx6ull # Colibri iMX6ULL Module
- const: fsl,imx6dl
- description: i.MX6ULL Boards with Toradex Colibri iMX6ULL 1GB (eMMC) Module
items:
- enum:
- toradex,colibri-imx6ull-emmc-eval # Colibri iMX6ULL 1GB (eMMC) M. on Colibri Evaluation Board
- const: toradex,colibri-imx6ull-emmc # Colibri iMX6ULL 1GB (eMMC) Module
- const: fsl,imx6dl
- description: i.MX6ULL Boards with Toradex Colibri iMX6ULL Wi-Fi / BT Modules
items:
- enum:
- toradex,colibri-imx6ull-wifi-eval # Colibri iMX6ULL Wi-Fi / BT M. on Colibri Evaluation Board
- const: toradex,colibri-imx6ull-wifi # Colibri iMX6ULL Wi-Fi / BT Module
- const: fsl,imx6dl
- description: Kontron N6411 S Board
items:
- const: kontron,imx6ull-n6411-s
@ -622,6 +640,7 @@ properties:
items:
- enum:
- element14,imx7s-warp # Element14 Warp i.MX7 Board
- toradex,colibri-imx7s # Colibri iMX7S Module
- const: fsl,imx7s
- description: i.MX7S Boards with Toradex Colibri iMX7S Module
@ -653,15 +672,8 @@ properties:
- technexion,imx7d-pico-hobbit # TechNexion i.MX7D Pico-Hobbit
- technexion,imx7d-pico-nymph # TechNexion i.MX7D Pico-Nymph
- technexion,imx7d-pico-pi # TechNexion i.MX7D Pico-Pi
- toradex,colibri-imx7d # Colibri iMX7 Dual Module
- toradex,colibri-imx7d-aster # Colibri iMX7 Dual Module on Aster Carrier Board
- toradex,colibri-imx7d-emmc # Colibri iMX7 Dual 1GB (eMMC) Module
- toradex,colibri-imx7d-emmc-aster # Colibri iMX7 Dual 1GB (eMMC) Module on
# Aster Carrier Board
- toradex,colibri-imx7d-emmc-eval-v3 # Colibri iMX7 Dual 1GB (eMMC) Module on
# Colibri Evaluation Board V3
- toradex,colibri-imx7d-eval-v3 # Colibri iMX7 Dual Module on
# Colibri Evaluation Board V3
- toradex,colibri-imx7d # Colibri iMX7D Module
- toradex,colibri-imx7d-emmc # Colibri iMX7D 1GB (eMMC) Module
- zii,imx7d-rmu2 # ZII RMU2 Board
- zii,imx7d-rpu2 # ZII RPU2 Board
- const: fsl,imx7d
@ -686,12 +698,12 @@ properties:
- description: i.MX7D Boards with Toradex Colibri i.MX7D Module
items:
- enum:
- toradex,colibri-imx7d-aster # Module on Aster Carrier Board
- toradex,colibri-imx7d-eval-v3 # Module on Colibri Evaluation Board V3
- toradex,colibri-imx7d-aster # Colibri iMX7D Module on Aster Carrier Board
- toradex,colibri-imx7d-eval-v3 # Colibri iMX7D Module on Colibri Evaluation Board V3
- const: toradex,colibri-imx7d
- const: fsl,imx7d
- description: i.MX7D Boards with Toradex Colibri i.MX7D eMMC Module
- description: i.MX7D Boards with Toradex Colibri i.MX7D 1GB (eMMC) Module
items:
- enum:
- toradex,colibri-imx7d-emmc-aster # Module on Aster Carrier Board
@ -812,10 +824,10 @@ properties:
- enum:
- einfochips,imx8qxp-ai_ml # i.MX8QXP AI_ML Board
- fsl,imx8qxp-mek # i.MX8QXP MEK Board
- toradex,colibri-imx8x # Colibri iMX8X Module
- toradex,colibri-imx8x # Colibri iMX8X Modules
- const: fsl,imx8qxp
- description: Toradex Colibri i.MX8 Evaluation Board
- description: i.MX8QXP Boards with Toradex Coilbri iMX8X Modules
items:
- enum:
- toradex,colibri-imx8x-eval-v3 # Colibri iMX8X Module on Colibri Evaluation Board V3
@ -847,9 +859,10 @@ properties:
- description: VF610 based Boards
items:
- enum:
- fsl,vf610-twr # VF610 Tower Board
- lwn,bk4 # Liebherr BK4 controller
- phytec,vf610-cosmic # PHYTEC Cosmic/Cosmic+ Board
- fsl,vf610-twr # VF610 Tower Board
- toradex,vf610-colibri_vf61 # Colibri VF61 Modules
- const: fsl,vf610
- description: Toradex Colibri VF61 Module on Colibri Evaluation Board
@ -886,6 +899,7 @@ properties:
- enum:
- fsl,ls1021a-moxa-uc-8410a
- fsl,ls1021a-qds
- fsl,ls1021a-tsn
- fsl,ls1021a-twr
- const: fsl,ls1021a
@ -977,6 +991,8 @@ properties:
- description: LX2160A based Boards
items:
- enum:
- fsl,lx2160a-bluebox3
- fsl,lx2160a-bluebox3-rev-a
- fsl,lx2160a-qds
- fsl,lx2160a-rdb
- fsl,lx2162a-qds
@ -990,6 +1006,13 @@ properties:
- const: solidrun,lx2160a-cex7
- const: fsl,lx2160a
- description: S32G2 based Boards
items:
- enum:
- nxp,s32g274a-evb
- nxp,s32g274a-rdb2
- const: nxp,s32g2
- description: S32V234 based Boards
items:
- enum:

1
sys/contrib/device-tree/Bindings/arm/mediatek.yaml
View File

@ -32,6 +32,7 @@ properties:
- const: mediatek,mt6580
- items:
- enum:
- fairphone,fp1
- mundoreader,bq-aquaris5
- const: mediatek,mt6589
- items:

4
sys/contrib/device-tree/Bindings/arm/mediatek/mediatek,mmsys.yaml
View File

@ -43,6 +43,9 @@ properties:
"#clock-cells":
const: 1
'#reset-cells':
const: 1
required:
- compatible
- reg
@ -56,4 +59,5 @@ examples:
compatible = "mediatek,mt8173-mmsys", "syscon";
reg = <0x14000000 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};

254
sys/contrib/device-tree/Bindings/arm/mediatek/mediatek,mt8195-clock.yaml Normal file
View File

@ -0,0 +1,254 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8195-clock.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: MediaTek Functional Clock Controller for MT8195
maintainers:
- Chun-Jie Chen <chun-jie.chen@mediatek.com>
description:
The clock architecture in Mediatek like below
PLLs -->
dividers -->
muxes
-->
clock gate
The devices except apusys_pll provide clock gate control in different IP blocks.
The apusys_pll provides Plls which generated from SoC 26m for AI Processing Unit.
properties:
compatible:
items:
- enum:
- mediatek,mt8195-scp_adsp
- mediatek,mt8195-imp_iic_wrap_s
- mediatek,mt8195-imp_iic_wrap_w
- mediatek,mt8195-mfgcfg
- mediatek,mt8195-vppsys0
- mediatek,mt8195-wpesys
- mediatek,mt8195-wpesys_vpp0
- mediatek,mt8195-wpesys_vpp1
- mediatek,mt8195-vppsys1
- mediatek,mt8195-imgsys
- mediatek,mt8195-imgsys1_dip_top
- mediatek,mt8195-imgsys1_dip_nr
- mediatek,mt8195-imgsys1_wpe
- mediatek,mt8195-ipesys
- mediatek,mt8195-camsys
- mediatek,mt8195-camsys_rawa
- mediatek,mt8195-camsys_yuva
- mediatek,mt8195-camsys_rawb
- mediatek,mt8195-camsys_yuvb
- mediatek,mt8195-camsys_mraw
- mediatek,mt8195-ccusys
- mediatek,mt8195-vdecsys_soc
- mediatek,mt8195-vdecsys
- mediatek,mt8195-vdecsys_core1
- mediatek,mt8195-vencsys
- mediatek,mt8195-vencsys_core1
- mediatek,mt8195-apusys_pll
reg:
maxItems: 1
'#clock-cells':
const: 1
required:
- compatible
- reg
additionalProperties: false
examples:
- |
scp_adsp: clock-controller@10720000 {
compatible = "mediatek,mt8195-scp_adsp";
reg = <0x10720000 0x1000>;
#clock-cells = <1>;
};
- |
imp_iic_wrap_s: clock-controller@11d03000 {
compatible = "mediatek,mt8195-imp_iic_wrap_s";
reg = <0x11d03000 0x1000>;
#clock-cells = <1>;
};
- |
imp_iic_wrap_w: clock-controller@11e05000 {
compatible = "mediatek,mt8195-imp_iic_wrap_w";
reg = <0x11e05000 0x1000>;
#clock-cells = <1>;
};
- |
mfgcfg: clock-controller@13fbf000 {
compatible = "mediatek,mt8195-mfgcfg";
reg = <0x13fbf000 0x1000>;
#clock-cells = <1>;
};
- |
vppsys0: clock-controller@14000000 {
compatible = "mediatek,mt8195-vppsys0";
reg = <0x14000000 0x1000>;
#clock-cells = <1>;
};
- |
wpesys: clock-controller@14e00000 {
compatible = "mediatek,mt8195-wpesys";
reg = <0x14e00000 0x1000>;
#clock-cells = <1>;
};
- |
wpesys_vpp0: clock-controller@14e02000 {
compatible = "mediatek,mt8195-wpesys_vpp0";
reg = <0x14e02000 0x1000>;
#clock-cells = <1>;
};
- |
wpesys_vpp1: clock-controller@14e03000 {
compatible = "mediatek,mt8195-wpesys_vpp1";
reg = <0x14e03000 0x1000>;
#clock-cells = <1>;
};
- |
vppsys1: clock-controller@14f00000 {
compatible = "mediatek,mt8195-vppsys1";
reg = <0x14f00000 0x1000>;
#clock-cells = <1>;
};
- |
imgsys: clock-controller@15000000 {
compatible = "mediatek,mt8195-imgsys";
reg = <0x15000000 0x1000>;
#clock-cells = <1>;
};
- |
imgsys1_dip_top: clock-controller@15110000 {
compatible = "mediatek,mt8195-imgsys1_dip_top";
reg = <0x15110000 0x1000>;
#clock-cells = <1>;
};
- |
imgsys1_dip_nr: clock-controller@15130000 {
compatible = "mediatek,mt8195-imgsys1_dip_nr";
reg = <0x15130000 0x1000>;
#clock-cells = <1>;
};
- |
imgsys1_wpe: clock-controller@15220000 {
compatible = "mediatek,mt8195-imgsys1_wpe";
reg = <0x15220000 0x1000>;
#clock-cells = <1>;
};
- |
ipesys: clock-controller@15330000 {
compatible = "mediatek,mt8195-ipesys";
reg = <0x15330000 0x1000>;
#clock-cells = <1>;
};
- |
camsys: clock-controller@16000000 {
compatible = "mediatek,mt8195-camsys";
reg = <0x16000000 0x1000>;
#clock-cells = <1>;
};
- |
camsys_rawa: clock-controller@1604f000 {
compatible = "mediatek,mt8195-camsys_rawa";
reg = <0x1604f000 0x1000>;
#clock-cells = <1>;
};
- |
camsys_yuva: clock-controller@1606f000 {
compatible = "mediatek,mt8195-camsys_yuva";
reg = <0x1606f000 0x1000>;
#clock-cells = <1>;
};
- |
camsys_rawb: clock-controller@1608f000 {
compatible = "mediatek,mt8195-camsys_rawb";
reg = <0x1608f000 0x1000>;
#clock-cells = <1>;
};
- |
camsys_yuvb: clock-controller@160af000 {
compatible = "mediatek,mt8195-camsys_yuvb";
reg = <0x160af000 0x1000>;
#clock-cells = <1>;
};
- |
camsys_mraw: clock-controller@16140000 {
compatible = "mediatek,mt8195-camsys_mraw";
reg = <0x16140000 0x1000>;
#clock-cells = <1>;
};
- |
ccusys: clock-controller@17200000 {
compatible = "mediatek,mt8195-ccusys";
reg = <0x17200000 0x1000>;
#clock-cells = <1>;
};
- |
vdecsys_soc: clock-controller@1800f000 {
compatible = "mediatek,mt8195-vdecsys_soc";
reg = <0x1800f000 0x1000>;
#clock-cells = <1>;
};
- |
vdecsys: clock-controller@1802f000 {
compatible = "mediatek,mt8195-vdecsys";
reg = <0x1802f000 0x1000>;
#clock-cells = <1>;
};
- |
vdecsys_core1: clock-controller@1803f000 {
compatible = "mediatek,mt8195-vdecsys_core1";
reg = <0x1803f000 0x1000>;
#clock-cells = <1>;
};
- |
vencsys: clock-controller@1a000000 {
compatible = "mediatek,mt8195-vencsys";
reg = <0x1a000000 0x1000>;
#clock-cells = <1>;
};
- |
vencsys_core1: clock-controller@1b000000 {
compatible = "mediatek,mt8195-vencsys_core1";
reg = <0x1b000000 0x1000>;
#clock-cells = <1>;
};
- |
apusys_pll: clock-controller@190f3000 {
compatible = "mediatek,mt8195-apusys_pll";
reg = <0x190f3000 0x1000>;
#clock-cells = <1>;
};

73
sys/contrib/device-tree/Bindings/arm/mediatek/mediatek,mt8195-sys-clock.yaml Normal file
View File

@ -0,0 +1,73 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8195-sys-clock.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: MediaTek System Clock Controller for MT8195
maintainers:
- Chun-Jie Chen <chun-jie.chen@mediatek.com>
description:
The clock architecture in Mediatek like below
PLLs -->
dividers -->
muxes
-->
clock gate
The apmixedsys provides most of PLLs which generated from SoC 26m.
The topckgen provides dividers and muxes which provide the clock source to other IP blocks.
The infracfg_ao and pericfg_ao provides clock gate in peripheral and infrastructure IP blocks.
properties:
compatible:
items:
- enum:
- mediatek,mt8195-topckgen
- mediatek,mt8195-infracfg_ao
- mediatek,mt8195-apmixedsys
- mediatek,mt8195-pericfg_ao
- const: syscon
reg:
maxItems: 1
'#clock-cells':
const: 1
required:
- compatible
- reg
additionalProperties: false
examples:
- |
topckgen: syscon@10000000 {
compatible = "mediatek,mt8195-topckgen", "syscon";
reg = <0x10000000 0x1000>;
#clock-cells = <1>;
};
- |
infracfg_ao: syscon@10001000 {
compatible = "mediatek,mt8195-infracfg_ao", "syscon";
reg = <0x10001000 0x1000>;
#clock-cells = <1>;
};
- |
apmixedsys: syscon@1000c000 {
compatible = "mediatek,mt8195-apmixedsys", "syscon";
reg = <0x1000c000 0x1000>;
#clock-cells = <1>;
};
- |
pericfg_ao: syscon@11003000 {
compatible = "mediatek,mt8195-pericfg_ao", "syscon";
reg = <0x11003000 0x1000>;
#clock-cells = <1>;
};

23
sys/contrib/device-tree/Bindings/arm/qcom.yaml
View File

@ -25,6 +25,7 @@ description: |
The 'SoC' element must be one of the following strings:
apq8016
apq8026
apq8074
apq8084
apq8096
@ -44,6 +45,8 @@ description: |
sdm660
sdm845
sdx55
sdx65
sm7225
sm8150
sm8250
sm8350
@ -94,6 +97,14 @@ properties:
- items:
- enum:
- lg,lenok
- const: qcom,apq8026
- items:
- enum:
- asus,nexus7-flo
- lg,nexus4-mako
- sony,xperia-yuga
- qcom,apq8064-cm-qs600
- qcom,apq8064-ifc6410
- const: qcom,apq8064
@ -129,6 +140,7 @@ properties:
- enum:
- fairphone,fp2
- lge,hammerhead
- samsung,klte
- sony,xperia-amami
- sony,xperia-castor
- sony,xperia-honami
@ -163,6 +175,7 @@ properties:
- items:
- enum:
- qcom,ipq4019-ap-dk01.1-c1
- qcom,ipq4019-ap-dk04.1-c3
- qcom,ipq4019-ap-dk07.1-c1
- qcom,ipq4019-ap-dk07.1-c2
@ -206,6 +219,11 @@ properties:
- qcom,sdx55-t55
- const: qcom,sdx55
- items:
- enum:
- qcom,sdx65-mtp
- const: qcom,sdx65
- items:
- enum:
- qcom,ipq6018-cp01
@ -217,6 +235,11 @@ properties:
- qcom,sa8155p-adp
- const: qcom,sa8155p
- items:
- enum:
- fairphone,fp4
- const: qcom,sm7225
- items:
- enum:
- qcom,sm8150-mtp

61
sys/contrib/device-tree/Bindings/arm/renesas.yaml
View File

@ -255,12 +255,19 @@ properties:
- enum:
- renesas,h3ulcb
- renesas,m3ulcb
- renesas,m3nulcb
- enum:
- renesas,r8a779m0
- renesas,r8a779m1
- renesas,r8a779m2
- renesas,r8a779m3
- renesas,r8a779m4
- renesas,r8a779m5
- renesas,r8a779m8
- enum:
- renesas,r8a7795
- renesas,r8a77961
- renesas,r8a77965
- description: R-Car M3-N (R8A77965)
items:
@ -308,6 +315,14 @@ properties:
- const: renesas,falcon-cpu
- const: renesas,r8a779a0
- description: R-Car H3e (R8A779M0)
items:
- enum:
- renesas,h3ulcb # H3ULCB (R-Car Starter Kit Premier)
- renesas,salvator-xs # Salvator-XS (Salvator-X 2nd version)
- const: renesas,r8a779m0
- const: renesas,r8a7795
- description: R-Car H3e-2G (R8A779M1)
items:
- enum:
@ -316,6 +331,14 @@ properties:
- const: renesas,r8a779m1
- const: renesas,r8a7795
- description: R-Car M3e (R8A779M2)
items:
- enum:
- renesas,m3ulcb # M3ULCB (R-Car Starter Kit Pro)
- renesas,salvator-xs # Salvator-XS (Salvator-X 2nd version)
- const: renesas,r8a779m2
- const: renesas,r8a77961
- description: R-Car M3e-2G (R8A779M3)
items:
- enum:
@ -324,6 +347,44 @@ properties:
- const: renesas,r8a779m3
- const: renesas,r8a77961
- description: R-Car M3Ne (R8A779M4)
items:
- enum:
- renesas,m3nulcb # M3NULCB (R-Car Starter Kit Pro)
- renesas,salvator-xs # Salvator-XS (Salvator-X 2nd version)
- const: renesas,r8a779m4
- const: renesas,r8a77965
- description: R-Car M3Ne-2G (R8A779M5)
items:
- enum:
- renesas,m3nulcb # M3NULCB (R-Car Starter Kit Pro)
- renesas,salvator-xs # Salvator-XS (Salvator-X 2nd version)
- const: renesas,r8a779m5
- const: renesas,r8a77965
- description: R-Car E3e (R8A779M6)
items:
- enum:
- renesas,ebisu # Ebisu
- const: renesas,r8a779m6
- const: renesas,r8a77990
- description: R-Car D3e (R8A779M7)
items:
- enum:
- renesas,draak # Draak
- const: renesas,r8a779m7
- const: renesas,r8a77995
- description: R-Car H3Ne (R8A779M8)
items:
- enum:
- renesas,h3ulcb # H3ULCB (R-Car Starter Kit Premier)
- renesas,salvator-xs # Salvator-XS (Salvator-X 2nd version)
- const: renesas,r8a779m8
- const: renesas,r8a7795
- description: RZ/N1D (R9A06G032)
items:
- enum:

48
sys/contrib/device-tree/Bindings/arm/rockchip.yaml
View File

@ -115,6 +115,11 @@ properties:
- const: firefly,roc-rk3328-cc
- const: rockchip,rk3328
- description: Firefly ROC-RK3328-PC
items:
- const: firefly,roc-rk3328-pc
- const: rockchip,rk3328
- description: Firefly ROC-RK3399-PC
items:
- enum:
@ -122,6 +127,12 @@ properties:
- firefly,roc-rk3399-pc-mezzanine
- const: rockchip,rk3399
- description: Firefly ROC-RK3399-PC-PLUS
items:
- enum:
- firefly,roc-rk3399-pc-plus
- const: rockchip,rk3399
- description: FriendlyElec NanoPi R2S
items:
- const: friendlyarm,nanopi-r2s
@ -287,6 +298,34 @@ properties:
- const: google,veyron
- const: rockchip,rk3288
- description: Google Scarlet - Dumo (ASUS Chromebook Tablet CT100)
items:
- const: google,scarlet-rev15-sku0
- const: google,scarlet-rev15
- const: google,scarlet-rev14-sku0
- const: google,scarlet-rev14
- const: google,scarlet-rev13-sku0
- const: google,scarlet-rev13
- const: google,scarlet-rev12-sku0
- const: google,scarlet-rev12
- const: google,scarlet-rev11-sku0
- const: google,scarlet-rev11
- const: google,scarlet-rev10-sku0
- const: google,scarlet-rev10
- const: google,scarlet-rev9-sku0
- const: google,scarlet-rev9
- const: google,scarlet-rev8-sku0
- const: google,scarlet-rev8
- const: google,scarlet-rev7-sku0
- const: google,scarlet-rev7
- const: google,scarlet-rev6-sku0
- const: google,scarlet-rev6
- const: google,scarlet-rev5-sku0
- const: google,scarlet-rev5
- const: google,scarlet
- const: google,gru
- const: rockchip,rk3399
- description: Google Scarlet - Kingdisplay (Acer Chromebook Tab 10)
items:
- const: google,scarlet-rev15-sku7
@ -455,16 +494,23 @@ properties:
- const: pine64,rockpro64
- const: rockchip,rk3399
- description: Pine64 Quartz64 Model A
items:
- const: pine64,quartz64-a
- const: rockchip,rk3566
- description: Radxa Rock
items:
- const: radxa,rock
- const: rockchip,rk3188
- description: Radxa ROCK Pi 4A/B/C
- description: Radxa ROCK Pi 4A/A+/B/B+/C
items:
- enum:
- radxa,rockpi4a
- radxa,rockpi4a-plus
- radxa,rockpi4b
- radxa,rockpi4b-plus
- radxa,rockpi4c
- const: radxa,rockpi4
- const: rockchip,rk3399

4
sys/contrib/device-tree/Bindings/arm/rockchip/pmu.yaml
View File

@ -22,7 +22,9 @@ select:
- rockchip,px30-pmu
- rockchip,rk3066-pmu
- rockchip,rk3288-pmu
- rockchip,rk3368-pmu
- rockchip,rk3399-pmu
- rockchip,rk3568-pmu
required:
- compatible
@ -34,7 +36,9 @@ properties:
- rockchip,px30-pmu
- rockchip,rk3066-pmu
- rockchip,rk3288-pmu
- rockchip,rk3368-pmu
- rockchip,rk3399-pmu
- rockchip,rk3568-pmu
- const: syscon
- const: simple-mfd

5
sys/contrib/device-tree/Bindings/arm/samsung/exynos-chipid.yaml
View File

@ -11,8 +11,9 @@ maintainers:
properties:
compatible:
items:
- const: samsung,exynos4210-chipid
enum:
- samsung,exynos4210-chipid
- samsung,exynos850-chipid
reg:
maxItems: 1

6
sys/contrib/device-tree/Bindings/arm/samsung/samsung-boards.yaml
View File

@ -199,6 +199,12 @@ properties:
- samsung,exynos7-espresso # Samsung Exynos7 Espresso
- const: samsung,exynos7
- description: Exynos Auto v9 based boards
items:
- enum:
- samsung,exynosautov9-sadk # Samsung Exynos Auto v9 SADK
- const: samsung,exynosautov9
required:
- compatible

5
sys/contrib/device-tree/Bindings/arm/sprd/sprd.yaml
View File

@ -30,6 +30,11 @@ properties:
- sprd,sp9863a-1h10
- const: sprd,sc9863a
- items:
- enum:
- sprd,ums512-1h10
- const: sprd,ums512
additionalProperties: true
...

2
sys/contrib/device-tree/Bindings/arm/sti.yaml
View File

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: ST STi Platforms Device Tree Bindings
maintainers:
- Patrice Chotard <patrice.chotard@st.com>
- Patrice Chotard <patrice.chotard@foss.st.com>
properties:
$nodename:

4
sys/contrib/device-tree/Bindings/arm/stm32/st,mlahb.yaml
View File

@ -7,8 +7,8 @@ $schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: STMicroelectronics STM32 ML-AHB interconnect bindings
maintainers:
- Fabien Dessenne <fabien.dessenne@st.com>
- Arnaud Pouliquen <arnaud.pouliquen@st.com>
- Fabien Dessenne <fabien.dessenne@foss.st.com>
- Arnaud Pouliquen <arnaud.pouliquen@foss.st.com>
description: |
These bindings describe the STM32 SoCs ML-AHB interconnect bus which connects

4
sys/contrib/device-tree/Bindings/arm/stm32/st,stm32-syscon.yaml
View File

@ -7,8 +7,8 @@ $schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: STMicroelectronics STM32 Platforms System Controller bindings
maintainers:
- Alexandre Torgue <alexandre.torgue@st.com>
- Christophe Roullier <christophe.roullier@st.com>
- Alexandre Torgue <alexandre.torgue@foss.st.com>
- Christophe Roullier <christophe.roullier@foss.st.com>
properties:
compatible:

6
sys/contrib/device-tree/Bindings/arm/stm32/stm32.yaml
View File

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: STMicroelectronics STM32 Platforms Device Tree Bindings
maintainers:
- Alexandre Torgue <alexandre.torgue@st.com>
- Alexandre Torgue <alexandre.torgue@foss.st.com>
properties:
$nodename:
@ -55,6 +55,10 @@ properties:
- enum:
- st,stm32h750i-art-pi
- const: st,stm32h750
- items:
- enum:
- st,stm32mp135f-dk
- const: st,stm32mp135
- items:
- enum:
- shiratech,stm32mp157a-iot-box # IoT Box

1
sys/contrib/device-tree/Bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml
View File

@ -30,6 +30,7 @@ properties:
enum:
- allwinner,sun5i-a13-mbus
- allwinner,sun8i-h3-mbus
- allwinner,sun8i-r40-mbus
- allwinner,sun50i-a64-mbus
reg:

38
sys/contrib/device-tree/Bindings/arm/sunxi/allwinner,sun6i-a31-cpuconfig.yaml Normal file
View File

@ -0,0 +1,38 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/sunxi/allwinner,sun6i-a31-cpuconfig.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Allwinner CPU Configuration Controller Device Tree Bindings
maintainers:
- Chen-Yu Tsai <wens@csie.org>
- Maxime Ripard <mripard@kernel.org>
properties:
compatible:
enum:
- allwinner,sun6i-a31-cpuconfig
- allwinner,sun8i-a23-cpuconfig
- allwinner,sun8i-a83t-cpucfg
- allwinner,sun8i-a83t-r-cpucfg
- allwinner,sun9i-a80-cpucfg
reg:
maxItems: 1
required:
- compatible
- reg
additionalProperties: false
examples:
- |
cpucfg@1f01c00 {
compatible = "allwinner,sun6i-a31-cpuconfig";
reg = <0x01f01c00 0x300>;
};
...

33
sys/contrib/device-tree/Bindings/arm/sunxi/allwinner,sun9i-a80-prcm.yaml Normal file
View File

@ -0,0 +1,33 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/sunxi/allwinner,sun9i-a80-prcm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Allwinner A80 PRCM Device Tree Bindings
maintainers:
- Chen-Yu Tsai <wens@csie.org>
- Maxime Ripard <mripard@kernel.org>
properties:
compatible:
const: allwinner,sun9i-a80-prcm
reg:
maxItems: 1
required:
- compatible
- reg
additionalProperties: false
examples:
- |
prcm@8001400 {
compatible = "allwinner,sun9i-a80-prcm";
reg = <0x08001400 0x200>;
};
...

15
sys/contrib/device-tree/Bindings/arm/ti/k3.yaml
View File

@ -24,16 +24,27 @@ properties:
- enum:
- ti,am654-evm
- siemens,iot2050-basic
- siemens,iot2050-basic-pg2
- siemens,iot2050-advanced
- siemens,iot2050-advanced-pg2
- const: ti,am654
- description: K3 J721E SoC
items:
oneOf:
- const: ti,j721e
- items:
- enum:
- ti,j721e-evm
- ti,j721e-sk
- const: ti,j721e
- description: K3 J7200 SoC
items:
oneOf:
- const: ti,j7200
- items:
- enum:
- ti,j7200-evm
- const: ti,j7200
- description: K3 AM642 SoC
items:

1
sys/contrib/device-tree/Bindings/arm/toshiba.yaml
View File

@ -18,6 +18,7 @@ properties:
items:
- enum:
- toshiba,tmpv7708-rm-mbrc # TMPV7708 RM main board
- toshiba,tmpv7708-visrobo-vrb # TMPV7708 VisROBO VRB board
- const: toshiba,tmpv7708
additionalProperties: true

17
sys/contrib/device-tree/Bindings/arm/xilinx.yaml
View File

@ -87,6 +87,7 @@ properties:
- xlnx,zynqmp-zcu102-revA
- xlnx,zynqmp-zcu102-revB
- xlnx,zynqmp-zcu102-rev1.0
- xlnx,zynqmp-zcu102-rev1.1
- const: xlnx,zynqmp-zcu102
- const: xlnx,zynqmp
@ -115,6 +116,22 @@ properties:
- const: xlnx,zynqmp-zcu111
- const: xlnx,zynqmp
- description: Xilinx Kria SOMs
items:
- const: xlnx,zynqmp-sm-k26-rev1
- const: xlnx,zynqmp-sm-k26-revB
- const: xlnx,zynqmp-sm-k26-revA
- const: xlnx,zynqmp-sm-k26
- const: xlnx,zynqmp
- description: Xilinx Kria SOMs (starter)
items:
- const: xlnx,zynqmp-smk-k26-rev1
- const: xlnx,zynqmp-smk-k26-revB
- const: xlnx,zynqmp-smk-k26-revA
- const: xlnx,zynqmp-smk-k26
- const: xlnx,zynqmp
additionalProperties: true
...

32
sys/contrib/device-tree/Bindings/auxdisplay/holtek,ht16k33.yaml
View File

@ -14,14 +14,21 @@ allOf:
properties:
compatible:
const: holtek,ht16k33
oneOf:
- items:
- enum:
- adafruit,3108 # 0.56" 4-Digit 7-Segment FeatherWing Display (Red)
- adafruit,3130 # 0.54" Quad Alphanumeric FeatherWing Display (Red)
- const: holtek,ht16k33
- const: holtek,ht16k33 # Generic 16*8 LED controller with dot-matrix display
reg:
maxItems: 1
refresh-rate-hz:
maxItems: 1
description: Display update interval in Hertz
description: Display update interval in Hertz for dot-matrix displays
interrupts:
maxItems: 1
@ -41,10 +48,22 @@ properties:
default: 16
description: Initial brightness level
led:
type: object
$ref: /schemas/leds/common.yaml#
unevaluatedProperties: false
required:
- compatible
- reg
- refresh-rate-hz
if:
properties:
compatible:
const: holtek,ht16k33
then:
required:
- refresh-rate-hz
additionalProperties: false
@ -52,6 +71,7 @@ examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
i2c1 {
#address-cells = <1>;
#size-cells = <0>;
@ -73,5 +93,11 @@ examples:
<MATRIX_KEY(4, 1, KEY_F9)>,
<MATRIX_KEY(5, 1, KEY_F3)>,
<MATRIX_KEY(6, 1, KEY_F1)>;
led {
color = <LED_COLOR_ID_RED>;
function = LED_FUNCTION_BACKLIGHT;
linux,default-trigger = "backlight";
};
};
};

79
sys/contrib/device-tree/Bindings/bus/palmbus.yaml Normal file
View File

@ -0,0 +1,79 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/bus/palmbus.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Ralink PalmBus Device Tree Bindings
maintainers:
- Sergio Paracuellos <sergio.paracuellos@gmail.com>
description: |
The ralink palmbus controller can be found in all ralink MIPS
SoCs. It provides an external bus for connecting multiple
external devices to the SoC.
properties:
$nodename:
pattern: "^palmbus(@[0-9a-f]+)?$"
"#address-cells":
const: 1
"#size-cells":
const: 1
compatible:
const: palmbus
reg:
maxItems: 1
ranges: true
patternProperties:
# All other properties should be child nodes with unit-address and 'reg'
"@[0-9a-f]+$":
type: object
properties:
reg:
maxItems: 1
required:
- reg
required:
- compatible
- reg
- "#address-cells"
- "#size-cells"
- ranges
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/mips-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
palmbus@1e000000 {
compatible = "palmbus";
reg = <0x1e000000 0x100000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x1e000000 0x0fffff>;
gpio@600 {
#gpio-cells = <2>;
#interrupt-cells = <2>;
compatible = "mediatek,mt7621-gpio";
gpio-controller;
gpio-ranges = <&pinctrl 0 0 95>;
interrupt-controller;
reg = <0x600 0x100>;
interrupt-parent = <&gic>;
interrupts = <GIC_SHARED 12 IRQ_TYPE_LEVEL_HIGH>;
};
};
...

216
sys/contrib/device-tree/Bindings/bus/ti-sysc.yaml Normal file
View File

@ -0,0 +1,216 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/bus/ti-sysc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Texas Instruments interconnect target module binding
maintainers:
- Tony Lindgren <tony@atomide.com>
description:
Texas Instruments SoCs can have a generic interconnect target module
for devices connected to various interconnects such as L3 interconnect
using Arteris NoC, and L4 interconnect using Sonics s3220. This module
is mostly used for interaction between module and Power, Reset and Clock
Manager PRCM. It participates in the OCP Disconnect Protocol, but other
than that it is mostly independent of the interconnect.
Each interconnect target module can have one or more devices connected to
it. There is a set of control registers for managing the interconnect target
module clocks, idle modes and interconnect level resets.
The interconnect target module control registers are sprinkled into the
unused register address space of the first child device IP block managed by
the interconnect target module. Typically the register names are REVISION,
SYSCONFIG and SYSSTATUS.
properties:
$nodename:
pattern: "^target-module(@[0-9a-f]+)?$"
compatible:
oneOf:
- items:
- enum:
- ti,sysc-omap2
- ti,sysc-omap2
- ti,sysc-omap4
- ti,sysc-omap4-simple
- ti,sysc-omap2-timer
- ti,sysc-omap4-timer
- ti,sysc-omap3430-sr
- ti,sysc-omap3630-sr
- ti,sysc-omap4-sr
- ti,sysc-omap3-sham
- ti,sysc-omap-aes
- ti,sysc-mcasp
- ti,sysc-dra7-mcasp
- ti,sysc-usb-host-fs
- ti,sysc-dra7-mcan
- ti,sysc-pruss
- const: ti,sysc
- items:
- const: ti,sysc
reg:
description:
Interconnect target module control registers consisting of
REVISION, SYSCONFIG and SYSSTATUS registers as defined in the
Technical Reference Manual for the SoC.
minItems: 1
maxItems: 3
reg-names:
description:
Interconnect target module control register names consisting
of "rev", "sysc" and "syss".
oneOf:
- minItems: 1
items:
- const: rev
- const: sysc
- const: syss
- items:
- const: rev
- const: syss
- enum: [ sysc, syss ]
power-domains:
description: Target module power domain if available.
maxItems: 1
clocks:
description:
Target module clocks consisting of one functional clock, one
interface clock, and up to 8 module specific optional clocks.
Some modules may have only the functional clock, and some have
no configurable clocks.
minItems: 1
maxItems: 4
clock-names:
description:
Target module clock names like "fck", "ick", "optck1", "optck2"
if the clocks are configurable.
oneOf:
- enum: [ ick, fck, sys_clk ]
- items:
- const: fck
- enum: [ ick. dbclk, osc, sys_clk, dss_clk, ahclkx ]
- items:
- const: fck
- const: phy-clk
- const: phy-clk-div
- items:
- const: fck
- const: hdmi_clk
- const: sys_clk
- const: tv_clk
- items:
- const: fck
- const: ahclkx
- const: ahclkr
resets:
description:
Target module reset bit in the RSTCTRL register if wired for the module.
Note that the other reset bits should be mapped for the child device
driver to use.
maxItems: 1
reset-names:
description:
Target module reset names in the RSTCTRL register, typically named
"rstctrl" if only one reset bit is wired for the module.
items:
- const: rstctrl
'#address-cells':
enum: [ 1, 2 ]
'#size-cells':
enum: [ 1, 2 ]
ranges: true
dma-ranges: true
ti,sysc-mask:
description: Mask of supported register bits for the SYSCONFIG register
$ref: /schemas/types.yaml#/definitions/uint32
ti,sysc-midle:
description: List of hardware supported idle modes
$ref: /schemas/types.yaml#/definitions/uint32-array
ti,sysc-sidle:
description: List of hardware supported idle modes
$ref: /schemas/types.yaml#/definitions/uint32-array
ti,syss-mask:
description: Mask of supported register bits for the SYSSTATUS register
$ref: /schemas/types.yaml#/definitions/uint32
ti,sysc-delay-us:
description: Delay needed after OCP softreset before accessing SYCONFIG
default: 0
minimum: 0
maximum: 2
ti,no-reset-on-init:
description: Interconnect target module shall not be reset at init
type: boolean
ti,no-idle-on-init:
description: Interconnect target module shall not be idled at init
type: boolean
ti,no-idle:
description: Interconnect target module shall not be idled
type: boolean
ti,hwmods:
description: Interconnect module name to use with legacy hwmod data
$ref: /schemas/types.yaml#/definitions/string
deprecated: true
required:
- compatible
- '#address-cells'
- '#size-cells'
- ranges
additionalProperties:
type: object
examples:
- |
#include <dt-bindings/bus/ti-sysc.h>
#include <dt-bindings/clock/omap4.h>
target-module@2b000 {
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "usb_otg_hs";
reg = <0x2b400 0x4>,
<0x2b404 0x4>,
<0x2b408 0x4>;
reg-names = "rev", "sysc", "syss";
clocks = <&l3_init_clkctrl OMAP4_USB_OTG_HS_CLKCTRL 0>;
clock-names = "fck";
ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
ti,sysc-midle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
ti,syss-mask = <1>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x2b000 0x1000>;
};

2
sys/contrib/device-tree/Bindings/clock/allwinner,sun8i-a83t-de2-clk.yaml
View File

@ -24,7 +24,7 @@ properties:
- const: allwinner,sun8i-v3s-de2-clk
- const: allwinner,sun50i-a64-de2-clk
- const: allwinner,sun50i-h5-de2-clk
- const: allwinner,sun50i-h6-de2-clk
- const: allwinner,sun50i-h6-de3-clk
- items:
- const: allwinner,sun8i-r40-de2-clk
- const: allwinner,sun8i-h3-de2-clk

5
sys/contrib/device-tree/Bindings/clock/arm,syscon-icst.yaml
View File

@ -69,6 +69,10 @@ properties:
- arm,impd1-vco1
- arm,impd1-vco2
reg:
maxItems: 1
description: The VCO register
clocks:
description: Parent clock for the ICST VCO
maxItems: 1
@ -83,6 +87,7 @@ properties:
vco-offset:
$ref: '/schemas/types.yaml#/definitions/uint32'
description: Offset to the VCO register for the oscillator
deprecated: true
required:
- "#clock-cells"

47
sys/contrib/device-tree/Bindings/clock/fixed-mmio-clock.yaml Normal file
View File

@ -0,0 +1,47 @@
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/fixed-mmio-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Binding for simple memory mapped IO fixed-rate clock sources
description:
This binding describes a fixed-rate clock for which the frequency can
be read from a single 32-bit memory mapped I/O register.
It was designed for test systems, like FPGA, not for complete,
finished SoCs.
maintainers:
- Jan Kotas <jank@cadence.com>
properties:
compatible:
const: fixed-mmio-clock
reg:
maxItems: 1
"#clock-cells":
const: 0
clock-output-names:
maxItems: 1
required:
- compatible
- reg
- "#clock-cells"
additionalProperties: false
examples:
- |
sysclock: sysclock@fd020004 {
compatible = "fixed-mmio-clock";
#clock-cells = <0>;
reg = <0xfd020004 0x4>;
clock-output-names = "sysclk";
};
...

43
sys/contrib/device-tree/Bindings/clock/imx8ulp-cgc-clock.yaml Normal file
View File

@ -0,0 +1,43 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/imx8ulp-cgc-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NXP i.MX8ULP Clock Generation & Control(CGC) Module Binding
maintainers:
- Jacky Bai <ping.bai@nxp.com>
description: |
On i.MX8ULP, The clock sources generation, distribution and management is
under the control of several CGCs & PCCs modules. The CGC modules generate
and distribute clocks on the device.
properties:
compatible:
enum:
- fsl,imx8ulp-cgc1
- fsl,imx8ulp-cgc2
reg:
maxItems: 1
'#clock-cells':
const: 1
required:
- compatible
- reg
- '#clock-cells'
additionalProperties: false
examples:
# Clock Generation & Control Module node:
- |
clock-controller@292c0000 {
compatible = "fsl,imx8ulp-cgc1";
reg = <0x292c0000 0x10000>;
#clock-cells = <1>;
};

50
sys/contrib/device-tree/Bindings/clock/imx8ulp-pcc-clock.yaml Normal file
View File

@ -0,0 +1,50 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/imx8ulp-pcc-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NXP i.MX8ULP Peripheral Clock Controller(PCC) Module Binding
maintainers:
- Jacky Bai <ping.bai@nxp.com>
description: |
On i.MX8ULP, The clock sources generation, distribution and management is
under the control of several CGCs & PCCs modules. The PCC modules control
software reset, clock selection, optional division and clock gating mode
for peripherals.
properties:
compatible:
enum:
- fsl,imx8ulp-pcc3
- fsl,imx8ulp-pcc4
- fsl,imx8ulp-pcc5
reg:
maxItems: 1
'#clock-cells':
const: 1
'#reset-cells':
const: 1
required:
- compatible
- reg
- '#clock-cells'
- '#reset-cells'
additionalProperties: false
examples:
# Peripheral Clock Control Module node:
- |
clock-controller@292d0000 {
compatible = "fsl,imx8ulp-pcc3";
reg = <0x292d0000 0x10000>;
#clock-cells = <1>;
#reset-cells = <1>;
};

2
sys/contrib/device-tree/Bindings/clock/ingenic,cgu.yaml
View File

@ -104,7 +104,7 @@ additionalProperties: false
examples:
- |
#include <dt-bindings/clock/jz4770-cgu.h>
#include <dt-bindings/clock/ingenic,jz4770-cgu.h>
cgu: clock-controller@10000000 {
compatible = "ingenic,jz4770-cgu", "simple-mfd";
reg = <0x10000000 0x100>;

4
sys/contrib/device-tree/Bindings/clock/maxim,max77686.txt
View File

@ -49,7 +49,7 @@ Example:
max77686: max77686@9 {
compatible = "maxim,max77686";
interrupt-parent = <&wakeup_eint>;
interrupts = <26 0>;
interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
reg = <0x09>;
#clock-cells = <1>;
@ -74,7 +74,7 @@ Example:
max77802: max77802@9 {
compatible = "maxim,max77802";
interrupt-parent = <&wakeup_eint>;
interrupts = <26 0>;
interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
reg = <0x09>;
#clock-cells = <1>;

13
sys/contrib/device-tree/Bindings/clock/qcom,dispcc-sm8x50.yaml
View File

@ -56,6 +56,16 @@ properties:
reg:
maxItems: 1
power-domains:
description:
A phandle and PM domain specifier for the MMCX power domain.
maxItems: 1
required-opps:
description:
A phandle to an OPP node describing required MMCX performance point.
maxItems: 1
required:
- compatible
- reg
@ -70,6 +80,7 @@ additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/power/qcom-rpmpd.h>
clock-controller@af00000 {
compatible = "qcom,sm8250-dispcc";
reg = <0x0af00000 0x10000>;
@ -90,5 +101,7 @@ examples:
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
power-domains = <&rpmhpd SM8250_MMCX>;
required-opps = <&rpmhpd_opp_low_svs>;
};
...

70
sys/contrib/device-tree/Bindings/clock/qcom,gcc-msm8994.yaml Normal file
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@ -0,0 +1,70 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8994.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller Binding for MSM8994
maintainers:
- Konrad Dybcio <konrad.dybcio@somainline.org>
description: |
Qualcomm global clock control module which supports the clocks, resets and
power domains on MSM8994 and MSM8992.
See also:
- dt-bindings/clock/qcom,gcc-msm8994.h
properties:
compatible:
enum:
- qcom,gcc-msm8992
- qcom,gcc-msm8994
clocks:
items:
- description: Board XO source
- description: Sleep clock source
clock-names:
items:
- const: xo
- const: sleep
'#clock-cells':
const: 1
'#reset-cells':
const: 1
'#power-domain-cells':
const: 1
reg:
maxItems: 1
required:
- compatible
- clocks
- clock-names
- reg
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
examples:
- |
clock-controller@300000 {
compatible = "qcom,gcc-msm8994";
reg = <0x00300000 0x90000>;
clocks = <&xo_board>, <&sleep_clk>;
clock-names = "xo", "sleep";
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
...

26
sys/contrib/device-tree/Bindings/clock/qcom,gcc-msm8998.yaml
View File

@ -25,21 +25,17 @@ properties:
items:
- description: Board XO source
- description: Sleep clock source
- description: USB 3.0 phy pipe clock
- description: UFS phy rx symbol clock for pipe 0
- description: UFS phy rx symbol clock for pipe 1
- description: UFS phy tx symbol clock
- description: PCIE phy pipe clock
- description: Audio reference clock (Optional clock)
- description: PLL test clock source (Optional clock)
minItems: 2
clock-names:
items:
- const: xo
- const: sleep_clk
- const: usb3_pipe
- const: ufs_rx_symbol0
- const: ufs_rx_symbol1
- const: ufs_tx_symbol0
- const: pcie0_pipe
- const: aud_ref_clk # Optional clock
- const: core_bi_pll_test_se # Optional clock
minItems: 2
'#clock-cells':
const: 1
@ -80,16 +76,10 @@ examples:
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
<&sleep>,
<0>,
<0>,
<0>,
<0>,
<0>;
clock-names = "xo",
"sleep_clk",
"usb3_pipe",
"ufs_rx_symbol0",
"ufs_rx_symbol1",
"ufs_tx_symbol0",
"pcie0_pipe";
"aud_ref_clk",
"core_bi_pll_test_se";
};
...

72
sys/contrib/device-tree/Bindings/clock/qcom,gcc-qcm2290.yaml Normal file
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@ -0,0 +1,72 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,gcc-qcm2290.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller Binding for QCM2290
maintainers:
- Shawn Guo <shawn.guo@linaro.org>
description: |
Qualcomm global clock control module which supports the clocks, resets
and power domains on QCM2290.
See also:
- dt-bindings/clock/qcom,gcc-qcm2290.h
properties:
compatible:
const: qcom,gcc-qcm2290
clocks:
items:
- description: Board XO source
- description: Sleep clock source
clock-names:
items:
- const: bi_tcxo
- const: sleep_clk
'#clock-cells':
const: 1
'#reset-cells':
const: 1
'#power-domain-cells':
const: 1
reg:
maxItems: 1
protected-clocks:
description:
Protected clock specifier list as per common clock binding.
required:
- compatible
- clocks
- clock-names
- reg
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmcc.h>
clock-controller@1400000 {
compatible = "qcom,gcc-qcm2290";
reg = <0x01400000 0x1f0000>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
clock-names = "bi_tcxo", "sleep_clk";
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>;
};
...

2
sys/contrib/device-tree/Bindings/clock/qcom,gcc.yaml
View File

@ -29,7 +29,6 @@ description: |
- dt-bindings/reset/qcom,gcc-msm8660.h
- dt-bindings/clock/qcom,gcc-msm8974.h (qcom,gcc-msm8226 and qcom,gcc-msm8974)
- dt-bindings/reset/qcom,gcc-msm8974.h (qcom,gcc-msm8226 and qcom,gcc-msm8974)
- dt-bindings/clock/qcom,gcc-msm8994.h
- dt-bindings/clock/qcom,gcc-mdm9607.h
- dt-bindings/clock/qcom,gcc-mdm9615.h
- dt-bindings/reset/qcom,gcc-mdm9615.h
@ -52,7 +51,6 @@ properties:
- qcom,gcc-msm8974
- qcom,gcc-msm8974pro
- qcom,gcc-msm8974pro-ac
- qcom,gcc-msm8994
- qcom,gcc-mdm9615
- qcom,gcc-sdm630
- qcom,gcc-sdm660

1
sys/contrib/device-tree/Bindings/clock/qcom,rpmcc.txt
View File

@ -25,6 +25,7 @@ Required properties :
"qcom,rpmcc-msm8994",·"qcom,rpmcc"
"qcom,rpmcc-msm8996", "qcom,rpmcc"
"qcom,rpmcc-msm8998", "qcom,rpmcc"
"qcom,rpmcc-qcm2290", "qcom,rpmcc"
"qcom,rpmcc-qcs404", "qcom,rpmcc"
"qcom,rpmcc-sdm660", "qcom,rpmcc"
"qcom,rpmcc-sm6115", "qcom,rpmcc"

71
sys/contrib/device-tree/Bindings/clock/qcom,sc7280-camcc.yaml Normal file
View File

@ -0,0 +1,71 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,sc7280-camcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Camera Clock & Reset Controller Binding for SC7280
maintainers:
- Taniya Das <tdas@codeaurora.org>
description: |
Qualcomm camera clock control module which supports the clocks, resets and
power domains on SC7280.
See also dt-bindings/clock/qcom,camcc-sc7280.h
properties:
compatible:
const: qcom,sc7280-camcc
clocks:
items:
- description: Board XO source
- description: Board XO active source
- description: Sleep clock source
clock-names:
items:
- const: bi_tcxo
- const: bi_tcxo_ao
- const: sleep_clk
'#clock-cells':
const: 1
'#reset-cells':
const: 1
'#power-domain-cells':
const: 1
reg:
maxItems: 1
required:
- compatible
- reg
- clocks
- clock-names
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
clock-controller@ad00000 {
compatible = "qcom,sc7280-camcc";
reg = <0x0ad00000 0x10000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>,
<&sleep_clk>;
clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
...

68
sys/contrib/device-tree/Bindings/clock/qcom,sc7280-lpasscc.yaml Normal file
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@ -0,0 +1,68 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,sc7280-lpasscc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm LPASS Core Clock Controller Binding for SC7280
maintainers:
- Taniya Das <tdas@codeaurora.org>
description: |
Qualcomm LPASS core clock control module which supports the clocks and
power domains on SC7280.
See also:
- dt-bindings/clock/qcom,lpass-sc7280.h
properties:
compatible:
enum:
- qcom,sc7280-lpasscc
clocks:
items:
- description: gcc_cfg_noc_lpass_clk from GCC
clock-names:
items:
- const: iface
'#clock-cells':
const: 1
reg:
items:
- description: LPASS qdsp6ss register
- description: LPASS top-cc register
- description: LPASS cc register
reg-names:
items:
- const: qdsp6ss
- const: top_cc
- const: cc
required:
- compatible
- reg
- clocks
- clock-names
- '#clock-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,gcc-sc7280.h>
#include <dt-bindings/clock/qcom,lpass-sc7280.h>
clock-controller@3000000 {
compatible = "qcom,sc7280-lpasscc";
reg = <0x03000000 0x40>, <0x03c04000 0x4>, <0x03389000 0x24>;
reg-names = "qdsp6ss", "top_cc", "cc";
clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>;
clock-names = "iface";
#clock-cells = <1>;
};
...

13
sys/contrib/device-tree/Bindings/clock/qcom,videocc.yaml
View File

@ -49,6 +49,16 @@ properties:
reg:
maxItems: 1
power-domains:
description:
A phandle and PM domain specifier for the MMCX power domain.
maxItems: 1
required-opps:
description:
A phandle to an OPP node describing required MMCX performance point.
maxItems: 1
required:
- compatible
- reg
@ -63,6 +73,7 @@ additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/power/qcom-rpmpd.h>
clock-controller@ab00000 {
compatible = "qcom,sdm845-videocc";
reg = <0x0ab00000 0x10000>;
@ -71,5 +82,7 @@ examples:
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
power-domains = <&rpmhpd SM8250_MMCX>;
required-opps = <&rpmhpd_opp_low_svs>;
};
...

185
sys/contrib/device-tree/Bindings/clock/samsung,exynos850-clock.yaml Normal file
View File

@ -0,0 +1,185 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/samsung,exynos850-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Samsung Exynos850 SoC clock controller
maintainers:
- Sam Protsenko <semen.protsenko@linaro.org>
- Chanwoo Choi <cw00.choi@samsung.com>
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
- Sylwester Nawrocki <s.nawrocki@samsung.com>
- Tomasz Figa <tomasz.figa@gmail.com>
description: |
Exynos850 clock controller is comprised of several CMU units, generating
clocks for different domains. Those CMU units are modeled as separate device
tree nodes, and might depend on each other. Root clocks in that clock tree are
two external clocks:: OSCCLK (26 MHz) and RTCCLK (32768 Hz). Those external
clocks must be defined as fixed-rate clocks in dts.
CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
dividers; all other leaf clocks (other CMUs) are usually derived from CMU_TOP.
Each clock is assigned an identifier and client nodes can use this identifier
to specify the clock which they consume. All clocks available for usage
in clock consumer nodes are defined as preprocessor macros in
'dt-bindings/clock/exynos850.h' header.
properties:
compatible:
enum:
- samsung,exynos850-cmu-top
- samsung,exynos850-cmu-core
- samsung,exynos850-cmu-dpu
- samsung,exynos850-cmu-hsi
- samsung,exynos850-cmu-peri
clocks:
minItems: 1
maxItems: 5
clock-names:
minItems: 1
maxItems: 5
"#clock-cells":
const: 1
reg:
maxItems: 1
allOf:
- if:
properties:
compatible:
contains:
const: samsung,exynos850-cmu-top
then:
properties:
clocks:
items:
- description: External reference clock (26 MHz)
clock-names:
items:
- const: oscclk
- if:
properties:
compatible:
contains:
const: samsung,exynos850-cmu-core
then:
properties:
clocks:
items:
- description: External reference clock (26 MHz)
- description: CMU_CORE bus clock (from CMU_TOP)
- description: CCI clock (from CMU_TOP)
- description: eMMC clock (from CMU_TOP)
- description: SSS clock (from CMU_TOP)
clock-names:
items:
- const: oscclk
- const: dout_core_bus
- const: dout_core_cci
- const: dout_core_mmc_embd
- const: dout_core_sss
- if:
properties:
compatible:
contains:
const: samsung,exynos850-cmu-dpu
then:
properties:
clocks:
items:
- description: External reference clock (26 MHz)
- description: DPU clock (from CMU_TOP)
clock-names:
items:
- const: oscclk
- const: dout_dpu
- if:
properties:
compatible:
contains:
const: samsung,exynos850-cmu-hsi
then:
properties:
clocks:
items:
- description: External reference clock (26 MHz)
- description: External RTC clock (32768 Hz)
- description: CMU_HSI bus clock (from CMU_TOP)
- description: SD card clock (from CMU_TOP)
- description: "USB 2.0 DRD clock (from CMU_TOP)"
clock-names:
items:
- const: oscclk
- const: rtcclk
- const: dout_hsi_bus
- const: dout_hsi_mmc_card
- const: dout_hsi_usb20drd
- if:
properties:
compatible:
contains:
const: samsung,exynos850-cmu-peri
then:
properties:
clocks:
items:
- description: External reference clock (26 MHz)
- description: CMU_PERI bus clock (from CMU_TOP)
- description: UART clock (from CMU_TOP)
- description: Parent clock for HSI2C and SPI (from CMU_TOP)
clock-names:
items:
- const: oscclk
- const: dout_peri_bus
- const: dout_peri_uart
- const: dout_peri_ip
required:
- compatible
- "#clock-cells"
- clocks
- clock-names
- reg
additionalProperties: false
examples:
# Clock controller node for CMU_PERI
- |
#include <dt-bindings/clock/exynos850.h>
cmu_peri: clock-controller@10030000 {
compatible = "samsung,exynos850-cmu-peri";
reg = <0x10030000 0x8000>;
#clock-cells = <1>;
clocks = <&oscclk>, <&cmu_top CLK_DOUT_PERI_BUS>,
<&cmu_top CLK_DOUT_PERI_UART>,
<&cmu_top CLK_DOUT_PERI_IP>;
clock-names = "oscclk", "dout_peri_bus",
"dout_peri_uart", "dout_peri_ip";
};
...

45
sys/contrib/device-tree/Bindings/clock/samsung,s2mps11.yaml Normal file
View File

@ -0,0 +1,45 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/samsung,s2mps11.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Samsung S2M and S5M family clock generator block
maintainers:
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
description: |
This is a part of device tree bindings for S2M and S5M family of Power
Management IC (PMIC).
The S2MPS11/13/15 and S5M8767 provide three(AP/CP/BT) buffered 32.768 kHz
outputs. The S2MPS14 provides two (AP/BT) buffered 32.768 KHz outputs.
All available clocks are defined as preprocessor macros in
dt-bindings/clock/samsung,s2mps11.h header.
See also Documentation/devicetree/bindings/mfd/samsung,s2mps11.yaml for
additional information and example.
properties:
compatible:
enum:
- samsung,s2mps11-clk
- samsung,s2mps13-clk # S2MPS13 and S2MPS15
- samsung,s2mps14-clk
- samsung,s5m8767-clk
"#clock-cells":
const: 1
clock-output-names:
minItems: 3
maxItems: 3
description: Names for AP, CP and BT clocks.
required:
- compatible
- "#clock-cells"
additionalProperties: false

4
sys/contrib/device-tree/Bindings/clock/sifive/fu740-prci.yaml
View File

@ -42,6 +42,9 @@ properties:
"#clock-cells":
const: 1
"#reset-cells":
const: 1
required:
- compatible
- reg
@ -57,4 +60,5 @@ examples:
reg = <0x10000000 0x1000>;
clocks = <&hfclk>, <&rtcclk>;
#clock-cells = <1>;
#reset-cells = <1>;
};

2
sys/contrib/device-tree/Bindings/clock/silabs,si5351.txt
View File

@ -2,7 +2,7 @@ Binding for Silicon Labs Si5351a/b/c programmable i2c clock generator.
Reference
[1] Si5351A/B/C Data Sheet
https://www.silabs.com/Support%20Documents/TechnicalDocs/Si5351.pdf
https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/data-sheets/Si5351-B.pdf
The Si5351a/b/c are programmable i2c clock generators with up to 8 output
clocks. Si5351a also has a reduced pin-count package (MSOP10) where only

6
sys/contrib/device-tree/Bindings/clock/socionext,uniphier-clock.yaml
View File

@ -23,6 +23,7 @@ properties:
- socionext,uniphier-ld11-clock
- socionext,uniphier-ld20-clock
- socionext,uniphier-pxs3-clock
- socionext,uniphier-nx1-clock
- description: Media I/O (MIO) clock, SD clock
enum:
- socionext,uniphier-ld4-mio-clock
@ -33,6 +34,7 @@ properties:
- socionext,uniphier-ld11-mio-clock
- socionext,uniphier-ld20-sd-clock
- socionext,uniphier-pxs3-sd-clock
- socionext,uniphier-nx1-sd-clock
- description: Peripheral clock
enum:
- socionext,uniphier-ld4-peri-clock
@ -43,6 +45,10 @@ properties:
- socionext,uniphier-ld11-peri-clock
- socionext,uniphier-ld20-peri-clock
- socionext,uniphier-pxs3-peri-clock
- socionext,uniphier-nx1-peri-clock
- description: SoC-glue clock
enum:
- socionext,uniphier-pro4-sg-clock
"#clock-cells":
const: 1

2
sys/contrib/device-tree/Bindings/clock/st,stm32mp1-rcc.yaml
View File

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Reset Clock Controller Binding
maintainers:
- Gabriel Fernandez <gabriel.fernandez@st.com>
- Gabriel Fernandez <gabriel.fernandez@foss.st.com>
description: |
The RCC IP is both a reset and a clock controller.

121
sys/contrib/device-tree/Bindings/clock/stericsson,u8500-clks.yaml Normal file
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@ -0,0 +1,121 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/stericsson,u8500-clks.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ST-Ericsson DB8500 (U8500) clocks
maintainers:
- Ulf Hansson <ulf.hansson@linaro.org>
- Linus Walleij <linus.walleij@linaro.org>
description: While named "U8500 clocks" these clocks are inside the
DB8500 digital baseband system-on-chip and its siblings such as
DB8520. These bindings consider the clocks present in the SoC
itself, not off-chip clocks. There are four different on-chip
clocks - RTC (32 kHz), CPU clock (SMP TWD), PRCMU (power reset and
control management unit) clocks and PRCC (peripheral reset and
clock controller) clocks. For some reason PRCC 4 does not exist so
the itemization can be a bit unintuitive.
properties:
compatible:
enum:
- stericsson,u8500-clks
- stericsson,u8540-clks
- stericsson,u9540-clks
reg:
items:
- description: PRCC 1 register area
- description: PRCC 2 register area
- description: PRCC 3 register area
- description: PRCC 5 register area
- description: PRCC 6 register area
prcmu-clock:
description: A subnode with one clock cell for PRCMU (power, reset, control
management unit) clocks. The cell indicates which PRCMU clock in the
prcmu-clock node the consumer wants to use.
type: object
properties:
'#clock-cells':
const: 1
additionalProperties: false
prcc-periph-clock:
description: A subnode with two clock cells for PRCC (peripheral
reset and clock controller) peripheral clocks. The first cell indicates
which PRCC block the consumer wants to use, possible values are 1, 2, 3,
5, 6. The second cell indicates which clock inside the PRCC block it
wants, possible values are 0 thru 31.
type: object
properties:
'#clock-cells':
const: 2
additionalProperties: false
prcc-kernel-clock:
description: A subnode with two clock cells for PRCC (peripheral reset
and clock controller) kernel clocks. The first cell indicates which PRCC
block the consumer wants to use, possible values are 1, 2, 3, 5, 6. The
second cell indicates which clock inside the PRCC block it wants, possible
values are 0 thru 31.
type: object
properties:
'#clock-cells':
const: 2
additionalProperties: false
prcc-reset-controller:
description: A subnode with two reset cells for the reset portions of the
PRCC (peripheral reset and clock controller). The first cell indicates
which PRCC block the consumer wants to use, possible values are 1, 2, 3
5 and 6. The second cell indicates which reset line inside the PRCC block
it wants to control, possible values are 0 thru 31.
type: object
properties:
'#reset-cells':
const: 2
additionalProperties: false
rtc32k-clock:
description: A subnode with zero clock cells for the 32kHz RTC clock.
type: object
properties:
'#clock-cells':
const: 0
additionalProperties: false
smp-twd-clock:
description: A subnode for the ARM SMP Timer Watchdog cluster with zero
clock cells.
type: object
properties:
'#clock-cells':
const: 0
additionalProperties: false
required:
- compatible
- reg
- prcmu-clock
- prcc-periph-clock
- prcc-kernel-clock
- rtc32k-clock
- smp-twd-clock
additionalProperties: false

47
sys/contrib/device-tree/Bindings/crypto/intel,keembay-ocs-ecc.yaml Normal file
View File

@ -0,0 +1,47 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/crypto/intel,keembay-ocs-ecc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Intel Keem Bay OCS ECC Device Tree Bindings
maintainers:
- Daniele Alessandrelli <daniele.alessandrelli@intel.com>
- Prabhjot Khurana <prabhjot.khurana@intel.com>
description:
The Intel Keem Bay Offload and Crypto Subsystem (OCS) Elliptic Curve
Cryptography (ECC) device provides hardware acceleration for elliptic curve
cryptography using the NIST P-256 and NIST P-384 elliptic curves.
properties:
compatible:
const: intel,keembay-ocs-ecc
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
maxItems: 1
required:
- compatible
- reg
- interrupts
- clocks
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
crypto@30001000 {
compatible = "intel,keembay-ocs-ecc";
reg = <0x30001000 0x1000>;
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&scmi_clk 95>;
};

2
sys/contrib/device-tree/Bindings/crypto/st,stm32-crc.yaml
View File

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: STMicroelectronics STM32 CRC bindings
maintainers:
- Lionel Debieve <lionel.debieve@st.com>
- Lionel Debieve <lionel.debieve@foss.st.com>
properties:
compatible:

2
sys/contrib/device-tree/Bindings/crypto/st,stm32-cryp.yaml
View File

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: STMicroelectronics STM32 CRYP bindings
maintainers:
- Lionel Debieve <lionel.debieve@st.com>
- Lionel Debieve <lionel.debieve@foss.st.com>
properties:
compatible:

2
sys/contrib/device-tree/Bindings/crypto/st,stm32-hash.yaml
View File

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: STMicroelectronics STM32 HASH bindings
maintainers:
- Lionel Debieve <lionel.debieve@st.com>
- Lionel Debieve <lionel.debieve@foss.st.com>
properties:
compatible:

2
sys/contrib/device-tree/Bindings/devfreq/rk3399_dmc.txt
View File

@ -174,7 +174,7 @@ Example:
compatible = "rockchip,rk3399-dmc";
devfreq-events = <&dfi>;
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_DDRCLK>;
clocks = <&cru SCLK_DDRC>;
clock-names = "dmc_clk";
operating-points-v2 = <&dmc_opp_table>;
center-supply = <&ppvar_centerlogic>;

3
sys/contrib/device-tree/Bindings/display/brcm,bcm2835-dsi0.yaml
View File

@ -47,6 +47,9 @@ properties:
interrupts:
maxItems: 1
power-domains:
maxItems: 1
required:
- "#clock-cells"
- compatible

3
sys/contrib/device-tree/Bindings/display/brcm,bcm2835-hdmi.yaml
View File

@ -51,6 +51,9 @@ properties:
dma-names:
const: audio-rx
power-domains:
maxItems: 1
required:
- compatible
- reg

3
sys/contrib/device-tree/Bindings/display/brcm,bcm2835-v3d.yaml
View File

@ -24,6 +24,9 @@ properties:
interrupts:
maxItems: 1
power-domains:
maxItems: 1
required:
- compatible
- reg

3
sys/contrib/device-tree/Bindings/display/brcm,bcm2835-vec.yaml
View File

@ -24,6 +24,9 @@ properties:
interrupts:
maxItems: 1
power-domains:
maxItems: 1
required:
- compatible
- reg

33
sys/contrib/device-tree/Bindings/display/bridge/lvds-codec.yaml
View File

@ -49,11 +49,26 @@ properties:
properties:
port@0:
$ref: /schemas/graph.yaml#/properties/port
$ref: /schemas/graph.yaml#/$defs/port-base
description: |
For LVDS encoders, port 0 is the parallel input
For LVDS decoders, port 0 is the LVDS input
properties:
endpoint:
$ref: /schemas/media/video-interfaces.yaml#
unevaluatedProperties: false
properties:
data-mapping:
enum:
- jeida-18
- jeida-24
- vesa-24
description: |
The color signals mapping order. See details in
Documentation/devicetree/bindings/display/panel/lvds.yaml
port@1:
$ref: /schemas/graph.yaml#/properties/port
description: |
@ -71,6 +86,22 @@ properties:
power-supply: true
if:
not:
properties:
compatible:
contains:
const: lvds-decoder
then:
properties:
ports:
properties:
port@0:
properties:
endpoint:
properties:
data-mapping: false
required:
- compatible
- ports

19
sys/contrib/device-tree/Bindings/display/bridge/ps8640.yaml
View File

@ -40,6 +40,9 @@ properties:
vdd33-supply:
description: Regulator for 3.3V digital core power.
aux-bus:
$ref: /schemas/display/dp-aux-bus.yaml#
ports:
$ref: /schemas/graph.yaml#/properties/ports
@ -98,7 +101,21 @@ examples:
reg = <1>;
ps8640_out: endpoint {
remote-endpoint = <&panel_in>;
};
};
};
};
aux-bus {
panel {
compatible = "boe,nv133fhm-n62";
power-supply = <&pp3300_dx_edp>;
backlight = <&backlight>;
port {
panel_in: endpoint {
remote-endpoint = <&ps8640_out>;
};
};
};
};
};

2
sys/contrib/device-tree/Bindings/display/bridge/snps,dw-mipi-dsi.yaml
View File

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Synopsys DesignWare MIPI DSI host controller
maintainers:
- Philippe CORNU <philippe.cornu@st.com>
- Philippe CORNU <philippe.cornu@foss.st.com>
description: |
This document defines device tree properties for the Synopsys DesignWare MIPI

158
sys/contrib/device-tree/Bindings/display/bridge/toshiba,tc358767.yaml Normal file
View File

@ -0,0 +1,158 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/bridge/toshiba,tc358767.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Toshiba TC358767 eDP bridge bindings
maintainers:
- Andrey Gusakov <andrey.gusakov@cogentembedded.com>
description: The TC358767 is bridge device which converts DSI/DPI to eDP/DP
properties:
compatible:
const: toshiba,tc358767
reg:
enum:
- 0x68
- 0x0f
description: |
i2c address of the bridge, 0x68 or 0x0f, depending on bootstrap pins
clock-names:
const: "ref"
clocks:
maxItems: 1
description: |
OF device-tree clock specification for refclk input. The reference.
clock rate must be 13 MHz, 19.2 MHz, 26 MHz, or 38.4 MHz.
shutdown-gpios:
maxItems: 1
description: |
OF device-tree gpio specification for SD pin(active high shutdown input)
reset-gpios:
maxItems: 1
description: |
OF device-tree gpio specification for RSTX pin(active low system reset)
toshiba,hpd-pin:
$ref: /schemas/types.yaml#/definitions/uint32
enum:
- 0
- 1
description: TC358767 GPIO pin number to which HPD is connected to (0 or 1)
ports:
$ref: /schemas/graph.yaml#/properties/ports
properties:
port@0:
$ref: /schemas/graph.yaml#/properties/port
description: |
DSI input port. The remote endpoint phandle should be a
reference to a valid DSI output endpoint node
port@1:
$ref: /schemas/graph.yaml#/properties/port
description: |
DPI input port. The remote endpoint phandle should be a
reference to a valid DPI output endpoint node
port@2:
$ref: /schemas/graph.yaml#/properties/port
description: |
eDP/DP output port. The remote endpoint phandle should be a
reference to a valid eDP panel input endpoint node. This port is
optional, treated as DP panel if not defined
oneOf:
- required:
- port@0
- required:
- port@1
required:
- compatible
- reg
- clock-names
- clocks
- ports
additionalProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
/* DPI input and eDP output */
i2c {
#address-cells = <1>;
#size-cells = <0>;
edp-bridge@68 {
compatible = "toshiba,tc358767";
reg = <0x68>;
shutdown-gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>;
clock-names = "ref";
clocks = <&edp_refclk>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <1>;
bridge_in_0: endpoint {
remote-endpoint = <&dpi_out>;
};
};
port@2 {
reg = <2>;
bridge_out: endpoint {
remote-endpoint = <&panel_in>;
};
};
};
};
};
- |
/* DPI input and DP output */
i2c {
#address-cells = <1>;
#size-cells = <0>;
edp-bridge@68 {
compatible = "toshiba,tc358767";
reg = <0x68>;
shutdown-gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>;
clock-names = "ref";
clocks = <&edp_refclk>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <1>;
bridge_in_1: endpoint {
remote-endpoint = <&dpi_out>;
};
};
};
};
};

2
sys/contrib/device-tree/Bindings/display/ingenic,ipu.yaml
View File

@ -45,7 +45,7 @@ additionalProperties: false
examples:
- |
#include <dt-bindings/clock/jz4770-cgu.h>
#include <dt-bindings/clock/ingenic,jz4770-cgu.h>
ipu@13080000 {
compatible = "ingenic,jz4770-ipu", "ingenic,jz4760-ipu";
reg = <0x13080000 0x800>;

4
sys/contrib/device-tree/Bindings/display/ingenic,lcd.yaml
View File

@ -88,7 +88,7 @@ additionalProperties: false
examples:
- |
#include <dt-bindings/clock/jz4740-cgu.h>
#include <dt-bindings/clock/ingenic,jz4740-cgu.h>
lcd-controller@13050000 {
compatible = "ingenic,jz4740-lcd";
reg = <0x13050000 0x1000>;
@ -107,7 +107,7 @@ examples:
};
- |
#include <dt-bindings/clock/jz4725b-cgu.h>
#include <dt-bindings/clock/ingenic,jz4725b-cgu.h>
lcd-controller@13050000 {
compatible = "ingenic,jz4725b-lcd";
reg = <0x13050000 0x1000>;

6
sys/contrib/device-tree/Bindings/display/mediatek/mediatek,dsi.txt
View File

@ -19,6 +19,11 @@ Required properties:
Documentation/devicetree/bindings/graph.txt. This port should be connected
to the input port of an attached DSI panel or DSI-to-eDP encoder chip.
Optional properties:
- resets: list of phandle + reset specifier pair, as described in [1].
[1] Documentation/devicetree/bindings/reset/reset.txt
MIPI TX Configuration Module
============================
@ -45,6 +50,7 @@ dsi0: dsi@1401b000 {
clocks = <&mmsys MM_DSI0_ENGINE>, <&mmsys MM_DSI0_DIGITAL>,
<&mipi_tx0>;
clock-names = "engine", "digital", "hs";
resets = <&mmsys MT8173_MMSYS_SW0_RST_B_DISP_DSI0>;
phys = <&mipi_tx0>;
phy-names = "dphy";

16
sys/contrib/device-tree/Bindings/display/msm/dp-controller.yaml
View File

@ -17,9 +17,16 @@ properties:
compatible:
enum:
- qcom,sc7180-dp
- qcom,sc8180x-dp
- qcom,sc8180x-edp
reg:
maxItems: 1
items:
- description: ahb register block
- description: aux register block
- description: link register block
- description: p0 register block
- description: p1 register block
interrupts:
maxItems: 1
@ -95,12 +102,15 @@ examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,dispcc-sc7180.h>
#include <dt-bindings/power/qcom-aoss-qmp.h>
#include <dt-bindings/power/qcom-rpmpd.h>
displayport-controller@ae90000 {
compatible = "qcom,sc7180-dp";
reg = <0xae90000 0x1400>;
reg = <0xae90000 0x200>,
<0xae90200 0x200>,
<0xae90400 0xc00>,
<0xae91000 0x400>,
<0xae91400 0x400>;
interrupt-parent = <&mdss>;
interrupts = <12>;
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,

232
sys/contrib/device-tree/Bindings/display/msm/dpu-sc7280.yaml Normal file
View File

@ -0,0 +1,232 @@
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/msm/dpu-sc7280.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Display DPU dt properties for SC7280
maintainers:
- Krishna Manikandan <mkrishn@codeaurora.org>
description: |
Device tree bindings for MSM Mobile Display Subsystem (MDSS) that encapsulates
sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
bindings of MDSS and DPU are mentioned for SC7280.
properties:
compatible:
const: qcom,sc7280-mdss
reg:
maxItems: 1
reg-names:
const: mdss
power-domains:
maxItems: 1
clocks:
items:
- description: Display AHB clock from gcc
- description: Display AHB clock from dispcc
- description: Display core clock
clock-names:
items:
- const: iface
- const: ahb
- const: core
interrupts:
maxItems: 1
interrupt-controller: true
"#address-cells": true
"#size-cells": true
"#interrupt-cells":
const: 1
iommus:
items:
- description: Phandle to apps_smmu node with SID mask for Hard-Fail port0
ranges: true
interconnects:
items:
- description: Interconnect path specifying the port ids for data bus
interconnect-names:
const: mdp0-mem
patternProperties:
"^display-controller@[0-9a-f]+$":
type: object
description: Node containing the properties of DPU.
properties:
compatible:
const: qcom,sc7280-dpu
reg:
items:
- description: Address offset and size for mdp register set
- description: Address offset and size for vbif register set
reg-names:
items:
- const: mdp
- const: vbif
clocks:
items:
- description: Display hf axi clock
- description: Display sf axi clock
- description: Display ahb clock
- description: Display lut clock
- description: Display core clock
- description: Display vsync clock
clock-names:
items:
- const: bus
- const: nrt_bus
- const: iface
- const: lut
- const: core
- const: vsync
interrupts:
maxItems: 1
power-domains:
maxItems: 1
operating-points-v2: true
ports:
$ref: /schemas/graph.yaml#/properties/ports
description: |
Contains the list of output ports from DPU device. These ports
connect to interfaces that are external to the DPU hardware,
such as DSI, DP etc. Each output port contains an endpoint that
describes how it is connected to an external interface.
properties:
port@0:
$ref: /schemas/graph.yaml#/properties/port
description: DPU_INTF1 (DSI)
port@1:
$ref: /schemas/graph.yaml#/properties/port
description: DPU_INTF5 (EDP)
required:
- port@0
required:
- compatible
- reg
- reg-names
- clocks
- interrupts
- power-domains
- operating-points-v2
- ports
required:
- compatible
- reg
- reg-names
- power-domains
- clocks
- interrupts
- interrupt-controller
- iommus
- ranges
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,dispcc-sc7280.h>
#include <dt-bindings/clock/qcom,gcc-sc7280.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interconnect/qcom,sc7280.h>
#include <dt-bindings/power/qcom-rpmpd.h>
display-subsystem@ae00000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "qcom,sc7280-mdss";
reg = <0xae00000 0x1000>;
reg-names = "mdss";
power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>;
clocks = <&gcc GCC_DISP_AHB_CLK>,
<&dispcc DISP_CC_MDSS_AHB_CLK>,
<&dispcc DISP_CC_MDSS_MDP_CLK>;
clock-names = "iface",
"ahb",
"core";
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <1>;
interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>;
interconnect-names = "mdp0-mem";
iommus = <&apps_smmu 0x900 0x402>;
ranges;
display-controller@ae01000 {
compatible = "qcom,sc7280-dpu";
reg = <0x0ae01000 0x8f000>,
<0x0aeb0000 0x2008>;
reg-names = "mdp", "vbif";
clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
<&gcc GCC_DISP_SF_AXI_CLK>,
<&dispcc DISP_CC_MDSS_AHB_CLK>,
<&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
<&dispcc DISP_CC_MDSS_MDP_CLK>,
<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
clock-names = "bus",
"nrt_bus",
"iface",
"lut",
"core",
"vsync";
interrupt-parent = <&mdss>;
interrupts = <0>;
power-domains = <&rpmhpd SC7280_CX>;
operating-points-v2 = <&mdp_opp_table>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dpu_intf1_out: endpoint {
remote-endpoint = <&dsi0_in>;
};
};
port@1 {
reg = <1>;
dpu_intf5_out: endpoint {
remote-endpoint = <&edp_in>;
};
};
};
};
};
...

1
sys/contrib/device-tree/Bindings/display/msm/dsi-phy-14nm.yaml
View File

@ -17,6 +17,7 @@ properties:
enum:
- qcom,dsi-phy-14nm
- qcom,dsi-phy-14nm-660
- qcom,dsi-phy-14nm-8953
reg:
items:

288
sys/contrib/device-tree/Bindings/display/msm/gpu.yaml Normal file
View File

@ -0,0 +1,288 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/display/msm/gpu.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Devicetree bindings for the Adreno or Snapdragon GPUs
maintainers:
- Rob Clark <robdclark@gmail.com>
properties:
compatible:
oneOf:
- description: |
The driver is parsing the compat string for Adreno to
figure out the gpu-id and patch level.
items:
- pattern: '^qcom,adreno-[3-6][0-9][0-9]\.[0-9]$'
- const: qcom,adreno
- description: |
The driver is parsing the compat string for Imageon to
figure out the gpu-id and patch level.
items:
- pattern: '^amd,imageon-200\.[0-1]$'
- const: amd,imageon
clocks: true
clock-names: true
reg:
minItems: 1
maxItems: 3
reg-names:
minItems: 1
items:
- const: kgsl_3d0_reg_memory
- const: cx_mem
- const: cx_dbgc
interrupts:
maxItems: 1
interrupt-names:
maxItems: 1
interconnects:
minItems: 1
maxItems: 2
interconnect-names:
minItems: 1
items:
- const: gfx-mem
- const: ocmem
iommus:
maxItems: 1
sram:
$ref: /schemas/types.yaml#/definitions/phandle-array
minItems: 1
maxItems: 4
description: |
phandles to one or more reserved on-chip SRAM regions.
phandle to the On Chip Memory (OCMEM) that's present on some a3xx and
a4xx Snapdragon SoCs. See
Documentation/devicetree/bindings/sram/qcom,ocmem.yaml
operating-points-v2: true
opp-table:
type: object
power-domains:
maxItems: 1
zap-shader:
type: object
description: |
For a5xx and a6xx devices this node contains a memory-region that
points to reserved memory to store the zap shader that can be used to
help bring the GPU out of secure mode.
properties:
memory-region:
$ref: /schemas/types.yaml#/definitions/phandle
firmware-name:
description: |
Default name of the firmware to load to the remote processor.
"#cooling-cells":
const: 2
nvmem-cell-names:
maxItems: 1
nvmem-cells:
description: efuse registers
maxItems: 1
qcom,gmu:
$ref: /schemas/types.yaml#/definitions/phandle
description: |
For GMU attached devices a phandle to the GMU device that will
control the power for the GPU.
required:
- compatible
- reg
- interrupts
additionalProperties: false
allOf:
- if:
properties:
compatible:
contains:
pattern: '^qcom,adreno-[3-5][0-9][0-9]\.[0-9]$'
then:
properties:
clocks:
minItems: 2
maxItems: 7
clock-names:
items:
anyOf:
- const: core
description: GPU Core clock
- const: iface
description: GPU Interface clock
- const: mem
description: GPU Memory clock
- const: mem_iface
description: GPU Memory Interface clock
- const: alt_mem_iface
description: GPU Alternative Memory Interface clock
- const: gfx3d
description: GPU 3D engine clock
- const: rbbmtimer
description: GPU RBBM Timer for Adreno 5xx series
minItems: 2
maxItems: 7
required:
- clocks
- clock-names
- if:
properties:
compatible:
contains:
pattern: '^qcom,adreno-6[0-9][0-9]\.[0-9]$'
then: # Since Adreno 6xx series clocks should be defined in GMU
properties:
clocks: false
clock-names: false
examples:
- |
// Example a3xx/4xx:
#include <dt-bindings/clock/qcom,mmcc-msm8974.h>
#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
gpu: gpu@fdb00000 {
compatible = "qcom,adreno-330.2", "qcom,adreno";
reg = <0xfdb00000 0x10000>;
reg-names = "kgsl_3d0_reg_memory";
clock-names = "core", "iface", "mem_iface";
clocks = <&mmcc OXILI_GFX3D_CLK>,
<&mmcc OXILICX_AHB_CLK>,
<&mmcc OXILICX_AXI_CLK>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "kgsl_3d0_irq";
sram = <&gpu_sram>;
power-domains = <&mmcc OXILICX_GDSC>;
operating-points-v2 = <&gpu_opp_table>;
iommus = <&gpu_iommu 0>;
#cooling-cells = <2>;
};
ocmem@fdd00000 {
compatible = "qcom,msm8974-ocmem";
reg = <0xfdd00000 0x2000>,
<0xfec00000 0x180000>;
reg-names = "ctrl", "mem";
clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>,
<&mmcc OCMEMCX_OCMEMNOC_CLK>;
clock-names = "core", "iface";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xfec00000 0x100000>;
gpu_sram: gpu-sram@0 {
reg = <0x0 0x100000>;
};
};
- |
// Example a6xx (with GMU):
#include <dt-bindings/clock/qcom,gpucc-sdm845.h>
#include <dt-bindings/clock/qcom,gcc-sdm845.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interconnect/qcom,sdm845.h>
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
zap_shader_region: gpu@8f200000 {
compatible = "shared-dma-pool";
reg = <0x0 0x90b00000 0x0 0xa00000>;
no-map;
};
};
gpu@5000000 {
compatible = "qcom,adreno-630.2", "qcom,adreno";
reg = <0x5000000 0x40000>, <0x509e000 0x10>;
reg-names = "kgsl_3d0_reg_memory", "cx_mem";
#cooling-cells = <2>;
interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
iommus = <&adreno_smmu 0>;
operating-points-v2 = <&gpu_opp_table>;
interconnects = <&rsc_hlos MASTER_GFX3D &rsc_hlos SLAVE_EBI1>;
interconnect-names = "gfx-mem";
qcom,gmu = <&gmu>;
gpu_opp_table: opp-table {
compatible = "operating-points-v2";
opp-430000000 {
opp-hz = /bits/ 64 <430000000>;
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
opp-peak-kBps = <5412000>;
};
opp-355000000 {
opp-hz = /bits/ 64 <355000000>;
opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
opp-peak-kBps = <3072000>;
};
opp-267000000 {
opp-hz = /bits/ 64 <267000000>;
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
opp-peak-kBps = <3072000>;
};
opp-180000000 {
opp-hz = /bits/ 64 <180000000>;
opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
opp-peak-kBps = <1804000>;
};
};
zap-shader {
memory-region = <&zap_shader_region>;
firmware-name = "qcom/LENOVO/81JL/qcdxkmsuc850.mbn";
};
};

7
sys/contrib/device-tree/Bindings/display/panel/boe,tv101wum-nl6.yaml
View File

@ -26,6 +26,10 @@ properties:
- auo,b101uan08.3
# BOE TV105WUM-NW0 10.5" WUXGA TFT LCD panel
- boe,tv105wum-nw0
# BOE TV110C9M-LL3 10.95" WUXGA TFT LCD panel
- boe,tv110c9m-ll3
# INX HJ110IZ-01A 10.95" WUXGA TFT LCD panel
- innolux,hj110iz-01a
reg:
description: the virtual channel number of a DSI peripheral
@ -36,6 +40,9 @@ properties:
pp1800-supply:
description: core voltage supply
pp3300-supply:
description: core voltage supply
avdd-supply:
description: phandle of the regulator that provides positive voltage

2
sys/contrib/device-tree/Bindings/display/panel/orisetech,otm8009a.yaml
View File

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Orise Tech OTM8009A 3.97" 480x800 TFT LCD panel (MIPI-DSI video mode)
maintainers:
- Philippe CORNU <philippe.cornu@st.com>
- Philippe CORNU <philippe.cornu@foss.st.com>
description: |
The Orise Tech OTM8009A is a 3.97" 480x800 TFT LCD panel connected using

188
sys/contrib/device-tree/Bindings/display/panel/panel-edp.yaml Normal file
View File

@ -0,0 +1,188 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/panel/panel-edp.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Probeable (via DP AUX / EDID) eDP Panels with simple poweron sequences
maintainers:
- Douglas Anderson <dianders@chromium.org>
description: |
This binding file can be used to indicate that an eDP panel is connected
to a Embedded DisplayPort AUX bus (see display/dp-aux-bus.yaml) without
actually specifying exactly what panel is connected. This is useful for
the case that more than one different panel could be connected to the
board, either for second-sourcing purposes or to support multiple SKUs
with different LCDs that hook up to a common board.
As per above, a requirement for using this binding is that the panel is
represented under the DP AUX bus. This means that we can use any
information provided by the DP AUX bus (including the EDID) to identify
the panel. We can use this to identify display size, resolution, and
timings among other things.
One piece of information about eDP panels that is typically _not_
provided anywhere on the DP AUX bus is the power sequencing timings.
This is the reason why, historically, we've always had to explicitly
list eDP panels. We solve that here with two tricks. The "worst case"
power on timings for any panels expected to be connected to a board are
specified in these bindings. Once we've powered on, it's expected that
the operating system will lookup the panel in a table (based on EDID
information) to figure out other power sequencing timings.
eDP panels in general can have somewhat arbitrary power sequencing
requirements. However, even though it's arbitrary in general, the
vast majority of panel datasheets have a power sequence diagram that
looks the exactly the same as every other panel. Each panel datasheet
cares about different timings in this diagram but the fact that the
diagram is so similar means we can come up with a single driver to
handle it.
These diagrams all look roughly like this, sometimes labeled with
slightly different numbers / lines but all pretty much the same
sequence. This is because much of this diagram comes straight from
the eDP Standard.
__________________________________________________
Vdd ___/: :\____ /
_/ : : \_____/
:<T1>:<T2>: :<--T10-->:<T11>:<T12>:
: +-----------------------+---------+---------+
eDP -----------+ Black video | Src vid | Blk vid +
Display : +-----------------------+---------+---------+
: _______________________:_________:_________:
HPD :<T3>| : : |
___________| : : |_____________
: : : :
Sink +-----------------------:---------:---------+
AUX CH -----------+ AUX Ch operational : : +-------------
+-----------------------:---------:---------+
: : : :
:<T4>: :<T7>: : :
Src main +------+------+--------------+---------+
lnk data----------------+LnkTrn| Idle |Valid vid data| Idle/off+-------------
+------+------+--------------+---------+
: <T5> :<-T6->:<-T8->: :
:__:<T9>:
LED_EN | |
_____________________________________| |____________________________
: :
__________:__:_
PWM | : : |
__________________________| : : |__________________________
: : : :
_____________:__________:__:_:______
Bklight ____/: : : : : :\____
power _______/ :<---T13---->: : : :<T16>: \______________
(Vbl) :<T17>:<---------T14--------->: :<-T15->:<T18>:
The above looks fairly complex but, as per above, each panel only cares
about a subset of those timings.
allOf:
- $ref: panel-common.yaml#
properties:
compatible:
const: edp-panel
hpd-reliable-delay-ms:
description:
A fixed amount of time that must be waited after powering on the
panel's power-supply before the HPD signal is a reliable way to know
when the AUX channel is ready. This is useful for panels that glitch
the HPD at the start of power-on. This value is not needed if HPD is
always reliable for all panels that might be connected.
hpd-absent-delay-ms:
description:
The panel specifies that HPD will be asserted this many milliseconds
from power on (timing T3 in the diagram above). If we have no way to
measure HPD then a fixed delay of this many milliseconds can be used.
This can also be used as a timeout when waiting for HPD. Does not
include the hpd-reliable-delay, so if hpd-reliable-delay was 80 ms
and hpd-absent-delay was 200 ms then we'd do a fixed 80 ms delay and
then we know HPD would assert in the next 120 ms. This value is not
needed if HPD hooked up, either through a GPIO in the panel node or
hooked up directly to the eDP controller.
backlight: true
enable-gpios: true
port: true
power-supply: true
no-hpd: true
hpd-gpios: true
additionalProperties: false
required:
- compatible
- power-supply
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
i2c {
#address-cells = <1>;
#size-cells = <0>;
bridge@2d {
compatible = "ti,sn65dsi86";
reg = <0x2d>;
interrupt-parent = <&tlmm>;
interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
enable-gpios = <&tlmm 102 GPIO_ACTIVE_HIGH>;
vpll-supply = <&src_pp1800_s4a>;
vccio-supply = <&src_pp1800_s4a>;
vcca-supply = <&src_pp1200_l2a>;
vcc-supply = <&src_pp1200_l2a>;
clocks = <&rpmhcc RPMH_LN_BB_CLK2>;
clock-names = "refclk";
no-hpd;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
endpoint {
remote-endpoint = <&dsi0_out>;
};
};
port@1 {
reg = <1>;
sn65dsi86_out: endpoint {
remote-endpoint = <&panel_in_edp>;
};
};
};
aux-bus {
panel {
compatible = "edp-panel";
power-supply = <&pp3300_dx_edp>;
backlight = <&backlight>;
hpd-gpios = <&sn65dsi86_bridge 2 GPIO_ACTIVE_HIGH>;
hpd-reliable-delay-ms = <15>;
port {
panel_in_edp: endpoint {
remote-endpoint = <&sn65dsi86_out>;
};
};
};
};
};
};

5
sys/contrib/device-tree/Bindings/display/panel/panel-simple.yaml
View File

@ -166,6 +166,8 @@ properties:
- innolux,at070tn92
# Innolux G070Y2-L01 7" WVGA (800x480) TFT LCD panel
- innolux,g070y2-l01
# Innolux G070Y2-T02 7" WVGA (800x480) TFT LCD TTL panel
- innolux,g070y2-t02
# Innolux Corporation 10.1" G101ICE-L01 WXGA (1280x800) LVDS panel
- innolux,g101ice-l01
# Innolux Corporation 12.1" WXGA (1280x800) TFT LCD panel
@ -309,6 +311,8 @@ properties:
- urt,umsh-8596md-11t
- urt,umsh-8596md-19t
- urt,umsh-8596md-20t
# Vivax TPC-9150 tablet 9.0" WSVGA TFT LCD panel
- vivax,tpc9150-panel
# VXT 800x480 color TFT LCD panel
- vxt,vl050-8048nt-c01
# Winstar Display Corporation 3.5" QVGA (320x240) TFT LCD panel
@ -317,6 +321,7 @@ properties:
- yes-optoelectronics,ytc700tlag-05-201c
backlight: true
ddc-i2c-bus: true
enable-gpios: true
port: true
power-supply: true

2
sys/contrib/device-tree/Bindings/display/panel/raydium,rm68200.yaml
View File

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Raydium Semiconductor Corporation RM68200 5.5" 720p MIPI-DSI TFT LCD panel
maintainers:
- Philippe CORNU <philippe.cornu@st.com>
- Philippe CORNU <philippe.cornu@foss.st.com>
description: |
The Raydium Semiconductor Corporation RM68200 is a 5.5" 720x1280 TFT LCD

98
sys/contrib/device-tree/Bindings/display/panel/samsung,s6d27a1.yaml Normal file
View File

@ -0,0 +1,98 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/panel/samsung,s6d27a1.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Samsung S6D27A1 display panel
description: The S6D27A1 is a 480x800 DPI display panel from Samsung Mobile
Displays (SMD). The panel must obey the rules for a SPI slave device
as specified in spi/spi-controller.yaml
maintainers:
- Markuss Broks <markuss.broks@gmail.com>
allOf:
- $ref: panel-common.yaml#
properties:
compatible:
const: samsung,s6d27a1
reg: true
interrupts:
description: provides an optional ESD (electrostatic discharge)
interrupt that signals abnormalities in the display hardware.
This can also be raised for other reasons like erroneous
configuration.
maxItems: 1
reset-gpios: true
vci-supply:
description: regulator that supplies the VCI analog voltage
usually around 3.0 V
vccio-supply:
description: regulator that supplies the VCCIO voltage usually
around 1.8 V
backlight: true
spi-cpha: true
spi-cpol: true
spi-max-frequency:
maximum: 1200000
port: true
required:
- compatible
- reg
- vci-supply
- vccio-supply
- spi-cpha
- spi-cpol
- port
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
spi {
compatible = "spi-gpio";
sck-gpios = <&gpio 0 GPIO_ACTIVE_HIGH>;
miso-gpios = <&gpio 1 GPIO_ACTIVE_HIGH>;
mosi-gpios = <&gpio 2 GPIO_ACTIVE_HIGH>;
cs-gpios = <&gpio 3 GPIO_ACTIVE_HIGH>;
num-chipselects = <1>;
#address-cells = <1>;
#size-cells = <0>;
panel@0 {
compatible = "samsung,s6d27a1";
spi-max-frequency = <1200000>;
spi-cpha;
spi-cpol;
reg = <0>;
vci-supply = <&lcd_3v0_reg>;
vccio-supply = <&lcd_1v8_reg>;
reset-gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
interrupt-parent = <&gpio>;
interrupts = <5 IRQ_TYPE_EDGE_RISING>;
port {
panel_in: endpoint {
remote-endpoint = <&display_out>;
};
};
};
};
...

56
sys/contrib/device-tree/Bindings/display/panel/sharp,ls060t1sx01.yaml Normal file
View File

@ -0,0 +1,56 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/panel/sharp,ls060t1sx01.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Sharp Microelectronics 6.0" FullHD TFT LCD panel
maintainers:
- Dmitry Baryskov <dmitry.baryshkov@linaro.org>
allOf:
- $ref: panel-common.yaml#
properties:
compatible:
const: sharp,ls060t1sx01
reg: true
backlight: true
reset-gpios: true
port: true
avdd-supply:
description: handle of the regulator that provides the positive supply voltage
avee-supply:
description: handle of the regulator that provides the negative supply voltage
vddi-supply:
description: handle of the regulator that provides the I/O supply voltage
vddh-supply:
description: handle of the regulator that provides the analog supply voltage
required:
- compatible
- reg
additionalProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
dsi {
#address-cells = <1>;
#size-cells = <0>;
panel@0 {
compatible = "sharp,ls060t1sx01";
reg = <0>;
avdd-supply = <&pm8941_l22>;
backlight = <&backlight>;
reset-gpios = <&pm8916_gpios 25 GPIO_ACTIVE_LOW>;
};
};
...

51
sys/contrib/device-tree/Bindings/display/renesas,du.yaml
View File

@ -39,6 +39,7 @@ properties:
- renesas,du-r8a77980 # for R-Car V3H compatible DU
- renesas,du-r8a77990 # for R-Car E3 compatible DU
- renesas,du-r8a77995 # for R-Car D3 compatible DU
- renesas,du-r8a779a0 # for R-Car V3U compatible DU
reg:
maxItems: 1
@ -773,6 +774,56 @@ allOf:
- reset-names
- renesas,vsps
- if:
properties:
compatible:
contains:
enum:
- renesas,du-r8a779a0
then:
properties:
clocks:
items:
- description: Functional clock
clock-names:
maxItems: 1
items:
- const: du.0
interrupts:
maxItems: 2
resets:
maxItems: 1
reset-names:
items:
- const: du.0
ports:
properties:
port@0:
description: DSI 0
port@1:
description: DSI 1
port@2: false
port@3: false
required:
- port@0
- port@1
renesas,vsps:
minItems: 2
required:
- clock-names
- interrupts
- resets
- reset-names
- renesas,vsps
additionalProperties: false
examples:

4
sys/contrib/device-tree/Bindings/display/st,stm32-dsi.yaml
View File

@ -7,8 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: STMicroelectronics STM32 DSI host controller
maintainers:
- Philippe Cornu <philippe.cornu@st.com>
- Yannick Fertre <yannick.fertre@st.com>
- Philippe Cornu <philippe.cornu@foss.st.com>
- Yannick Fertre <yannick.fertre@foss.st.com>
description:
The STMicroelectronics STM32 DSI controller uses the Synopsys DesignWare MIPI-DSI host controller.

4
sys/contrib/device-tree/Bindings/display/st,stm32-ltdc.yaml
View File

@ -7,8 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: STMicroelectronics STM32 lcd-tft display controller
maintainers:
- Philippe Cornu <philippe.cornu@st.com>
- Yannick Fertre <yannick.fertre@st.com>
- Philippe Cornu <philippe.cornu@foss.st.com>
- Yannick Fertre <yannick.fertre@foss.st.com>
properties:
compatible:

4
sys/contrib/device-tree/Bindings/display/tilcdc/tilcdc.txt
View File

@ -60,7 +60,7 @@ Example:
blue-and-red-wiring = "crossed";
port {
lcdc_0: endpoint@0 {
lcdc_0: endpoint {
remote-endpoint = <&hdmi_0>;
};
};
@ -75,7 +75,7 @@ Example:
pinctrl-1 = <&nxp_hdmi_bonelt_off_pins>;
port {
hdmi_0: endpoint@0 {
hdmi_0: endpoint {
remote-endpoint = <&lcdc_0>;
};
};

4
sys/contrib/device-tree/Bindings/display/xlnx/xlnx,zynqmp-dpsub.yaml
View File

@ -160,8 +160,8 @@ examples:
<&xlnx_dpdma 2>,
<&xlnx_dpdma 3>;
phys = <&psgtr 1 PHY_TYPE_DP 0 3 27000000>,
<&psgtr 0 PHY_TYPE_DP 1 3 27000000>;
phys = <&psgtr 1 PHY_TYPE_DP 0 3>,
<&psgtr 0 PHY_TYPE_DP 1 3>;
phy-names = "dp-phy0", "dp-phy1";
};

301
sys/contrib/device-tree/Bindings/display/xylon,logicvc-display.yaml Normal file
View File

@ -0,0 +1,301 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
# Copyright 2019 Bootlin
%YAML 1.2
---
$id: "http://devicetree.org/schemas/display/xylon,logicvc-display.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Xylon LogiCVC display controller
maintainers:
- Paul Kocialkowski <paul.kocialkowski@bootlin.com>
description: |
The Xylon LogiCVC is a display controller that supports multiple layers.
It is usually implemented as programmable logic and was optimized for use
with Xilinx Zynq-7000 SoCs and Xilinx FPGAs.
Because the controller is intended for use in a FPGA, most of the
configuration of the controller takes place at logic configuration bitstream
synthesis time. As a result, many of the device-tree bindings are meant to
reflect the synthesis configuration and must not be configured differently.
Matching synthesis parameters are provided when applicable.
Layers are declared in the "layers" sub-node and have dedicated configuration.
In version 3 of the controller, each layer has fixed memory offset and address
starting from the video memory base address for its framebuffer. In version 4,
framebuffers are configured with a direct memory address instead.
properties:
compatible:
enum:
- xylon,logicvc-3.02.a-display
- xylon,logicvc-4.01.a-display
reg:
maxItems: 1
clocks:
minItems: 1
maxItems: 4
clock-names:
minItems: 1
items:
# vclk is required and must be provided as first item.
- const: vclk
# Other clocks are optional and can be provided in any order.
- enum:
- vclk2
- lvdsclk
- lvdsclkn
- enum:
- vclk2
- lvdsclk
- lvdsclkn
- enum:
- vclk2
- lvdsclk
- lvdsclkn
interrupts:
maxItems: 1
memory-region:
maxItems: 1
xylon,display-interface:
enum:
# Parallel RGB interface (C_DISPLAY_INTERFACE == 0)
- parallel-rgb
# ITU-T BR656 interface (C_DISPLAY_INTERFACE == 1)
- bt656
# 4-bit LVDS interface (C_DISPLAY_INTERFACE == 2)
- lvds-4bits
# 3-bit LVDS interface (C_DISPLAY_INTERFACE == 4)
- lvds-3bits
# DVI interface (C_DISPLAY_INTERFACE == 5)
- dvi
description: Display output interface (C_DISPLAY_INTERFACE).
xylon,display-colorspace:
enum:
# RGB colorspace (C_DISPLAY_COLOR_SPACE == 0)
- rgb
# YUV 4:2:2 colorspace (C_DISPLAY_COLOR_SPACE == 1)
- yuv422
# YUV 4:4:4 colorspace (C_DISPLAY_COLOR_SPACE == 2)
- yuv444
description: Display output colorspace (C_DISPLAY_COLOR_SPACE).
xylon,display-depth:
$ref: "/schemas/types.yaml#/definitions/uint32"
description: Display output depth (C_PIXEL_DATA_WIDTH).
xylon,row-stride:
$ref: "/schemas/types.yaml#/definitions/uint32"
description: Fixed number of pixels in a framebuffer row (C_ROW_STRIDE).
xylon,dithering:
$ref: "/schemas/types.yaml#/definitions/flag"
description: Dithering module is enabled (C_XCOLOR)
xylon,background-layer:
$ref: "/schemas/types.yaml#/definitions/flag"
description: |
The last layer is used to display a black background (C_USE_BACKGROUND).
The layer must still be registered.
xylon,layers-configurable:
$ref: "/schemas/types.yaml#/definitions/flag"
description: |
Configuration of layers' size, position and offset is enabled
(C_USE_SIZE_POSITION).
layers:
type: object
properties:
"#address-cells":
const: 1
"#size-cells":
const: 0
patternProperties:
"^layer@[0-9]+$":
type: object
properties:
reg:
maxItems: 1
xylon,layer-depth:
$ref: "/schemas/types.yaml#/definitions/uint32"
description: Layer depth (C_LAYER_X_DATA_WIDTH).
xylon,layer-colorspace:
enum:
# RGB colorspace (C_LAYER_X_TYPE == 0)
- rgb
# YUV packed colorspace (C_LAYER_X_TYPE == 0)
- yuv
description: Layer colorspace (C_LAYER_X_TYPE).
xylon,layer-alpha-mode:
enum:
# Alpha is configured layer-wide (C_LAYER_X_ALPHA_MODE == 0)
- layer
# Alpha is configured per-pixel (C_LAYER_X_ALPHA_MODE == 1)
- pixel
description: Alpha mode for the layer (C_LAYER_X_ALPHA_MODE).
xylon,layer-base-offset:
$ref: "/schemas/types.yaml#/definitions/uint32"
description: |
Offset in number of lines (C_LAYER_X_OFFSET) starting from the
video RAM base (C_VMEM_BASEADDR), only for version 3.
xylon,layer-buffer-offset:
$ref: "/schemas/types.yaml#/definitions/uint32"
description: |
Offset in number of lines (C_BUFFER_*_OFFSET) starting from the
layer base offset for the second buffer used in double-buffering.
xylon,layer-primary:
$ref: "/schemas/types.yaml#/definitions/flag"
description: |
Layer should be registered as a primary plane (exactly one is
required).
additionalProperties: false
required:
- reg
- xylon,layer-depth
- xylon,layer-colorspace
- xylon,layer-alpha-mode
required:
- "#address-cells"
- "#size-cells"
- layer@0
additionalProperties: false
description: |
The description of the display controller layers, containing layer
sub-nodes that each describe a registered layer.
port:
$ref: /schemas/graph.yaml#/properties/port
description: |
Video output port, typically connected to a panel or bridge.
additionalProperties: false
required:
- compatible
- reg
- clocks
- clock-names
- interrupts
- xylon,display-interface
- xylon,display-colorspace
- xylon,display-depth
- xylon,row-stride
- layers
- port
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
logicvc: logicvc@43c00000 {
compatible = "xylon,logicvc-3.02.a", "syscon", "simple-mfd";
reg = <0x43c00000 0x6000>;
#address-cells = <1>;
#size-cells = <1>;
logicvc_display: display@0 {
compatible = "xylon,logicvc-3.02.a-display";
reg = <0x0 0x6000>;
memory-region = <&logicvc_cma>;
clocks = <&logicvc_vclk 0>, <&logicvc_lvdsclk 0>;
clock-names = "vclk", "lvdsclk";
interrupt-parent = <&intc>;
interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
xylon,display-interface = "lvds-4bits";
xylon,display-colorspace = "rgb";
xylon,display-depth = <16>;
xylon,row-stride = <1024>;
xylon,layers-configurable;
layers {
#address-cells = <1>;
#size-cells = <0>;
layer@0 {
reg = <0>;
xylon,layer-depth = <16>;
xylon,layer-colorspace = "rgb";
xylon,layer-alpha-mode = "layer";
xylon,layer-base-offset = <0>;
xylon,layer-buffer-offset = <480>;
xylon,layer-primary;
};
layer@1 {
reg = <1>;
xylon,layer-depth = <16>;
xylon,layer-colorspace = "rgb";
xylon,layer-alpha-mode = "layer";
xylon,layer-base-offset = <2400>;
xylon,layer-buffer-offset = <480>;
};
layer@2 {
reg = <2>;
xylon,layer-depth = <16>;
xylon,layer-colorspace = "rgb";
xylon,layer-alpha-mode = "layer";
xylon,layer-base-offset = <960>;
xylon,layer-buffer-offset = <480>;
};
layer@3 {
reg = <3>;
xylon,layer-depth = <16>;
xylon,layer-colorspace = "rgb";
xylon,layer-alpha-mode = "layer";
xylon,layer-base-offset = <480>;
xylon,layer-buffer-offset = <480>;
};
layer@4 {
reg = <4>;
xylon,layer-depth = <16>;
xylon,layer-colorspace = "rgb";
xylon,layer-alpha-mode = "layer";
xylon,layer-base-offset = <8192>;
xylon,layer-buffer-offset = <480>;
};
};
port {
#address-cells = <1>;
#size-cells = <0>;
logicvc_output: endpoint@0 {
reg = <0>;
remote-endpoint = <&panel_input>;
};
};
};
};

2
sys/contrib/device-tree/Bindings/dma/ingenic,dma.yaml
View File

@ -68,7 +68,7 @@ unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/jz4780-cgu.h>
#include <dt-bindings/clock/ingenic,jz4780-cgu.h>
dma: dma-controller@13420000 {
compatible = "ingenic,jz4780-dma";
reg = <0x13420000 0x400>, <0x13421000 0x40>;

2
sys/contrib/device-tree/Bindings/dma/qcom_bam_dma.txt
View File

@ -15,6 +15,8 @@ Required properties:
the secure world.
- qcom,controlled-remotely : optional, indicates that the bam is controlled by
remote proccessor i.e. execution environment.
- qcom,powered-remotely : optional, indicates that the bam is powered up by
a remote processor but must be initialized by the local processor.
- num-channels : optional, indicates supported number of DMA channels in a
remotely controlled bam.
- qcom,num-ees : optional, indicates supported number of Execution Environments

2
sys/contrib/device-tree/Bindings/dma/st,stm32-dma.yaml
View File

@ -50,7 +50,7 @@ description: |
maintainers:
- Amelie Delaunay <amelie.delaunay@st.com>
- Amelie Delaunay <amelie.delaunay@foss.st.com>
allOf:
- $ref: "dma-controller.yaml#"

2
sys/contrib/device-tree/Bindings/dma/st,stm32-dmamux.yaml
View File

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: STMicroelectronics STM32 DMA MUX (DMA request router) bindings
maintainers:
- Amelie Delaunay <amelie.delaunay@st.com>
- Amelie Delaunay <amelie.delaunay@foss.st.com>
allOf:
- $ref: "dma-router.yaml#"

2
sys/contrib/device-tree/Bindings/dma/st,stm32-mdma.yaml
View File

@ -50,7 +50,7 @@ description: |
if no HW ack signal is used by the MDMA client
maintainers:
- Amelie Delaunay <amelie.delaunay@st.com>
- Amelie Delaunay <amelie.delaunay@foss.st.com>
allOf:
- $ref: "dma-controller.yaml#"

123
sys/contrib/device-tree/Bindings/dsp/fsl,dsp.yaml
View File

@ -8,6 +8,7 @@ title: NXP i.MX8 DSP core
maintainers:
- Daniel Baluta <daniel.baluta@nxp.com>
- Shengjiu Wang <shengjiu.wang@nxp.com>
description: |
Some boards from i.MX8 family contain a DSP core used for
@ -19,6 +20,10 @@ properties:
- fsl,imx8qxp-dsp
- fsl,imx8qm-dsp
- fsl,imx8mp-dsp
- fsl,imx8qxp-hifi4
- fsl,imx8qm-hifi4
- fsl,imx8mp-hifi4
- fsl,imx8ulp-hifi4
reg:
maxItems: 1
@ -28,37 +33,53 @@ properties:
- description: ipg clock
- description: ocram clock
- description: core clock
- description: debug interface clock
- description: message unit clock
minItems: 3
clock-names:
items:
- const: ipg
- const: ocram
- const: core
- const: debug
- const: mu
minItems: 3
power-domains:
description:
List of phandle and PM domain specifier as documented in
Documentation/devicetree/bindings/power/power_domain.txt
minItems: 1
maxItems: 4
mboxes:
description:
List of <&phandle type channel> - 2 channels for TXDB, 2 channels for RXDB
or - 1 channel for TX, 1 channel for RX, 1 channel for RXDB
(see mailbox/fsl,mu.txt)
minItems: 3
maxItems: 4
mbox-names:
items:
- const: txdb0
- const: txdb1
- const: rxdb0
- const: rxdb1
minItems: 3
maxItems: 4
memory-region:
description:
phandle to a node describing reserved memory (System RAM memory)
used by DSP (see bindings/reserved-memory/reserved-memory.txt)
maxItems: 1
minItems: 1
maxItems: 4
firmware-name:
description: |
Default name of the firmware to load to the remote processor.
fsl,dsp-ctrl:
$ref: /schemas/types.yaml#/definitions/phandle
description:
Phandle to syscon block which provide access for processor enablement
required:
- compatible
@ -70,6 +91,58 @@ required:
- mbox-names
- memory-region
allOf:
- if:
properties:
compatible:
contains:
enum:
- fsl,imx8qxp-dsp
- fsl,imx8qm-dsp
- fsl,imx8qxp-hifi4
- fsl,imx8qm-hifi4
then:
properties:
power-domains:
minItems: 4
else:
properties:
power-domains:
maxItems: 1
- if:
properties:
compatible:
contains:
enum:
- fsl,imx8qxp-hifi4
- fsl,imx8qm-hifi4
- fsl,imx8mp-hifi4
- fsl,imx8ulp-hifi4
then:
properties:
memory-region:
minItems: 4
mboxes:
maxItems: 3
mbox-names:
items:
- const: tx
- const: rx
- const: rxdb
else:
properties:
memory-region:
maxItems: 1
mboxes:
minItems: 4
mbox-names:
items:
- const: txdb0
- const: txdb1
- const: rxdb0
- const: rxdb1
additionalProperties: false
examples:
@ -91,3 +164,41 @@ examples:
mboxes = <&lsio_mu13 2 0>, <&lsio_mu13 2 1>, <&lsio_mu13 3 0>, <&lsio_mu13 3 1>;
memory-region = <&dsp_reserved>;
};
- |
#include <dt-bindings/clock/imx8mp-clock.h>
dsp_reserved: dsp@92400000 {
reg = <0x92400000 0x1000000>;
no-map;
};
dsp_vdev0vring0: vdev0vring0@942f0000 {
reg = <0x942f0000 0x8000>;
no-map;
};
dsp_vdev0vring1: vdev0vring1@942f8000 {
reg = <0x942f8000 0x8000>;
no-map;
};
dsp_vdev0buffer: vdev0buffer@94300000 {
compatible = "shared-dma-pool";
reg = <0x94300000 0x100000>;
no-map;
};
dsp: dsp@3b6e8000 {
compatible = "fsl,imx8mp-hifi4";
reg = <0x3b6e8000 0x88000>;
clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_DSP_ROOT>,
<&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_OCRAMA_IPG>,
<&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_DSP_ROOT>,
<&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_DSPDBG_ROOT>;
clock-names = "ipg", "ocram", "core", "debug";
firmware-name = "imx/dsp/hifi4.bin";
power-domains = <&audiomix_pd>;
mbox-names = "tx", "rx", "rxdb";
mboxes = <&mu2 0 0>,
<&mu2 1 0>,
<&mu2 3 0>;
memory-region = <&dsp_vdev0buffer>, <&dsp_vdev0vring0>,
<&dsp_vdev0vring1>, <&dsp_reserved>;
fsl,dsp-ctrl = <&audio_blk_ctrl>;
};

6
sys/contrib/device-tree/Bindings/eeprom/at24.yaml
View File

@ -97,6 +97,12 @@ properties:
- items:
- const: nxp,se97b
- const: atmel,24c02
- items:
- const: onnn,cat24c04
- const: atmel,24c04
- items:
- const: onnn,cat24c05
- const: atmel,24c04
- items:
- const: renesas,r1ex24002
- const: atmel,24c02

14
sys/contrib/device-tree/Bindings/example-schema.yaml
View File

@ -119,7 +119,7 @@ properties:
# valid for this binding.
clock-frequency:
# The type is set in the core schema. Per device schema only need to set
# The type is set in the core schema. Per-device schema only need to set
# constraints on the possible values.
minimum: 100
maximum: 400000
@ -133,24 +133,24 @@ properties:
# *-supply is always a single phandle, so nothing more to define.
foo-supply: true
# Vendor specific properties
# Vendor-specific properties
#
# Vendor specific properties have slightly different schema requirements than
# Vendor-specific properties have slightly different schema requirements than
# common properties. They must have at least a type definition and
# 'description'.
vendor,int-property:
description: Vendor specific properties must have a description
description: Vendor-specific properties must have a description
$ref: /schemas/types.yaml#/definitions/uint32
enum: [2, 4, 6, 8, 10]
vendor,bool-property:
description: Vendor specific properties must have a description. Boolean
description: Vendor-specific properties must have a description. Boolean
properties are one case where the json-schema 'type' keyword can be used
directly.
type: boolean
vendor,string-array-property:
description: Vendor specific properties should reference a type in the
description: Vendor-specific properties should reference a type in the
core schema.
$ref: /schemas/types.yaml#/definitions/string-array
items:
@ -158,7 +158,7 @@ properties:
- enum: [baz, boo]
vendor,property-in-standard-units-microvolt:
description: Vendor specific properties having a standard unit suffix
description: Vendor-specific properties having a standard unit suffix
don't need a type.
enum: [ 100, 200, 300 ]

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