e1000: cleanup pre-processor tags
The codes has been exposed correctly, so remove pre-processor tags. Signed-off-by: Guinan Sun <guinanx.sun@intel.com> Reviewed-by: Wei Zhao <wei.zhao1@intel.com> Approved by: imp Obtained from: DPDK (a50e998a0fd94e5db508710868a3417b1846425c) MFC after: 1 week
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@ -34,6 +34,8 @@
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/*$FreeBSD$*/
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/*$FreeBSD$*/
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#include "e1000_api.h"
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#include "e1000_api.h"
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#include "e1000_manage.h"
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/**
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/**
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* e1000_calculate_checksum - Calculate checksum for buffer
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* e1000_calculate_checksum - Calculate checksum for buffer
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* @buffer: pointer to EEPROM
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* @buffer: pointer to EEPROM
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@ -455,6 +457,7 @@ s32 e1000_host_interface_command(struct e1000_hw *hw, u8 *buffer, u32 length)
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return E1000_SUCCESS;
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return E1000_SUCCESS;
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}
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}
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/**
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/**
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* e1000_load_firmware - Writes proxy FW code buffer to host interface
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* e1000_load_firmware - Writes proxy FW code buffer to host interface
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* and execute.
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* and execute.
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@ -573,5 +576,3 @@ s32 e1000_load_firmware(struct e1000_hw *hw, u8 *buffer, u32 length)
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return E1000_SUCCESS;
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return E1000_SUCCESS;
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}
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}
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@ -381,6 +381,7 @@
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#define E1000_TSCTC 0x040F8 /* TCP Segmentation Context Tx - R/clr */
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#define E1000_TSCTC 0x040F8 /* TCP Segmentation Context Tx - R/clr */
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#define E1000_TSCTFC 0x040FC /* TCP Segmentation Context Tx Fail - R/clr */
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#define E1000_TSCTFC 0x040FC /* TCP Segmentation Context Tx Fail - R/clr */
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#define E1000_IAC 0x04100 /* Interrupt Assertion Count */
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#define E1000_IAC 0x04100 /* Interrupt Assertion Count */
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/* Interrupt Cause */
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#define E1000_ICRXPTC 0x04104 /* Interrupt Cause Rx Pkt Timer Expire Count */
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#define E1000_ICRXPTC 0x04104 /* Interrupt Cause Rx Pkt Timer Expire Count */
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#define E1000_ICRXATC 0x04108 /* Interrupt Cause Rx Abs Timer Expire Count */
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#define E1000_ICRXATC 0x04108 /* Interrupt Cause Rx Abs Timer Expire Count */
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#define E1000_ICTXPTC 0x0410C /* Interrupt Cause Tx Pkt Timer Expire Count */
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#define E1000_ICTXPTC 0x0410C /* Interrupt Cause Tx Pkt Timer Expire Count */
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@ -503,12 +504,14 @@
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#define E1000_WUC 0x05800 /* Wakeup Control - RW */
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#define E1000_WUC 0x05800 /* Wakeup Control - RW */
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#define E1000_WUFC 0x05808 /* Wakeup Filter Control - RW */
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#define E1000_WUFC 0x05808 /* Wakeup Filter Control - RW */
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#define E1000_WUS 0x05810 /* Wakeup Status - RO */
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#define E1000_WUS 0x05810 /* Wakeup Status - RO */
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/* Management registers */
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#define E1000_MANC 0x05820 /* Management Control - RW */
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#define E1000_MANC 0x05820 /* Management Control - RW */
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#define E1000_IPAV 0x05838 /* IP Address Valid - RW */
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#define E1000_IPAV 0x05838 /* IP Address Valid - RW */
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#define E1000_IP4AT 0x05840 /* IPv4 Address Table - RW Array */
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#define E1000_IP4AT 0x05840 /* IPv4 Address Table - RW Array */
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#define E1000_IP6AT 0x05880 /* IPv6 Address Table - RW Array */
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#define E1000_IP6AT 0x05880 /* IPv6 Address Table - RW Array */
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#define E1000_WUPL 0x05900 /* Wakeup Packet Length - RW */
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#define E1000_WUPL 0x05900 /* Wakeup Packet Length - RW */
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#define E1000_WUPM 0x05A00 /* Wakeup Packet Memory - RO A */
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#define E1000_WUPM 0x05A00 /* Wakeup Packet Memory - RO A */
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/* MSI-X Table Register Descriptions */
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#define E1000_PBACL 0x05B68 /* MSIx PBA Clear - Read/Write 1's to clear */
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#define E1000_PBACL 0x05B68 /* MSIx PBA Clear - Read/Write 1's to clear */
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#define E1000_FFLT 0x05F00 /* Flexible Filter Length Table - RW Array */
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#define E1000_FFLT 0x05F00 /* Flexible Filter Length Table - RW Array */
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#define E1000_HOST_IF 0x08800 /* Host Interface */
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#define E1000_HOST_IF 0x08800 /* Host Interface */
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