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Got the sense of the L1 cache enabled test wrong; fixed.

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This commit is contained in:
Garrett Wollman 1996-01-23 20:36:49 +00:00
parent db4a5c0521
commit aacfda3486
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=13591
1 changed files with 2 additions and 2 deletions
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4
sys/pci/pcisupport.c
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@ -1,6 +1,6 @@
/**************************************************************************
**
** $Id: pcisupport.c,v 1.25 1996/01/22 22:43:48 wollman Exp $
** $Id: pcisupport.c,v 1.26 1996/01/23 20:21:24 wollman Exp $
**
** Device driver for DEC/INTEL PCI chipsets.
**
@ -403,7 +403,7 @@ static const struct condmsg conf82437fx[] =
{ 0x52, 0x30, 0x20, M_EQ, " asynchronous" },
{ 0x52, 0x30, 0x30, M_EQ, " dual-bank pipelined-burst" },
{ 0x00, 0x00, 0x00, M_TR, " secondary; L1 " },
{ 0x52, 0x01, 0x00, M_NN, 0 },
{ 0x52, 0x01, 0x00, M_EN, 0 },
{ 0x00, 0x00, 0x00, M_TR, "\n" },
/* DRAMC -- DRAM Control Register */