Add an ioctl to assert and deassert an ioapic pin atomically. This will be used
to inject edge triggered legacy interrupts into the guest. Start using the new API in device models that use edge triggered interrupts: viz. the 8254 timer and the LPC/uart device emulation. Submitted by: Tycho Nightingale (tycho.nightingale@pluribusnetworks.com)
This commit is contained in:
parent
9164a239ea
commit
ac7304a758
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=258494
@ -418,6 +418,17 @@ vm_ioapic_deassert_irq(struct vmctx *ctx, int irq)
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return (ioctl(ctx->fd, VM_IOAPIC_DEASSERT_IRQ, &ioapic_irq));
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}
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int
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vm_ioapic_pulse_irq(struct vmctx *ctx, int irq)
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{
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struct vm_ioapic_irq ioapic_irq;
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bzero(&ioapic_irq, sizeof(struct vm_ioapic_irq));
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ioapic_irq.irq = irq;
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return (ioctl(ctx->fd, VM_IOAPIC_PULSE_IRQ, &ioapic_irq));
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}
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int
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vm_inject_nmi(struct vmctx *ctx, int vcpu)
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{
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@ -69,6 +69,7 @@ int vm_inject_event2(struct vmctx *ctx, int vcpu, enum vm_event_type type,
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int vm_lapic_irq(struct vmctx *ctx, int vcpu, int vector);
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int vm_ioapic_assert_irq(struct vmctx *ctx, int irq);
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int vm_ioapic_deassert_irq(struct vmctx *ctx, int irq);
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int vm_ioapic_pulse_irq(struct vmctx *ctx, int irq);
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int vm_inject_nmi(struct vmctx *ctx, int vcpu);
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int vm_capability_name2type(const char *capname);
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const char *vm_capability_type2name(int type);
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@ -170,6 +170,7 @@ enum {
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IOCNUM_INJECT_NMI = 32,
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IOCNUM_IOAPIC_ASSERT_IRQ = 33,
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IOCNUM_IOAPIC_DEASSERT_IRQ = 34,
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IOCNUM_IOAPIC_PULSE_IRQ = 35,
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/* PCI pass-thru */
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IOCNUM_BIND_PPTDEV = 40,
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@ -209,6 +210,8 @@ enum {
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_IOW('v', IOCNUM_IOAPIC_ASSERT_IRQ, struct vm_ioapic_irq)
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#define VM_IOAPIC_DEASSERT_IRQ \
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_IOW('v', IOCNUM_IOAPIC_DEASSERT_IRQ, struct vm_ioapic_irq)
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#define VM_IOAPIC_PULSE_IRQ \
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_IOW('v', IOCNUM_IOAPIC_PULSE_IRQ, struct vm_ioapic_irq)
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#define VM_SET_CAPABILITY \
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_IOW('v', IOCNUM_SET_CAPABILITY, struct vm_capability)
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#define VM_GET_CAPABILITY \
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@ -160,8 +160,14 @@ vioapic_set_pinstate(struct vioapic *vioapic, int pin, bool newstate)
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}
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}
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enum irqstate {
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IRQSTATE_ASSERT,
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IRQSTATE_DEASSERT,
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IRQSTATE_PULSE
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};
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static int
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vioapic_set_irqstate(struct vm *vm, int irq, bool state)
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vioapic_set_irqstate(struct vm *vm, int irq, enum irqstate irqstate)
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{
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struct vioapic *vioapic;
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@ -171,7 +177,20 @@ vioapic_set_irqstate(struct vm *vm, int irq, bool state)
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vioapic = vm_ioapic(vm);
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VIOAPIC_LOCK(vioapic);
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vioapic_set_pinstate(vioapic, irq, state);
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switch (irqstate) {
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case IRQSTATE_ASSERT:
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vioapic_set_pinstate(vioapic, irq, true);
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break;
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case IRQSTATE_DEASSERT:
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vioapic_set_pinstate(vioapic, irq, false);
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break;
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case IRQSTATE_PULSE:
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vioapic_set_pinstate(vioapic, irq, true);
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vioapic_set_pinstate(vioapic, irq, false);
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break;
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default:
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panic("vioapic_set_irqstate: invalid irqstate %d", irqstate);
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}
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VIOAPIC_UNLOCK(vioapic);
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return (0);
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@ -181,14 +200,21 @@ int
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vioapic_assert_irq(struct vm *vm, int irq)
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{
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return (vioapic_set_irqstate(vm, irq, true));
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return (vioapic_set_irqstate(vm, irq, IRQSTATE_ASSERT));
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}
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int
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vioapic_deassert_irq(struct vm *vm, int irq)
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{
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return (vioapic_set_irqstate(vm, irq, false));
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return (vioapic_set_irqstate(vm, irq, IRQSTATE_DEASSERT));
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}
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int
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vioapic_pulse_irq(struct vm *vm, int irq)
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{
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return (vioapic_set_irqstate(vm, irq, IRQSTATE_PULSE));
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}
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static uint32_t
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@ -41,6 +41,7 @@ void vioapic_cleanup(struct vioapic *vioapic);
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int vioapic_assert_irq(struct vm *vm, int irq);
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int vioapic_deassert_irq(struct vm *vm, int irq);
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int vioapic_pulse_irq(struct vm *vm, int irq);
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int vioapic_mmio_write(void *vm, int vcpuid, uint64_t gpa,
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uint64_t wval, int size, void *arg);
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@ -303,6 +303,10 @@ vmmdev_ioctl(struct cdev *cdev, u_long cmd, caddr_t data, int fflag,
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ioapic_irq = (struct vm_ioapic_irq *)data;
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error = vioapic_deassert_irq(sc->vm, ioapic_irq->irq);
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break;
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case VM_IOAPIC_PULSE_IRQ:
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ioapic_irq = (struct vm_ioapic_irq *)data;
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error = vioapic_pulse_irq(sc->vm, ioapic_irq->irq);
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break;
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case VM_MAP_MEMORY:
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seg = (struct vm_memory_segment *)data;
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error = vm_malloc(sc->vm, seg->gpa, seg->len);
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@ -1135,7 +1135,11 @@ pci_lintr_assert(struct pci_devinst *pi)
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{
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assert(pi->pi_lintr_pin >= 0);
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vm_ioapic_assert_irq(pi->pi_vmctx, pi->pi_lintr_pin);
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if (pi->pi_lintr_state == 0) {
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pi->pi_lintr_state = 1;
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vm_ioapic_assert_irq(pi->pi_vmctx, pi->pi_lintr_pin);
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}
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}
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void
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@ -1143,7 +1147,11 @@ pci_lintr_deassert(struct pci_devinst *pi)
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{
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assert(pi->pi_lintr_pin >= 0);
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vm_ioapic_deassert_irq(pi->pi_vmctx, pi->pi_lintr_pin);
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if (pi->pi_lintr_state == 1) {
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pi->pi_lintr_state = 0;
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vm_ioapic_deassert_irq(pi->pi_vmctx, pi->pi_lintr_pin);
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}
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}
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/*
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@ -104,6 +104,7 @@ struct pci_devinst {
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struct vmctx *pi_vmctx;
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uint8_t pi_bus, pi_slot, pi_func;
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int8_t pi_lintr_pin;
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int8_t pi_lintr_state;
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char pi_name[PI_NAMESZ];
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int pi_bar_getsize;
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@ -94,17 +94,16 @@ lpc_uart_intr_assert(void *arg)
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assert(sc->irq >= 0);
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vm_ioapic_assert_irq(lpc_bridge->pi_vmctx, sc->irq);
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vm_ioapic_pulse_irq(lpc_bridge->pi_vmctx, sc->irq);
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}
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static void
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lpc_uart_intr_deassert(void *arg)
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{
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struct lpc_uart_softc *sc = arg;
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assert(sc->irq >= 0);
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vm_ioapic_deassert_irq(lpc_bridge->pi_vmctx, sc->irq);
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/*
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* The COM devices on the LPC bus generate edge triggered interrupts,
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* so nothing more to do here.
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*/
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}
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static int
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@ -105,8 +105,7 @@ pit_mevent_cb(int fd, enum ev_type type, void *param)
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pit_mev_count++;
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vm_ioapic_assert_irq(c->ctx, 2);
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vm_ioapic_deassert_irq(c->ctx, 2);
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vm_ioapic_pulse_irq(c->ctx, 2);
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/*
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* Delete the timer for one-shots
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