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riscv pmap: zero reserved pte bits in ppn

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The top 10 bits of a pte are reserved by specification[1] and are not part of
the PPN.

[1] 'Volume II: RISC-V Privileged Architectures V20190608-Priv-MSU-Ratified',
'4.4.1 Addressing and Memory Protection', page 72: "The PTE format for Sv39 is
shown in Figure 4.18. ... Bits 63–54 are reserved for future use and must be
zeroed by software for forward compatibility."

Submitted by:	Nathaniel Filardo <nwf20@cl.cam.ac.uk>
Reviewed by:	kp, mhorne
Differential Revision:	https://reviews.freebsd.org/D25523
This commit is contained in:
Kristof Provost 2020-07-01 19:15:43 +00:00
parent 6f11e59d72
commit b865714d95
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=362853
2 changed files with 5 additions and 1 deletions
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3
sys/riscv/include/pte.h
View File

@ -83,6 +83,9 @@ typedef uint64_t pn_t; /* page number */
#define PTE_PROMOTE (PTE_V | PTE_RWX | PTE_D | PTE_A | PTE_G | PTE_U | \
PTE_SW_MANAGED | PTE_SW_WIRED)
/* Bits 63 - 54 are reserved for future use. */
#define PTE_HI_MASK 0xFFC0000000000000ULL
#define PTE_PPN0_S 10
#define PTE_PPN1_S 19
#define PTE_PPN2_S 28

3
sys/riscv/riscv/pmap.c
View File

@ -339,7 +339,8 @@ pagezero(void *p)
#define pmap_l2_index(va) (((va) >> L2_SHIFT) & Ln_ADDR_MASK)
#define pmap_l3_index(va) (((va) >> L3_SHIFT) & Ln_ADDR_MASK)
#define PTE_TO_PHYS(pte) ((pte >> PTE_PPN0_S) * PAGE_SIZE)
#define PTE_TO_PHYS(pte) \
((((pte) & ~PTE_HI_MASK) >> PTE_PPN0_S) * PAGE_SIZE)
static __inline pd_entry_t *
pmap_l1(pmap_t pmap, vm_offset_t va)