Update the device tree source files to a Linux 4.7-RC.
MFC after: 2 weeks Sponsored by: ABT Systems Ltd
This commit is contained in:
Andrew Turner
commit
bc116e04c0
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=306083
71
sys/gnu/dts/arm/am335x-baltos-ir2110.dts
Normal file
71
sys/gnu/dts/arm/am335x-baltos-ir2110.dts
Normal file
@ -0,0 +1,71 @@
|
||||
/*
|
||||
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/*
|
||||
* VScom OnRISC
|
||||
* http://www.vscom.de
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "am335x-baltos.dtsi"
|
||||
|
||||
/ {
|
||||
model = "OnRISC Baltos iR 2110";
|
||||
};
|
||||
|
||||
&am33xx_pinmux {
|
||||
uart1_pins: pinmux_uart1_pins {
|
||||
pinctrl-single,pins = <
|
||||
AM33XX_IOPAD(0x980, PIN_INPUT | MUX_MODE0) /* uart1_rxd */
|
||||
AM33XX_IOPAD(0x984, PIN_INPUT | MUX_MODE0) /* uart1_txd */
|
||||
AM33XX_IOPAD(0x978, PIN_INPUT_PULLDOWN | MUX_MODE0) /* uart1_ctsn */
|
||||
AM33XX_IOPAD(0x97c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_rtsn */
|
||||
AM33XX_IOPAD(0x8e0, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* lcd_vsync.gpio2[22] DTR */
|
||||
AM33XX_IOPAD(0x8e4, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_hsync.gpio2[23] DSR */
|
||||
AM33XX_IOPAD(0x8e8, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_pclk.gpio2[24] DCD */
|
||||
AM33XX_IOPAD(0x8ec, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_ac_bias_en.gpio2[25] RI */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart1_pins>;
|
||||
dtr-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>;
|
||||
dsr-gpios = <&gpio2 23 GPIO_ACTIVE_LOW>;
|
||||
dcd-gpios = <&gpio2 24 GPIO_ACTIVE_LOW>;
|
||||
rng-gpios = <&gpio2 25 GPIO_ACTIVE_LOW>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb0_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb0 {
|
||||
status = "okay";
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
||||
&cpsw_emac0 {
|
||||
phy_id = <&davinci_mdio>, <1>;
|
||||
phy-mode = "rmii";
|
||||
dual_emac_res_vlan = <1>;
|
||||
};
|
||||
|
||||
&cpsw_emac1 {
|
||||
phy_id = <&davinci_mdio>, <7>;
|
||||
phy-mode = "rgmii-txid";
|
||||
dual_emac_res_vlan = <2>;
|
||||
};
|
||||
|
||||
&phy_sel {
|
||||
rmii-clock-ext = <1>;
|
||||
};
|
||||
119
sys/gnu/dts/arm/am335x-baltos-ir3220.dts
Normal file
119
sys/gnu/dts/arm/am335x-baltos-ir3220.dts
Normal file
@ -0,0 +1,119 @@
|
||||
/*
|
||||
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/*
|
||||
* VScom OnRISC
|
||||
* http://www.vscom.de
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "am335x-baltos.dtsi"
|
||||
|
||||
/ {
|
||||
model = "OnRISC Baltos iR 3220";
|
||||
};
|
||||
|
||||
&am33xx_pinmux {
|
||||
tca6416_pins: pinmux_tca6416_pins {
|
||||
pinctrl-single,pins = <
|
||||
AM33XX_IOPAD(0x9b4, PIN_INPUT_PULLUP | MUX_MODE7) /* xdma_event_intr1.gpio0[20] tca6416 stuff */
|
||||
>;
|
||||
};
|
||||
|
||||
uart1_pins: pinmux_uart1_pins {
|
||||
pinctrl-single,pins = <
|
||||
AM33XX_IOPAD(0x980, PIN_INPUT | MUX_MODE0) /* uart1_rxd */
|
||||
AM33XX_IOPAD(0x984, PIN_INPUT | MUX_MODE0) /* uart1_txd */
|
||||
AM33XX_IOPAD(0x978, PIN_INPUT_PULLDOWN | MUX_MODE0) /* uart1_ctsn */
|
||||
AM33XX_IOPAD(0x97c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_rtsn */
|
||||
AM33XX_IOPAD(0x8e0, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* lcd_vsync.gpio2[22] DTR */
|
||||
AM33XX_IOPAD(0x8e4, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_hsync.gpio2[23] DSR */
|
||||
AM33XX_IOPAD(0x8e8, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_pclk.gpio2[24] DCD */
|
||||
AM33XX_IOPAD(0x8ec, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_ac_bias_en.gpio2[25] RI */
|
||||
>;
|
||||
};
|
||||
|
||||
uart2_pins: pinmux_uart2_pins {
|
||||
pinctrl-single,pins = <
|
||||
AM33XX_IOPAD(0x950, PIN_INPUT | MUX_MODE1) /* spi0_sclk.uart2_rxd_mux3 */
|
||||
AM33XX_IOPAD(0x954, PIN_OUTPUT | MUX_MODE1) /* spi0_d0.uart2_txd_mux3 */
|
||||
AM33XX_IOPAD(0x988, PIN_INPUT_PULLDOWN | MUX_MODE2) /* i2c0_sda.uart2_ctsn_mux0 */
|
||||
AM33XX_IOPAD(0x98c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* i2c0_scl.uart2_rtsn_mux0 */
|
||||
AM33XX_IOPAD(0x830, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad12.gpio1[12] DTR */
|
||||
AM33XX_IOPAD(0x834, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad13.gpio1[13] DSR */
|
||||
AM33XX_IOPAD(0x838, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad14.gpio1[14] DCD */
|
||||
AM33XX_IOPAD(0x83c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad15.gpio1[15] RI */
|
||||
|
||||
AM33XX_IOPAD(0x9a0, PIN_INPUT_PULLUP | MUX_MODE7) /* mcasp0_aclkr.gpio3[18], INPUT_PULLDOWN | MODE7 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart1_pins>;
|
||||
dtr-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>;
|
||||
dsr-gpios = <&gpio2 23 GPIO_ACTIVE_LOW>;
|
||||
dcd-gpios = <&gpio2 24 GPIO_ACTIVE_LOW>;
|
||||
rng-gpios = <&gpio2 25 GPIO_ACTIVE_LOW>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart2_pins>;
|
||||
dtr-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
|
||||
dsr-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
|
||||
dcd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
|
||||
rng-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
tca6416: gpio@20 {
|
||||
compatible = "ti,tca6416";
|
||||
reg = <0x20>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <20 GPIO_ACTIVE_LOW>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&tca6416_pins>;
|
||||
};
|
||||
};
|
||||
|
||||
&usb0_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb0 {
|
||||
status = "okay";
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
||||
&cpsw_emac0 {
|
||||
phy-mode = "rmii";
|
||||
dual_emac_res_vlan = <1>;
|
||||
fixed-link {
|
||||
speed = <100>;
|
||||
full-duplex;
|
||||
};
|
||||
};
|
||||
|
||||
&cpsw_emac1 {
|
||||
phy_id = <&davinci_mdio>, <7>;
|
||||
phy-mode = "rgmii-txid";
|
||||
dual_emac_res_vlan = <2>;
|
||||
};
|
||||
|
||||
&phy_sel {
|
||||
rmii-clock-ext = <1>;
|
||||
};
|
||||
408
sys/gnu/dts/arm/am335x-baltos.dtsi
Normal file
408
sys/gnu/dts/arm/am335x-baltos.dtsi
Normal file
@ -0,0 +1,408 @@
|
||||
/*
|
||||
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/*
|
||||
* VScom OnRISC
|
||||
* http://www.vscom.de
|
||||
*/
|
||||
|
||||
#include "am33xx.dtsi"
|
||||
#include <dt-bindings/pwm/pwm.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
/ {
|
||||
compatible = "vscom,onrisc", "ti,am33xx";
|
||||
|
||||
cpus {
|
||||
cpu@0 {
|
||||
cpu0-supply = <&vdd1_reg>;
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x80000000 0x10000000>; /* 256 MB */
|
||||
};
|
||||
|
||||
vbat: fixedregulator@0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vbat";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
wl12xx_vmmc: fixedregulator@2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&wl12xx_gpio>;
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vwl1271";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
gpio = <&gpio3 8 0>;
|
||||
startup-delay-us = <70000>;
|
||||
enable-active-high;
|
||||
};
|
||||
};
|
||||
|
||||
&am33xx_pinmux {
|
||||
mmc2_pins: pinmux_mmc2_pins {
|
||||
pinctrl-single,pins = <
|
||||
AM33XX_IOPAD(0x820, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad8.mmc1_dat0_mux0 */
|
||||
AM33XX_IOPAD(0x824, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad9.mmc1_dat1_mux0 */
|
||||
AM33XX_IOPAD(0x828, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad10.mmc1_dat2_mux0 */
|
||||
AM33XX_IOPAD(0x82c, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad11.mmc1_dat3_mux0 */
|
||||
AM33XX_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk_mux0 */
|
||||
AM33XX_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd_mux0 */
|
||||
AM33XX_IOPAD(0x9e4, PIN_INPUT_PULLUP | MUX_MODE7) /* emu0.gpio3[7] */
|
||||
>;
|
||||
};
|
||||
|
||||
wl12xx_gpio: pinmux_wl12xx_gpio {
|
||||
pinctrl-single,pins = <
|
||||
AM33XX_IOPAD(0x9e8, PIN_OUTPUT_PULLUP | MUX_MODE7) /* emu1.gpio3[8] */
|
||||
>;
|
||||
};
|
||||
|
||||
tps65910_pins: pinmux_tps65910_pins {
|
||||
pinctrl-single,pins = <
|
||||
AM33XX_IOPAD(0x878, PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_ben1.gpio1[28] */
|
||||
>;
|
||||
};
|
||||
|
||||
i2c1_pins: pinmux_i2c1_pins {
|
||||
pinctrl-single,pins = <
|
||||
AM33XX_IOPAD(0x958, PIN_INPUT | MUX_MODE2) /* spi0_d1.i2c1_sda_mux3 */
|
||||
AM33XX_IOPAD(0x95c, PIN_INPUT | MUX_MODE2) /* spi0_cs0.i2c1_scl_mux3 */
|
||||
>;
|
||||
};
|
||||
|
||||
uart0_pins: pinmux_uart0_pins {
|
||||
pinctrl-single,pins = <
|
||||
AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
|
||||
AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
|
||||
>;
|
||||
};
|
||||
|
||||
cpsw_default: cpsw_default {
|
||||
pinctrl-single,pins = <
|
||||
/* Slave 1 */
|
||||
AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs_dv */
|
||||
AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_tx_en.rmii1_txen */
|
||||
AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */
|
||||
AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */
|
||||
AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */
|
||||
AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */
|
||||
AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_ref_clk.rmii1_refclk */
|
||||
|
||||
|
||||
/* Slave 2 */
|
||||
AM33XX_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a0.rgmii2_tctl */
|
||||
AM33XX_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a1.rgmii2_rctl */
|
||||
AM33XX_IOPAD(0x848, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a2.rgmii2_td3 */
|
||||
AM33XX_IOPAD(0x84c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a3.rgmii2_td2 */
|
||||
AM33XX_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a4.rgmii2_td1 */
|
||||
AM33XX_IOPAD(0x854, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a5.rgmii2_td0 */
|
||||
AM33XX_IOPAD(0x858, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a6.rgmii2_tclk */
|
||||
AM33XX_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a7.rgmii2_rclk */
|
||||
AM33XX_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */
|
||||
AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */
|
||||
AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */
|
||||
AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */
|
||||
>;
|
||||
};
|
||||
|
||||
cpsw_sleep: cpsw_sleep {
|
||||
pinctrl-single,pins = <
|
||||
/* Slave 1 reset value */
|
||||
AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
|
||||
/* Slave 2 reset value*/
|
||||
AM33XX_IOPAD(0x840, PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
AM33XX_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
AM33XX_IOPAD(0x848, PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
AM33XX_IOPAD(0x84c, PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
AM33XX_IOPAD(0x850, PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
AM33XX_IOPAD(0x854, PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
AM33XX_IOPAD(0x858, PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
AM33XX_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
AM33XX_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
>;
|
||||
};
|
||||
|
||||
davinci_mdio_default: davinci_mdio_default {
|
||||
pinctrl-single,pins = <
|
||||
/* MDIO */
|
||||
AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
|
||||
AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
|
||||
>;
|
||||
};
|
||||
|
||||
davinci_mdio_sleep: davinci_mdio_sleep {
|
||||
pinctrl-single,pins = <
|
||||
/* MDIO reset value */
|
||||
AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
>;
|
||||
};
|
||||
|
||||
nandflash_pins_s0: nandflash_pins_s0 {
|
||||
pinctrl-single,pins = <
|
||||
AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
|
||||
AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
|
||||
AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
|
||||
AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
|
||||
AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
|
||||
AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
|
||||
AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
|
||||
AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
|
||||
AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
|
||||
AM33XX_IOPAD(0x874, PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_30 */
|
||||
AM33XX_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
|
||||
AM33XX_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
|
||||
AM33XX_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
|
||||
AM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
|
||||
AM33XX_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&elm {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpmc {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&nandflash_pins_s0>;
|
||||
ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */
|
||||
status = "okay";
|
||||
|
||||
nand@0,0 {
|
||||
compatible = "ti,omap2-nand";
|
||||
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
|
||||
interrupt-parent = <&gpmc>;
|
||||
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
|
||||
<1 IRQ_TYPE_NONE>; /* termcount */
|
||||
rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
|
||||
nand-bus-width = <8>;
|
||||
ti,nand-ecc-opt = "bch8";
|
||||
ti,nand-xfer-type = "polled";
|
||||
|
||||
gpmc,device-nand = "true";
|
||||
gpmc,device-width = <1>;
|
||||
gpmc,sync-clk-ps = <0>;
|
||||
gpmc,cs-on-ns = <0>;
|
||||
gpmc,cs-rd-off-ns = <44>;
|
||||
gpmc,cs-wr-off-ns = <44>;
|
||||
gpmc,adv-on-ns = <6>;
|
||||
gpmc,adv-rd-off-ns = <34>;
|
||||
gpmc,adv-wr-off-ns = <44>;
|
||||
gpmc,we-on-ns = <0>;
|
||||
gpmc,we-off-ns = <40>;
|
||||
gpmc,oe-on-ns = <0>;
|
||||
gpmc,oe-off-ns = <54>;
|
||||
gpmc,access-ns = <64>;
|
||||
gpmc,rd-cycle-ns = <82>;
|
||||
gpmc,wr-cycle-ns = <82>;
|
||||
gpmc,bus-turnaround-ns = <0>;
|
||||
gpmc,cycle2cycle-delay-ns = <0>;
|
||||
gpmc,clk-activation-ns = <0>;
|
||||
gpmc,wr-access-ns = <40>;
|
||||
gpmc,wr-data-mux-bus-ns = <0>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
elm_id = <&elm>;
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart0_pins>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c1_pins>;
|
||||
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
tps: tps@2d {
|
||||
reg = <0x2d>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <28 GPIO_ACTIVE_LOW>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&tps65910_pins>;
|
||||
};
|
||||
|
||||
at24@50 {
|
||||
compatible = "at24,24c02";
|
||||
pagesize = <8>;
|
||||
reg = <0x50>;
|
||||
};
|
||||
};
|
||||
|
||||
&usb {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_ctrl_mod {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cppi41dma {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
#include "tps65910.dtsi"
|
||||
|
||||
&tps {
|
||||
vcc1-supply = <&vbat>;
|
||||
vcc2-supply = <&vbat>;
|
||||
vcc3-supply = <&vbat>;
|
||||
vcc4-supply = <&vbat>;
|
||||
vcc5-supply = <&vbat>;
|
||||
vcc6-supply = <&vbat>;
|
||||
vcc7-supply = <&vbat>;
|
||||
vccio-supply = <&vbat>;
|
||||
|
||||
ti,en-ck32k-xtal = <1>;
|
||||
|
||||
regulators {
|
||||
vrtc_reg: regulator@0 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vio_reg: regulator@1 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vdd1_reg: regulator@2 {
|
||||
/* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
|
||||
regulator-name = "vdd_mpu";
|
||||
regulator-min-microvolt = <912500>;
|
||||
regulator-max-microvolt = <1312500>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vdd2_reg: regulator@3 {
|
||||
/* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
|
||||
regulator-name = "vdd_core";
|
||||
regulator-min-microvolt = <912500>;
|
||||
regulator-max-microvolt = <1150000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vdd3_reg: regulator@4 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vdig1_reg: regulator@5 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vdig2_reg: regulator@6 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vpll_reg: regulator@7 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vdac_reg: regulator@8 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vaux1_reg: regulator@9 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vaux2_reg: regulator@10 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vaux33_reg: regulator@11 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vmmc_reg: regulator@12 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&mac {
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&cpsw_default>;
|
||||
pinctrl-1 = <&cpsw_sleep>;
|
||||
dual_emac = <1>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&davinci_mdio {
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&davinci_mdio_default>;
|
||||
pinctrl-1 = <&davinci_mdio_sleep>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mmc1 {
|
||||
vmmc-supply = <&vmmc_reg>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mmc2 {
|
||||
status = "okay";
|
||||
vmmc-supply = <&wl12xx_vmmc>;
|
||||
ti,non-removable;
|
||||
bus-width = <4>;
|
||||
cap-power-off-card;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mmc2_pins>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
wlcore: wlcore@2 {
|
||||
compatible = "ti,wl1835";
|
||||
reg = <2>;
|
||||
interrupt-parent = <&gpio3>;
|
||||
interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
&sham {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&aes {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpio0 {
|
||||
ti,no-reset-on-init;
|
||||
};
|
||||
306
sys/gnu/dts/arm/am335x-icev2.dts
Normal file
306
sys/gnu/dts/arm/am335x-icev2.dts
Normal file
@ -0,0 +1,306 @@
|
||||
/*
|
||||
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/*
|
||||
* AM335x ICE V2 board
|
||||
* http://www.ti.com/tool/tmdsice3359
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "am33xx.dtsi"
|
||||
|
||||
/ {
|
||||
model = "TI AM3359 ICE-V2";
|
||||
compatible = "ti,am3359-icev2", "ti,am33xx";
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x80000000 0x10000000>; /* 256 MB */
|
||||
};
|
||||
|
||||
vbat: fixedregulator@0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vbat";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vtt_fixed: fixedregulator@1 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vtt";
|
||||
regulator-min-microvolt = <1500000>;
|
||||
regulator-max-microvolt = <1500000>;
|
||||
gpio = <&gpio0 18 GPIO_ACTIVE_HIGH>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
leds@0 {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
led@0 {
|
||||
label = "out0";
|
||||
gpios = <&tpic2810 0 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
led@1 {
|
||||
label = "out1";
|
||||
gpios = <&tpic2810 1 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
led@2 {
|
||||
label = "out2";
|
||||
gpios = <&tpic2810 2 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
led@3 {
|
||||
label = "out3";
|
||||
gpios = <&tpic2810 3 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
led@4 {
|
||||
label = "out4";
|
||||
gpios = <&tpic2810 4 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
led@5 {
|
||||
label = "out5";
|
||||
gpios = <&tpic2810 5 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
led@6 {
|
||||
label = "out6";
|
||||
gpios = <&tpic2810 6 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
led@7 {
|
||||
label = "out7";
|
||||
gpios = <&tpic2810 7 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
};
|
||||
};
|
||||
|
||||
/* Tricolor status LEDs */
|
||||
leds@1 {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&user_leds>;
|
||||
|
||||
led@0 {
|
||||
label = "status0:red:cpu0";
|
||||
gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
linux,default-trigger = "cpu0";
|
||||
};
|
||||
|
||||
led@1 {
|
||||
label = "status0:green:usr";
|
||||
gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
led@2 {
|
||||
label = "status0:yellow:usr";
|
||||
gpios = <&gpio3 9 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
led@3 {
|
||||
label = "status1:red:mmc0";
|
||||
gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
linux,default-trigger = "mmc0";
|
||||
};
|
||||
|
||||
led@4 {
|
||||
label = "status1:green:usr";
|
||||
gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
led@5 {
|
||||
label = "status1:yellow:usr";
|
||||
gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&am33xx_pinmux {
|
||||
user_leds: user_leds {
|
||||
pinctrl-single,pins = <
|
||||
AM33XX_IOPAD(0x91c, PIN_OUTPUT | MUX_MODE7) /* (J18) gmii1_txd3.gpio0[16] */
|
||||
AM33XX_IOPAD(0x920, PIN_OUTPUT | MUX_MODE7) /* (K15) gmii1_txd2.gpio0[17] */
|
||||
AM33XX_IOPAD(0x9b0, PIN_OUTPUT | MUX_MODE7) /* (A15) xdma_event_intr0.gpio0[19] */
|
||||
AM33XX_IOPAD(0x9b4, PIN_OUTPUT | MUX_MODE7) /* (D14) xdma_event_intr1.gpio0[20] */
|
||||
AM33XX_IOPAD(0x880, PIN_OUTPUT | MUX_MODE7) /* (U9) gpmc_csn1.gpio1[30] */
|
||||
AM33XX_IOPAD(0x92c, PIN_OUTPUT | MUX_MODE7) /* (K18) gmii1_txclk.gpio3[9] */
|
||||
>;
|
||||
};
|
||||
|
||||
mmc0_pins_default: mmc0_pins_default {
|
||||
pinctrl-single,pins = <
|
||||
AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0) /* (F17) mmc0_dat3.mmc0_dat3 */
|
||||
AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0) /* (F18) mmc0_dat2.mmc0_dat2 */
|
||||
AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0) /* (G15) mmc0_dat1.mmc0_dat1 */
|
||||
AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0) /* (G16) mmc0_dat0.mmc0_dat0 */
|
||||
AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) /* (G17) mmc0_clk.mmc0_clk */
|
||||
AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) /* (G18) mmc0_cmd.mmc0_cmd */
|
||||
AM33XX_IOPAD(0x960, PIN_INPUT_PULLUP | MUX_MODE5) /* (C15) spi0_cs1.mmc0_sdcd */
|
||||
>;
|
||||
};
|
||||
|
||||
i2c0_pins_default: i2c0_pins_default {
|
||||
pinctrl-single,pins = <
|
||||
AM33XX_IOPAD(0x988, PIN_INPUT | MUX_MODE0) /* (C17) I2C0_SDA.I2C0_SDA */
|
||||
AM33XX_IOPAD(0x98c, PIN_INPUT | MUX_MODE0) /* (C16) I2C0_SCL.I2C0_SCL */
|
||||
>;
|
||||
};
|
||||
|
||||
spi0_pins_default: spi0_pins_default {
|
||||
pinctrl-single,pins = <
|
||||
AM33XX_IOPAD(0x950, PIN_INPUT_PULLUP | MUX_MODE0) /* (A17) spi0_sclk.spi0_sclk */
|
||||
AM33XX_IOPAD(0x954, PIN_INPUT_PULLUP | MUX_MODE0) /* (B17) spi0_d0.spi0_d0 */
|
||||
AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE0) /* (B16) spi0_d1.spi0_d1 */
|
||||
AM33XX_IOPAD(0x95c, PIN_INPUT_PULLUP | MUX_MODE0) /* (A16) spi0_cs0.spi0_cs0 */
|
||||
>;
|
||||
};
|
||||
|
||||
uart3_pins_default: uart3_pins_default {
|
||||
pinctrl-single,pins = <
|
||||
AM33XX_IOPAD(0x934, PIN_INPUT_PULLUP | MUX_MODE1) /* (L17) gmii1_rxd3.uart3_rxd */
|
||||
AM33XX_IOPAD(0x938, PIN_OUTPUT_PULLUP | MUX_MODE1) /* (L16) gmii1_rxd2.uart3_txd */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c0_pins_default>;
|
||||
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
tps: power-controller@2d {
|
||||
reg = <0x2d>;
|
||||
};
|
||||
|
||||
tpic2810: gpio@60 {
|
||||
compatible = "ti,tpic2810";
|
||||
reg = <0x60>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
#include "tps65910.dtsi"
|
||||
|
||||
&tps {
|
||||
vcc1-supply = <&vbat>;
|
||||
vcc2-supply = <&vbat>;
|
||||
vcc3-supply = <&vbat>;
|
||||
vcc4-supply = <&vbat>;
|
||||
vcc5-supply = <&vbat>;
|
||||
vcc6-supply = <&vbat>;
|
||||
vcc7-supply = <&vbat>;
|
||||
vccio-supply = <&vbat>;
|
||||
|
||||
regulators {
|
||||
vrtc_reg: regulator@0 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vio_reg: regulator@1 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vdd1_reg: regulator@2 {
|
||||
regulator-name = "vdd_mpu";
|
||||
regulator-min-microvolt = <912500>;
|
||||
regulator-max-microvolt = <1326000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vdd2_reg: regulator@3 {
|
||||
regulator-name = "vdd_core";
|
||||
regulator-min-microvolt = <912500>;
|
||||
regulator-max-microvolt = <1144000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vdd3_reg: regulator@4 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vdig1_reg: regulator@5 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vdig2_reg: regulator@6 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vpll_reg: regulator@7 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vdac_reg: regulator@8 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vaux1_reg: regulator@9 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vaux2_reg: regulator@10 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vaux33_reg: regulator@11 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vmmc_reg: regulator@12 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&mmc1 {
|
||||
status = "okay";
|
||||
vmmc-supply = <&vmmc_reg>;
|
||||
bus-width = <4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mmc0_pins_default>;
|
||||
};
|
||||
|
||||
&gpio0 {
|
||||
/* Do not idle the GPIO used for holding the VTT regulator */
|
||||
ti,no-reset-on-init;
|
||||
ti,no-idle-on-init;
|
||||
};
|
||||
|
||||
&uart3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart3_pins_default>;
|
||||
status = "okay";
|
||||
};
|
||||
85
sys/gnu/dts/arm/am572x-idk.dts
Normal file
85
sys/gnu/dts/arm/am572x-idk.dts
Normal file
@ -0,0 +1,85 @@
|
||||
/*
|
||||
* Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "dra74x.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include "am57xx-idk-common.dtsi"
|
||||
|
||||
/ {
|
||||
model = "TI AM5728 IDK";
|
||||
compatible = "ti,am5728-idk", "ti,am5728", "ti,dra742", "ti,dra74",
|
||||
"ti,dra7";
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x80000000 0x0 0x80000000>;
|
||||
};
|
||||
|
||||
extcon_usb2: extcon_usb2 {
|
||||
compatible = "linux,extcon-usb-gpio";
|
||||
id-gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
status-leds {
|
||||
compatible = "gpio-leds";
|
||||
cpu0-led {
|
||||
label = "status0:red:cpu0";
|
||||
gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
linux,default-trigger = "cpu0";
|
||||
};
|
||||
|
||||
usr0-led {
|
||||
label = "status0:green:usr";
|
||||
gpios = <&gpio3 11 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
heartbeat-led {
|
||||
label = "status0:blue:heartbeat";
|
||||
gpios = <&gpio3 12 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
|
||||
cpu1-led {
|
||||
label = "status1:red:cpu1";
|
||||
gpios = <&gpio3 10 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
linux,default-trigger = "cpu1";
|
||||
};
|
||||
|
||||
usr1-led {
|
||||
label = "status1:green:usr";
|
||||
gpios = <&gpio7 23 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
mmc0-led {
|
||||
label = "status1:blue:mmc0";
|
||||
gpios = <&gpio7 22 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
linux,default-trigger = "mmc0";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&omap_dwc3_2 {
|
||||
extcon = <&extcon_usb2>;
|
||||
};
|
||||
|
||||
&mmc1 {
|
||||
status = "okay";
|
||||
vmmc-supply = <&v3_3d>;
|
||||
vmmc_aux-supply = <&ldo1_reg>;
|
||||
bus-width = <4>;
|
||||
cd-gpios = <&gpio6 27 0>; /* gpio 219 */
|
||||
};
|
||||
23
sys/gnu/dts/arm/am57xx-commercial-grade.dtsi
Normal file
23
sys/gnu/dts/arm/am57xx-commercial-grade.dtsi
Normal file
@ -0,0 +1,23 @@
|
||||
&cpu_alert0 {
|
||||
temperature = <80000>; /* milliCelsius */
|
||||
};
|
||||
|
||||
&cpu_crit {
|
||||
temperature = <90000>; /* milliCelsius */
|
||||
};
|
||||
|
||||
&gpu_crit {
|
||||
temperature = <90000>; /* milliCelsius */
|
||||
};
|
||||
|
||||
&core_crit {
|
||||
temperature = <90000>; /* milliCelsius */
|
||||
};
|
||||
|
||||
&dspeve_crit {
|
||||
temperature = <90000>; /* milliCelsius */
|
||||
};
|
||||
|
||||
&iva_crit {
|
||||
temperature = <90000>; /* milliCelsius */
|
||||
};
|
||||
306
sys/gnu/dts/arm/am57xx-idk-common.dtsi
Normal file
306
sys/gnu/dts/arm/am57xx-idk-common.dtsi
Normal file
@ -0,0 +1,306 @@
|
||||
/*
|
||||
* Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include "am57xx-industrial-grade.dtsi"
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
rtc0 = &tps659038_rtc;
|
||||
rtc1 = &rtc;
|
||||
};
|
||||
|
||||
vmain: fixedregulator-vmain {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "VMAIN";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
v3_3d: fixedregulator-v3_3d {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "V3_3D";
|
||||
vin-supply = <&smps9_reg>;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vtt_fixed: fixedregulator-vtt {
|
||||
/* TPS51200 */
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vtt_fixed";
|
||||
vin-supply = <&v3_3d>;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
tps659038: tps659038@58 {
|
||||
compatible = "ti,tps659038";
|
||||
reg = <0x58>;
|
||||
interrupts-extended = <&gpio6 16 IRQ_TYPE_LEVEL_HIGH
|
||||
&dra7_pmx_core 0x418>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
ti,system-power-controller;
|
||||
|
||||
tps659038_pmic {
|
||||
compatible = "ti,tps659038-pmic";
|
||||
|
||||
smps12-in-supply = <&vmain>;
|
||||
smps3-in-supply = <&vmain>;
|
||||
smps45-in-supply = <&vmain>;
|
||||
smps6-in-supply = <&vmain>;
|
||||
smps7-in-supply = <&vmain>;
|
||||
smps8-in-supply = <&vmain>;
|
||||
smps9-in-supply = <&vmain>;
|
||||
ldo1-in-supply = <&vmain>;
|
||||
ldo2-in-supply = <&vmain>;
|
||||
ldo3-in-supply = <&vmain>;
|
||||
ldo4-in-supply = <&vmain>;
|
||||
ldo9-in-supply = <&vmain>;
|
||||
ldoln-in-supply = <&vmain>;
|
||||
ldousb-in-supply = <&vmain>;
|
||||
ldortc-in-supply = <&vmain>;
|
||||
|
||||
regulators {
|
||||
smps12_reg: smps12 {
|
||||
/* VDD_MPU */
|
||||
regulator-name = "smps12";
|
||||
regulator-min-microvolt = <850000>;
|
||||
regulator-max-microvolt = <1250000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
smps3_reg: smps3 {
|
||||
/* VDD_DDR EMIF1 EMIF2 */
|
||||
regulator-name = "smps3";
|
||||
regulator-min-microvolt = <1350000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
smps45_reg: smps45 {
|
||||
/* VDD_DSPEVE on AM572 */
|
||||
/* VDD_IVA + VDD_DSP on AM571 */
|
||||
regulator-name = "smps45";
|
||||
regulator-min-microvolt = <850000>;
|
||||
regulator-max-microvolt = <1250000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
smps6_reg: smps6 {
|
||||
/* VDD_GPU */
|
||||
regulator-name = "smps6";
|
||||
regulator-min-microvolt = <850000>;
|
||||
regulator-max-microvolt = <1250000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
smps7_reg: smps7 {
|
||||
/* VDD_CORE */
|
||||
regulator-name = "smps7";
|
||||
regulator-min-microvolt = <850000>;
|
||||
regulator-max-microvolt = <1150000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
smps8_reg: smps8 {
|
||||
/* 5728 - VDD_IVAHD */
|
||||
/* 5718 - N.C. test point */
|
||||
regulator-name = "smps8";
|
||||
};
|
||||
|
||||
smps9_reg: smps9 {
|
||||
/* VDD_3_3D */
|
||||
regulator-name = "smps9";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
ldo1_reg: ldo1 {
|
||||
/* VDDSHV8 - VSDMMC */
|
||||
/* NOTE: on rev 1.3a, data supply */
|
||||
regulator-name = "ldo1";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo2_reg: ldo2 {
|
||||
/* VDDSH18V */
|
||||
regulator-name = "ldo2";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
ldo3_reg: ldo3 {
|
||||
/* R1.3a 572x V1_8PHY_LDO3: USB, SATA */
|
||||
regulator-name = "ldo3";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
ldo4_reg: ldo4 {
|
||||
/* R1.3a 572x V1_8PHY_LDO4: PCIE, HDMI*/
|
||||
regulator-name = "ldo4";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
/* LDO5-8 unused */
|
||||
|
||||
ldo9_reg: ldo9 {
|
||||
/* VDD_RTC */
|
||||
regulator-name = "ldo9";
|
||||
regulator-min-microvolt = <840000>;
|
||||
regulator-max-microvolt = <1160000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
ldoln_reg: ldoln {
|
||||
/* VDDA_1V8_PLL */
|
||||
regulator-name = "ldoln";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
ldousb_reg: ldousb {
|
||||
/* VDDA_3V_USB: VDDA_USBHS33 */
|
||||
regulator-name = "ldousb";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
ldortc_reg: ldortc {
|
||||
/* VDDA_RTC */
|
||||
regulator-name = "ldortc";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
regen1: regen1 {
|
||||
/* VDD_3V3_ON */
|
||||
regulator-name = "regen1";
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
regen2: regen2 {
|
||||
/* Needed for PMIC internal resource */
|
||||
regulator-name = "regen2";
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
tps659038_rtc: tps659038_rtc {
|
||||
compatible = "ti,palmas-rtc";
|
||||
interrupt-parent = <&tps659038>;
|
||||
interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
|
||||
wakeup-source;
|
||||
};
|
||||
|
||||
tps659038_pwr_button: tps659038_pwr_button {
|
||||
compatible = "ti,palmas-pwrbutton";
|
||||
interrupt-parent = <&tps659038>;
|
||||
interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
|
||||
wakeup-source;
|
||||
ti,palmas-long-press-seconds = <12>;
|
||||
};
|
||||
|
||||
tps659038_gpio: tps659038_gpio {
|
||||
compatible = "ti,palmas-gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&uart3 {
|
||||
status = "okay";
|
||||
interrupts-extended = <&crossbar_mpu GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH
|
||||
&dra7_pmx_core 0x248>;
|
||||
};
|
||||
|
||||
&rtc {
|
||||
status = "okay";
|
||||
ext-clk-src;
|
||||
};
|
||||
|
||||
&mac {
|
||||
status = "okay";
|
||||
dual_emac;
|
||||
};
|
||||
|
||||
&cpsw_emac0 {
|
||||
phy_id = <&davinci_mdio>, <0>;
|
||||
phy-mode = "rgmii";
|
||||
dual_emac_res_vlan = <1>;
|
||||
};
|
||||
|
||||
&cpsw_emac1 {
|
||||
phy_id = <&davinci_mdio>, <1>;
|
||||
phy-mode = "rgmii";
|
||||
dual_emac_res_vlan = <2>;
|
||||
};
|
||||
|
||||
&usb2_phy1 {
|
||||
phy-supply = <&ldousb_reg>;
|
||||
};
|
||||
|
||||
&usb2_phy2 {
|
||||
phy-supply = <&ldousb_reg>;
|
||||
};
|
||||
|
||||
&usb1 {
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
||||
&usb2 {
|
||||
dr_mode = "otg";
|
||||
};
|
||||
|
||||
&mmc2 {
|
||||
status = "okay";
|
||||
vmmc-supply = <&v3_3d>;
|
||||
bus-width = <8>;
|
||||
ti,non-removable;
|
||||
max-frequency = <96000000>;
|
||||
};
|
||||
23
sys/gnu/dts/arm/am57xx-industrial-grade.dtsi
Normal file
23
sys/gnu/dts/arm/am57xx-industrial-grade.dtsi
Normal file
@ -0,0 +1,23 @@
|
||||
&cpu_alert0 {
|
||||
temperature = <90000>; /* milliCelsius */
|
||||
};
|
||||
|
||||
&cpu_crit {
|
||||
temperature = <105000>; /* milliCelsius */
|
||||
};
|
||||
|
||||
&gpu_crit {
|
||||
temperature = <105000>; /* milliCelsius */
|
||||
};
|
||||
|
||||
&core_crit {
|
||||
temperature = <105000>; /* milliCelsius */
|
||||
};
|
||||
|
||||
&dspeve_crit {
|
||||
temperature = <105000>; /* milliCelsius */
|
||||
};
|
||||
|
||||
&iva_crit {
|
||||
temperature = <105000>; /* milliCelsius */
|
||||
};
|
||||
93
sys/gnu/dts/arm/arm-realview-eb-11mp-revb.dts
Normal file
93
sys/gnu/dts/arm/arm-realview-eb-11mp-revb.dts
Normal file
@ -0,0 +1,93 @@
|
||||
/*
|
||||
* Copyright 2016 Linaro Ltd
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#include "arm-realview-eb-11mp.dts"
|
||||
|
||||
/ {
|
||||
model = "ARM RealView Emulation Baseboard with ARM11MPCore Rev B";
|
||||
};
|
||||
|
||||
/*
|
||||
* The revision B has a distinctly different layout of the syscon, so
|
||||
* append a specific compatible-string.
|
||||
*/
|
||||
&syscon {
|
||||
compatible = "arm,realview-eb11mp-revb-syscon", "arm,realview-eb-syscon", "syscon", "simple-mfd";
|
||||
};
|
||||
|
||||
&intc {
|
||||
reg = <0x10101000 0x1000>,
|
||||
<0x10100100 0x100>;
|
||||
};
|
||||
|
||||
&L2 {
|
||||
reg = <0x10102000 0x1000>;
|
||||
};
|
||||
|
||||
&scu {
|
||||
reg = <0x10100000 0x100>;
|
||||
};
|
||||
|
||||
&twd_timer {
|
||||
reg = <0x10100600 0x20>;
|
||||
};
|
||||
|
||||
&twd_wdog {
|
||||
reg = <0x10100620 0x20>;
|
||||
};
|
||||
|
||||
/*
|
||||
* On revision B, we cannot reach the secondary interrupt
|
||||
* controller, as a result, some peripherals that are dependent
|
||||
* on their IRQ cannot be reached, so disable them.
|
||||
*/
|
||||
&intc_second {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&gpio0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&gpio1 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&gpio2 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&serial2 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&serial3 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&ssp {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&wdog {
|
||||
status = "disabled";
|
||||
};
|
||||
74
sys/gnu/dts/arm/arm-realview-eb-11mp.dts
Normal file
74
sys/gnu/dts/arm/arm-realview-eb-11mp.dts
Normal file
@ -0,0 +1,74 @@
|
||||
/*
|
||||
* Copyright 2016 Linaro Ltd
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "arm-realview-eb-mp.dtsi"
|
||||
|
||||
/ {
|
||||
model = "ARM RealView Emulation Baseboard with ARM11MPCore Rev C";
|
||||
arm,hbi = <0x146>;
|
||||
|
||||
/*
|
||||
* This is the ARM11 MPCore tile (HBI-0146) used with the RealView EB.
|
||||
* Reference: ARM DUI 0318F
|
||||
*
|
||||
* To run this machine with QEMU, specify the following:
|
||||
* qemu-system-arm -M realview-eb-mpcore -smp cpus=4
|
||||
*/
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
enable-method = "arm,realview-smp";
|
||||
|
||||
MP11_0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,arm11mpcore";
|
||||
reg = <0>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
|
||||
MP11_1: cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,arm11mpcore";
|
||||
reg = <1>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
|
||||
MP11_2: cpu@2 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,arm11mpcore";
|
||||
reg = <2>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
|
||||
MP11_3: cpu@3 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,arm11mpcore";
|
||||
reg = <3>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pmu {
|
||||
interrupt-affinity = <&MP11_0>, <&MP11_1>, <&MP11_2>, <&MP11_3>;
|
||||
};
|
||||
70
sys/gnu/dts/arm/arm-realview-eb-a9mp.dts
Normal file
70
sys/gnu/dts/arm/arm-realview-eb-a9mp.dts
Normal file
@ -0,0 +1,70 @@
|
||||
/*
|
||||
* Copyright 2016 Linaro Ltd
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "arm-realview-eb-mp.dtsi"
|
||||
|
||||
/ {
|
||||
model = "ARM RealView EB Cortex A9 MPCore";
|
||||
|
||||
/*
|
||||
* This is the Cortex A9 MPCore tile used with the
|
||||
* RealView EB.
|
||||
*/
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
enable-method = "arm,realview-smp";
|
||||
|
||||
A9_0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
reg = <0>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
|
||||
A9_1: cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
reg = <1>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
|
||||
A9_2: cpu@2 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
reg = <2>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
|
||||
A9_3: cpu@3 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
reg = <3>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pmu {
|
||||
interrupt-affinity = <&A9_0>, <&A9_1>, <&A9_2>, <&A9_3>;
|
||||
};
|
||||
225
sys/gnu/dts/arm/arm-realview-eb-mp.dtsi
Normal file
225
sys/gnu/dts/arm/arm-realview-eb-mp.dtsi
Normal file
@ -0,0 +1,225 @@
|
||||
/*
|
||||
* Copyright 2016 Linaro Ltd
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include "arm-realview-eb.dtsi"
|
||||
|
||||
/*
|
||||
* This is the common include file for all MPCore variants of the
|
||||
* Evaluation Baseboard, i.e. ARM11MPCore, ARM11MPCore Revision B
|
||||
* and Cortex-A9 MPCore.
|
||||
*/
|
||||
/ {
|
||||
soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "arm,realview-eb-soc", "simple-bus";
|
||||
regmap = <&syscon>;
|
||||
ranges;
|
||||
|
||||
/* Primary interrupt controller in the test chip */
|
||||
intc: interrupt-controller@1f000100 {
|
||||
compatible = "arm,eb11mp-gic";
|
||||
#interrupt-cells = <3>;
|
||||
#address-cells = <1>;
|
||||
interrupt-controller;
|
||||
reg = <0x1f001000 0x1000>,
|
||||
<0x1f000100 0x100>;
|
||||
};
|
||||
|
||||
/* Secondary interrupt controller on the FPGA */
|
||||
intc_second: interrupt-controller@10040000 {
|
||||
compatible = "arm,pl390";
|
||||
#interrupt-cells = <3>;
|
||||
#address-cells = <1>;
|
||||
interrupt-controller;
|
||||
reg = <0x10041000 0x1000>,
|
||||
<0x10040000 0x100>;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
L2: l2-cache {
|
||||
compatible = "arm,l220-cache";
|
||||
reg = <0x1f002000 0x1000>;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 30 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 31 IRQ_TYPE_LEVEL_HIGH>;
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
/*
|
||||
* Override default cache size, sets and
|
||||
* associativity as these may be erroneously set
|
||||
* up by boot loader(s), probably for safety
|
||||
* since th outer sync operation can cause the
|
||||
* cache to hang unless disabled.
|
||||
*/
|
||||
cache-size = <1048576>; // 1MB
|
||||
cache-sets = <4096>;
|
||||
cache-line-size = <32>;
|
||||
arm,shared-override;
|
||||
arm,parity-enable;
|
||||
arm,outer-sync-disable;
|
||||
};
|
||||
|
||||
scu: scu@1f000000 {
|
||||
compatible = "arm,arm11mp-scu";
|
||||
reg = <0x1f000000 0x100>;
|
||||
};
|
||||
|
||||
twd_timer: timer@1f000600 {
|
||||
compatible = "arm,arm11mp-twd-timer";
|
||||
reg = <0x1f000600 0x20>;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <1 13 0xf04>;
|
||||
};
|
||||
|
||||
twd_wdog: watchdog@1f000620 {
|
||||
compatible = "arm,arm11mp-twd-wdt";
|
||||
reg = <0x1f000620 0x20>;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <1 14 0xf04>;
|
||||
};
|
||||
|
||||
/* PMU with one IRQ line per core */
|
||||
pmu: pmu@0 {
|
||||
compatible = "arm,arm11mpcore-pmu";
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 18 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 19 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 20 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/*
|
||||
* This adapts all the peripherals to the interrupt routing
|
||||
* to the GIC on the core tile.
|
||||
*/
|
||||
|
||||
ðernet {
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
&usb {
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
&aaci {
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
&mmc {
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 15 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
&kmi0 {
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
&kmi1 {
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
&charlcd {
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
&serial0 {
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
&serial1 {
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
&timer01 {
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
&timer23 {
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
&rtc {
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
/*
|
||||
* On revision A, these peripherals does not have their IRQ lines
|
||||
* routed to the core tile, but they can be reached on the secondary
|
||||
* GIC.
|
||||
*/
|
||||
&gpio0 {
|
||||
interrupt-parent = <&intc_second>;
|
||||
interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
&gpio1 {
|
||||
interrupt-parent = <&intc_second>;
|
||||
interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
&gpio2 {
|
||||
interrupt-parent = <&intc_second>;
|
||||
interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
&serial2 {
|
||||
interrupt-parent = <&intc_second>;
|
||||
interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&serial3 {
|
||||
interrupt-parent = <&intc_second>;
|
||||
interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ssp {
|
||||
interrupt-parent = <&intc_second>;
|
||||
interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wdog {
|
||||
interrupt-parent = <&intc_second>;
|
||||
interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "okay";
|
||||
};
|
||||
166
sys/gnu/dts/arm/arm-realview-eb.dts
Normal file
166
sys/gnu/dts/arm/arm-realview-eb.dts
Normal file
@ -0,0 +1,166 @@
|
||||
/*
|
||||
* Copyright 2016 Linaro Ltd
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include "arm-realview-eb.dtsi"
|
||||
|
||||
/ {
|
||||
model = "ARM RealView Emulation Baseboard";
|
||||
compatible = "arm,realview-eb";
|
||||
arm,hbi = <0x140>;
|
||||
|
||||
/*
|
||||
* This is the core tile with the CPU and GIC etc for the
|
||||
* ARM926EJ-S, ARM1136, ARM1176 that does not have L2 cache
|
||||
* or PMU.
|
||||
*
|
||||
* To run this machine with QEMU, specify the following:
|
||||
* qemu-system-arm -M realview-eb
|
||||
* Unless specified, QEMU will emulate an ARM926EJ-S core tile.
|
||||
* Switches -cpu arm1136 or -cpu arm1176 emulates the other
|
||||
* core tiles.
|
||||
*/
|
||||
soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "arm,realview-eb-soc", "simple-bus";
|
||||
regmap = <&syscon>;
|
||||
ranges;
|
||||
|
||||
intc: interrupt-controller@10040000 {
|
||||
compatible = "arm,pl390";
|
||||
#interrupt-cells = <3>;
|
||||
#address-cells = <1>;
|
||||
interrupt-controller;
|
||||
reg = <0x10041000 0x1000>,
|
||||
<0x10040000 0x100>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/*
|
||||
* This adapts all the peripherals to the interrupt routing
|
||||
* to the GIC on the core tile.
|
||||
*/
|
||||
|
||||
ðernet {
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
&usb {
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
&aaci {
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
&mmc {
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 18 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
&kmi0 {
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
&kmi1 {
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
&charlcd {
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
&serial0 {
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
&serial1 {
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
&serial2 {
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
&serial3 {
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
&ssp {
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
&wdog {
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
&timer01 {
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
&timer23 {
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
&gpio0 {
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
&gpio1 {
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
&gpio2 {
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
&rtc {
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
&clcd {
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
453
sys/gnu/dts/arm/arm-realview-eb.dtsi
Normal file
453
sys/gnu/dts/arm/arm-realview-eb.dtsi
Normal file
@ -0,0 +1,453 @@
|
||||
/*
|
||||
* Copyright 2016 Linaro Ltd
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "arm,realview-eb";
|
||||
|
||||
chosen { };
|
||||
|
||||
aliases {
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
serial2 = &serial2;
|
||||
serial3 = &serial3;
|
||||
i2c0 = &i2c;
|
||||
};
|
||||
|
||||
memory {
|
||||
/* 128 MiB memory @ 0x0 */
|
||||
reg = <0x00000000 0x08000000>;
|
||||
};
|
||||
|
||||
/* The voltage to the MMC card is hardwired at 3.3V */
|
||||
vmmc: fixedregulator@0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vmmc";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
veth: fixedregulator@0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "veth";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
xtal24mhz: xtal24mhz@24M {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
|
||||
timclk: timclk@1M {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clock-div = <24>;
|
||||
clock-mult = <1>;
|
||||
clocks = <&xtal24mhz>;
|
||||
};
|
||||
|
||||
mclk: mclk@24M {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clock-div = <1>;
|
||||
clock-mult = <1>;
|
||||
clocks = <&xtal24mhz>;
|
||||
};
|
||||
|
||||
kmiclk: kmiclk@24M {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clock-div = <1>;
|
||||
clock-mult = <1>;
|
||||
clocks = <&xtal24mhz>;
|
||||
};
|
||||
|
||||
sspclk: sspclk@24M {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clock-div = <1>;
|
||||
clock-mult = <1>;
|
||||
clocks = <&xtal24mhz>;
|
||||
};
|
||||
|
||||
uartclk: uartclk@24M {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clock-div = <1>;
|
||||
clock-mult = <1>;
|
||||
clocks = <&xtal24mhz>;
|
||||
};
|
||||
|
||||
wdogclk: wdogclk@24M {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clock-div = <1>;
|
||||
clock-mult = <1>;
|
||||
clocks = <&xtal24mhz>;
|
||||
};
|
||||
|
||||
/* FIXME: this actually hangs off the PLL clocks */
|
||||
pclk: pclk@0 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
flash0@40000000 {
|
||||
/* 2 * 32MiB NOR Flash memory */
|
||||
compatible = "arm,versatile-flash", "cfi-flash";
|
||||
reg = <0x40000000 0x04000000>;
|
||||
bank-width = <4>;
|
||||
};
|
||||
|
||||
flash1@44000000 {
|
||||
/* 2 * 32MiB NOR Flash memory */
|
||||
compatible = "arm,versatile-flash", "cfi-flash";
|
||||
reg = <0x44000000 0x04000000>;
|
||||
bank-width = <4>;
|
||||
};
|
||||
|
||||
/* SMSC 9118 ethernet with PHY and EEPROM */
|
||||
ethernet: ethernet@4e000000 {
|
||||
compatible = "smsc,lan9118", "smsc,lan9115";
|
||||
reg = <0x4e000000 0x10000>;
|
||||
phy-mode = "mii";
|
||||
reg-io-width = <4>;
|
||||
smsc,irq-active-high;
|
||||
smsc,irq-push-pull;
|
||||
vdd33a-supply = <&veth>;
|
||||
vddvario-supply = <&veth>;
|
||||
};
|
||||
|
||||
usb: usb@4f000000 {
|
||||
compatible = "nxp,usb-isp1761";
|
||||
reg = <0x4f000000 0x20000>;
|
||||
port1-otg;
|
||||
};
|
||||
|
||||
/* These peripherals are inside the FPGA */
|
||||
fpga {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "simple-bus";
|
||||
ranges;
|
||||
|
||||
syscon: syscon@10000000 {
|
||||
compatible = "arm,realview-eb-syscon", "syscon", "simple-mfd";
|
||||
reg = <0x10000000 0x1000>;
|
||||
|
||||
led@08.0 {
|
||||
compatible = "register-bit-led";
|
||||
offset = <0x08>;
|
||||
mask = <0x01>;
|
||||
label = "versatile:0";
|
||||
linux,default-trigger = "heartbeat";
|
||||
default-state = "on";
|
||||
};
|
||||
led@08.1 {
|
||||
compatible = "register-bit-led";
|
||||
offset = <0x08>;
|
||||
mask = <0x02>;
|
||||
label = "versatile:1";
|
||||
linux,default-trigger = "mmc0";
|
||||
default-state = "off";
|
||||
};
|
||||
led@08.2 {
|
||||
compatible = "register-bit-led";
|
||||
offset = <0x08>;
|
||||
mask = <0x04>;
|
||||
label = "versatile:2";
|
||||
linux,default-trigger = "cpu0";
|
||||
default-state = "off";
|
||||
};
|
||||
led@08.3 {
|
||||
compatible = "register-bit-led";
|
||||
offset = <0x08>;
|
||||
mask = <0x08>;
|
||||
label = "versatile:3";
|
||||
default-state = "off";
|
||||
};
|
||||
led@08.4 {
|
||||
compatible = "register-bit-led";
|
||||
offset = <0x08>;
|
||||
mask = <0x10>;
|
||||
label = "versatile:4";
|
||||
default-state = "off";
|
||||
};
|
||||
led@08.5 {
|
||||
compatible = "register-bit-led";
|
||||
offset = <0x08>;
|
||||
mask = <0x20>;
|
||||
label = "versatile:5";
|
||||
default-state = "off";
|
||||
};
|
||||
led@08.6 {
|
||||
compatible = "register-bit-led";
|
||||
offset = <0x08>;
|
||||
mask = <0x40>;
|
||||
label = "versatile:6";
|
||||
default-state = "off";
|
||||
};
|
||||
led@08.7 {
|
||||
compatible = "register-bit-led";
|
||||
offset = <0x08>;
|
||||
mask = <0x80>;
|
||||
label = "versatile:7";
|
||||
default-state = "off";
|
||||
};
|
||||
oscclk0: osc0@0c {
|
||||
compatible = "arm,syscon-icst307";
|
||||
#clock-cells = <0>;
|
||||
lock-offset = <0x20>;
|
||||
vco-offset = <0x0C>;
|
||||
clocks = <&xtal24mhz>;
|
||||
};
|
||||
oscclk1: osc1@10 {
|
||||
compatible = "arm,syscon-icst307";
|
||||
#clock-cells = <0>;
|
||||
lock-offset = <0x20>;
|
||||
vco-offset = <0x10>;
|
||||
clocks = <&xtal24mhz>;
|
||||
};
|
||||
oscclk2: osc2@14 {
|
||||
compatible = "arm,syscon-icst307";
|
||||
#clock-cells = <0>;
|
||||
lock-offset = <0x20>;
|
||||
vco-offset = <0x14>;
|
||||
clocks = <&xtal24mhz>;
|
||||
};
|
||||
oscclk3: osc3@18 {
|
||||
compatible = "arm,syscon-icst307";
|
||||
#clock-cells = <0>;
|
||||
lock-offset = <0x20>;
|
||||
vco-offset = <0x18>;
|
||||
clocks = <&xtal24mhz>;
|
||||
};
|
||||
oscclk4: osc4@1c {
|
||||
compatible = "arm,syscon-icst307";
|
||||
#clock-cells = <0>;
|
||||
lock-offset = <0x20>;
|
||||
vco-offset = <0x1c>;
|
||||
clocks = <&xtal24mhz>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c: i2c@10002000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "arm,versatile-i2c";
|
||||
reg = <0x10002000 0x1000>;
|
||||
|
||||
rtc@68 {
|
||||
compatible = "dallas,ds1338";
|
||||
reg = <0x68>;
|
||||
};
|
||||
};
|
||||
|
||||
aaci: aaci@10004000 {
|
||||
compatible = "arm,pl041", "arm,primecell";
|
||||
reg = <0x10004000 0x1000>;
|
||||
clocks = <&pclk>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
mmc: mmcsd@10005000 {
|
||||
compatible = "arm,pl18x", "arm,primecell";
|
||||
reg = <0x10005000 0x1000>;
|
||||
|
||||
/* Due to frequent FIFO overruns, use just 500 kHz */
|
||||
max-frequency = <500000>;
|
||||
bus-width = <4>;
|
||||
cap-sd-highspeed;
|
||||
cap-mmc-highspeed;
|
||||
clocks = <&mclk>, <&pclk>;
|
||||
clock-names = "mclk", "apb_pclk";
|
||||
vmmc-supply = <&vmmc>;
|
||||
cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
|
||||
wp-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
kmi0: kmi@10006000 {
|
||||
compatible = "arm,pl050", "arm,primecell";
|
||||
reg = <0x10006000 0x1000>;
|
||||
clocks = <&kmiclk>, <&pclk>;
|
||||
clock-names = "KMIREFCLK", "apb_pclk";
|
||||
};
|
||||
|
||||
kmi1: kmi@10007000 {
|
||||
compatible = "arm,pl050", "arm,primecell";
|
||||
reg = <0x10007000 0x1000>;
|
||||
clocks = <&kmiclk>, <&pclk>;
|
||||
clock-names = "KMIREFCLK", "apb_pclk";
|
||||
};
|
||||
|
||||
charlcd: fpga_charlcd: charlcd@10008000 {
|
||||
compatible = "arm,versatile-lcd";
|
||||
reg = <0x10008000 0x1000>;
|
||||
clocks = <&pclk>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
serial0: serial@10009000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0x10009000 0x1000>;
|
||||
clocks = <&uartclk>, <&pclk>;
|
||||
clock-names = "uartclk", "apb_pclk";
|
||||
};
|
||||
|
||||
serial1: serial@1000a000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0x1000a000 0x1000>;
|
||||
clocks = <&uartclk>, <&pclk>;
|
||||
clock-names = "uartclk", "apb_pclk";
|
||||
};
|
||||
|
||||
serial2: serial@1000b000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0x1000b000 0x1000>;
|
||||
clocks = <&uartclk>, <&pclk>;
|
||||
clock-names = "uartclk", "apb_pclk";
|
||||
};
|
||||
|
||||
serial3: serial@1000c000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0x1000c000 0x1000>;
|
||||
clocks = <&uartclk>, <&pclk>;
|
||||
clock-names = "uartclk", "apb_pclk";
|
||||
};
|
||||
|
||||
ssp: ssp@1000d000 {
|
||||
compatible = "arm,pl022", "arm,primecell";
|
||||
reg = <0x1000d000 0x1000>;
|
||||
clocks = <&sspclk>, <&pclk>;
|
||||
clock-names = "SSPCLK", "apb_pclk";
|
||||
};
|
||||
|
||||
wdog: watchdog@10010000 {
|
||||
compatible = "arm,sp805", "arm,primecell";
|
||||
reg = <0x10010000 0x1000>;
|
||||
clocks = <&wdogclk>, <&pclk>;
|
||||
clock-names = "wdogclk", "apb_pclk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
timer01: timer@10011000 {
|
||||
compatible = "arm,sp804", "arm,primecell";
|
||||
reg = <0x10011000 0x1000>;
|
||||
clocks = <&timclk>, <&timclk>, <&pclk>;
|
||||
clock-names = "timer1", "timer2", "apb_pclk";
|
||||
};
|
||||
|
||||
timer23: timer@10012000 {
|
||||
compatible = "arm,sp804", "arm,primecell";
|
||||
reg = <0x10012000 0x1000>;
|
||||
clocks = <&timclk>, <&timclk>, <&pclk>;
|
||||
clock-names = "timer1", "timer2", "apb_pclk";
|
||||
};
|
||||
|
||||
gpio0: gpio@10013000 {
|
||||
compatible = "arm,pl061", "arm,primecell";
|
||||
reg = <0x10013000 0x1000>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
clocks = <&pclk>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
gpio1: gpio@10014000 {
|
||||
compatible = "arm,pl061", "arm,primecell";
|
||||
reg = <0x10014000 0x1000>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
clocks = <&pclk>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
gpio2: gpio@10015000 {
|
||||
compatible = "arm,pl061", "arm,primecell";
|
||||
reg = <0x10015000 0x1000>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
clocks = <&pclk>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
rtc: rtc@10017000 {
|
||||
compatible = "arm,pl031", "arm,primecell";
|
||||
reg = <0x10017000 0x1000>;
|
||||
clocks = <&pclk>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
clcd: clcd@10020000 {
|
||||
compatible = "arm,pl111", "arm,primecell";
|
||||
reg = <0x10020000 0x1000>;
|
||||
interrupt-names = "combined";
|
||||
clocks = <&oscclk0>, <&pclk>;
|
||||
clock-names = "clcdclk", "apb_pclk";
|
||||
|
||||
port {
|
||||
clcd_pads: endpoint {
|
||||
remote-endpoint = <&clcd_panel>;
|
||||
arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
|
||||
};
|
||||
};
|
||||
|
||||
panel {
|
||||
compatible = "panel-dpi";
|
||||
|
||||
port {
|
||||
clcd_panel: endpoint {
|
||||
remote-endpoint = <&clcd_pads>;
|
||||
};
|
||||
};
|
||||
|
||||
/* Standard 640x480 VGA timings */
|
||||
panel-timing {
|
||||
clock-frequency = <25175000>;
|
||||
hactive = <640>;
|
||||
hback-porch = <48>;
|
||||
hfront-porch = <16>;
|
||||
hsync-len = <96>;
|
||||
vactive = <480>;
|
||||
vback-porch = <33>;
|
||||
vfront-porch = <10>;
|
||||
vsync-len = <2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
178
sys/gnu/dts/arm/arm-realview-pba8.dts
Normal file
178
sys/gnu/dts/arm/arm-realview-pba8.dts
Normal file
@ -0,0 +1,178 @@
|
||||
/*
|
||||
* Copyright 2016 Linaro Ltd
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "arm-realview-pbx.dtsi"
|
||||
|
||||
/ {
|
||||
model = "ARM RealView Platform Baseboard for Cortex-A8";
|
||||
compatible = "arm,realview-pba8";
|
||||
arm,hbi = <0x178>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
enable-method = "arm,realview-smp";
|
||||
|
||||
cpu0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a8";
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
pmu: pmu@0 {
|
||||
compatible = "arm,cortex-a8-pmu";
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-affinity = <&cpu0>;
|
||||
};
|
||||
|
||||
/* Primary GIC PL390 interrupt controller in the test chip */
|
||||
intc: interrupt-controller@1e000000 {
|
||||
compatible = "arm,pl390";
|
||||
#interrupt-cells = <3>;
|
||||
#address-cells = <1>;
|
||||
interrupt-controller;
|
||||
reg = <0x1e001000 0x1000>,
|
||||
<0x1e000000 0x100>;
|
||||
};
|
||||
};
|
||||
|
||||
ðernet {
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
&usb {
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
&soc {
|
||||
compatible = "arm,realview-pba8-soc", "simple-bus";
|
||||
};
|
||||
|
||||
&syscon {
|
||||
compatible = "arm,realview-pba8-syscon", "syscon", "simple-mfd";
|
||||
};
|
||||
|
||||
&serial0 {
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
&serial1 {
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
&serial2 {
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
&serial3 {
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
&ssp {
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
&wdog0 {
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
&wdog1 {
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
&timer01 {
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
&timer23 {
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
&gpio0 {
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
&gpio1 {
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
&gpio2 {
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
&rtc {
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
&timer45 {
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
&timer67 {
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
&aaci {
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
&mmc {
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 18 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
&kmi0 {
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
&kmi1 {
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
&clcd {
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
229
sys/gnu/dts/arm/arm-realview-pbx-a9.dts
Normal file
229
sys/gnu/dts/arm/arm-realview-pbx-a9.dts
Normal file
@ -0,0 +1,229 @@
|
||||
/*
|
||||
* Copyright 2016 Linaro Ltd
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "arm-realview-pbx.dtsi"
|
||||
|
||||
/ {
|
||||
/*
|
||||
* This is the RealView Platform Baseboard Explore for Cortex-A9
|
||||
* (HBI0182 + HBI0183) as described in ARM DUI 0440B
|
||||
*/
|
||||
model = "ARM RealView Platform Baseboard Explore for Cortex-A9";
|
||||
arm,hbi = <0x182>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
enable-method = "arm,realview-smp";
|
||||
|
||||
cpu-map {
|
||||
cluster0 {
|
||||
core0 {
|
||||
cpu = <&CPU0>;
|
||||
};
|
||||
core1 {
|
||||
cpu = <&CPU1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
CPU0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
reg = <0x0>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
CPU1: cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
reg = <0x1>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
};
|
||||
|
||||
L2: l2-cache {
|
||||
compatible = "arm,pl310-cache";
|
||||
reg = <0x1f002000 0x1000>;
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
/*
|
||||
* Override default cache size, sets and
|
||||
* associativity as these may be erroneously set
|
||||
* up by boot loader(s).
|
||||
*/
|
||||
cache-size = <1048576>; // 1MB
|
||||
cache-sets = <4096>;
|
||||
cache-line-size = <32>;
|
||||
arm,parity-disable;
|
||||
arm,tag-latency = <1>;
|
||||
arm,data-latency = <1 1>;
|
||||
arm,dirty-latency = <1>;
|
||||
};
|
||||
|
||||
scu: scu@1f000000 {
|
||||
compatible = "arm,cortex-a9-scu";
|
||||
reg = <0x1f000000 0x100>;
|
||||
};
|
||||
|
||||
twd_timer: timer@1f000600 {
|
||||
compatible = "arm,cortex-a9-twd-timer";
|
||||
reg = <0x1f000600 0x20>;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <1 13 0xf04>;
|
||||
};
|
||||
|
||||
twd_wdog: watchdog@1f000620 {
|
||||
compatible = "arm,cortex-a9-twd-wdt";
|
||||
reg = <0x1f000620 0x20>;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <1 14 0xf04>;
|
||||
};
|
||||
|
||||
pmu: pmu@0 {
|
||||
compatible = "arm,cortex-a9-pmu";
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 45 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-affinity = <&CPU0>, <&CPU1>;
|
||||
};
|
||||
|
||||
/* Primary GIC PL390 interrupt controller in the test chip */
|
||||
intc: interrupt-controller@1f000000 {
|
||||
compatible = "arm,cortex-a9-gic";
|
||||
#interrupt-cells = <3>;
|
||||
#address-cells = <1>;
|
||||
interrupt-controller;
|
||||
reg = <0x1f001000 0x1000>,
|
||||
<0x1f000100 0x100>;
|
||||
};
|
||||
};
|
||||
|
||||
ðernet {
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
&usb {
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
&serial0 {
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
&serial1 {
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
&serial2 {
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
&serial3 {
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
&ssp {
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
&wdog0 {
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
&wdog1 {
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
&timer01 {
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
&timer23 {
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
&gpio0 {
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
&gpio1 {
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
&gpio2 {
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
&rtc {
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
&timer45 {
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
&timer67 {
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
&aaci {
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
&mmc {
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 18 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
&kmi0 {
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
&kmi1 {
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
&clcd {
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
542
sys/gnu/dts/arm/arm-realview-pbx.dtsi
Normal file
542
sys/gnu/dts/arm/arm-realview-pbx.dtsi
Normal file
@ -0,0 +1,542 @@
|
||||
/*
|
||||
* Copyright 2016 Linaro Ltd
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "arm,realview-pbx";
|
||||
|
||||
chosen { };
|
||||
|
||||
aliases {
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
serial2 = &serial2;
|
||||
serial3 = &serial3;
|
||||
i2c0 = &i2c;
|
||||
};
|
||||
|
||||
memory {
|
||||
/* 128 MiB memory @ 0x0 */
|
||||
reg = <0x00000000 0x08000000>;
|
||||
};
|
||||
|
||||
/* The voltage to the MMC card is hardwired at 3.3V */
|
||||
vmmc: fixedregulator@0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vmmc";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
veth: fixedregulator@0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "veth";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
xtal24mhz: xtal24mhz@24M {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
|
||||
refclk32khz: refclk32khz {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
timclk: timclk@1M {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clock-div = <24>;
|
||||
clock-mult = <1>;
|
||||
clocks = <&xtal24mhz>;
|
||||
};
|
||||
|
||||
mclk: mclk@24M {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clock-div = <1>;
|
||||
clock-mult = <1>;
|
||||
clocks = <&xtal24mhz>;
|
||||
};
|
||||
|
||||
kmiclk: kmiclk@24M {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clock-div = <1>;
|
||||
clock-mult = <1>;
|
||||
clocks = <&xtal24mhz>;
|
||||
};
|
||||
|
||||
sspclk: sspclk@24M {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clock-div = <1>;
|
||||
clock-mult = <1>;
|
||||
clocks = <&xtal24mhz>;
|
||||
};
|
||||
|
||||
uartclk: uartclk@24M {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clock-div = <1>;
|
||||
clock-mult = <1>;
|
||||
clocks = <&xtal24mhz>;
|
||||
};
|
||||
|
||||
wdogclk: wdogclk@24M {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clock-div = <1>;
|
||||
clock-mult = <1>;
|
||||
clocks = <&xtal24mhz>;
|
||||
};
|
||||
|
||||
/* FIXME: this actually hangs off the PLL clocks */
|
||||
pclk: pclk@0 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
flash0@40000000 {
|
||||
/* 2 * 32MiB NOR Flash memory */
|
||||
compatible = "arm,versatile-flash", "cfi-flash";
|
||||
reg = <0x40000000 0x04000000>;
|
||||
bank-width = <4>;
|
||||
};
|
||||
|
||||
flash1@44000000 {
|
||||
/* 2 * 32MiB NOR Flash memory */
|
||||
compatible = "arm,versatile-flash", "cfi-flash";
|
||||
reg = <0x44000000 0x04000000>;
|
||||
bank-width = <4>;
|
||||
};
|
||||
|
||||
/* SMSC 9118 ethernet with PHY and EEPROM */
|
||||
ethernet: ethernet@4e000000 {
|
||||
compatible = "smsc,lan9118", "smsc,lan9115";
|
||||
reg = <0x4e000000 0x10000>;
|
||||
phy-mode = "mii";
|
||||
reg-io-width = <4>;
|
||||
smsc,irq-active-high;
|
||||
smsc,irq-push-pull;
|
||||
vdd33a-supply = <&veth>;
|
||||
vddvario-supply = <&veth>;
|
||||
};
|
||||
|
||||
usb: usb@4f000000 {
|
||||
compatible = "nxp,usb-isp1761";
|
||||
reg = <0x4f000000 0x20000>;
|
||||
port1-otg;
|
||||
};
|
||||
|
||||
soc: soc@0 {
|
||||
compatible = "arm,realview-pbx-soc", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
regmap = <&syscon>;
|
||||
ranges;
|
||||
|
||||
syscon: syscon@10000000 {
|
||||
compatible = "arm,realview-pbx-syscon", "syscon", "simple-mfd";
|
||||
reg = <0x10000000 0x1000>;
|
||||
|
||||
led@08.0 {
|
||||
compatible = "register-bit-led";
|
||||
offset = <0x08>;
|
||||
mask = <0x01>;
|
||||
label = "versatile:0";
|
||||
linux,default-trigger = "heartbeat";
|
||||
default-state = "on";
|
||||
};
|
||||
led@08.1 {
|
||||
compatible = "register-bit-led";
|
||||
offset = <0x08>;
|
||||
mask = <0x02>;
|
||||
label = "versatile:1";
|
||||
linux,default-trigger = "mmc0";
|
||||
default-state = "off";
|
||||
};
|
||||
led@08.2 {
|
||||
compatible = "register-bit-led";
|
||||
offset = <0x08>;
|
||||
mask = <0x04>;
|
||||
label = "versatile:2";
|
||||
linux,default-trigger = "cpu0";
|
||||
default-state = "off";
|
||||
};
|
||||
led@08.3 {
|
||||
compatible = "register-bit-led";
|
||||
offset = <0x08>;
|
||||
mask = <0x08>;
|
||||
label = "versatile:3";
|
||||
default-state = "off";
|
||||
};
|
||||
led@08.4 {
|
||||
compatible = "register-bit-led";
|
||||
offset = <0x08>;
|
||||
mask = <0x10>;
|
||||
label = "versatile:4";
|
||||
default-state = "off";
|
||||
};
|
||||
led@08.5 {
|
||||
compatible = "register-bit-led";
|
||||
offset = <0x08>;
|
||||
mask = <0x20>;
|
||||
label = "versatile:5";
|
||||
default-state = "off";
|
||||
};
|
||||
led@08.6 {
|
||||
compatible = "register-bit-led";
|
||||
offset = <0x08>;
|
||||
mask = <0x40>;
|
||||
label = "versatile:6";
|
||||
default-state = "off";
|
||||
};
|
||||
led@08.7 {
|
||||
compatible = "register-bit-led";
|
||||
offset = <0x08>;
|
||||
mask = <0x80>;
|
||||
label = "versatile:7";
|
||||
default-state = "off";
|
||||
};
|
||||
oscclk0: osc0@0c {
|
||||
compatible = "arm,syscon-icst307";
|
||||
#clock-cells = <0>;
|
||||
lock-offset = <0x20>;
|
||||
vco-offset = <0x0C>;
|
||||
clocks = <&xtal24mhz>;
|
||||
};
|
||||
oscclk1: osc1@10 {
|
||||
compatible = "arm,syscon-icst307";
|
||||
#clock-cells = <0>;
|
||||
lock-offset = <0x20>;
|
||||
vco-offset = <0x10>;
|
||||
clocks = <&xtal24mhz>;
|
||||
};
|
||||
oscclk2: osc2@14 {
|
||||
compatible = "arm,syscon-icst307";
|
||||
#clock-cells = <0>;
|
||||
lock-offset = <0x20>;
|
||||
vco-offset = <0x14>;
|
||||
clocks = <&xtal24mhz>;
|
||||
};
|
||||
oscclk3: osc3@18 {
|
||||
compatible = "arm,syscon-icst307";
|
||||
#clock-cells = <0>;
|
||||
lock-offset = <0x20>;
|
||||
vco-offset = <0x18>;
|
||||
clocks = <&xtal24mhz>;
|
||||
};
|
||||
oscclk4: osc4@1c {
|
||||
compatible = "arm,syscon-icst307";
|
||||
#clock-cells = <0>;
|
||||
lock-offset = <0x20>;
|
||||
vco-offset = <0x1c>;
|
||||
clocks = <&xtal24mhz>;
|
||||
};
|
||||
};
|
||||
|
||||
sp810_syscon0: sysctl@10001000 {
|
||||
compatible = "arm,sp810", "arm,primecell";
|
||||
reg = <0x10001000 0x1000>;
|
||||
clocks = <&refclk32khz>, <&timclk>, <&xtal24mhz>;
|
||||
clock-names = "refclk", "timclk", "apb_pclk";
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "timerclk0",
|
||||
"timerclk1",
|
||||
"timerclk2",
|
||||
"timerclk3";
|
||||
assigned-clocks = <&sp810_syscon0 0>,
|
||||
<&sp810_syscon0 1>,
|
||||
<&sp810_syscon0 2>,
|
||||
<&sp810_syscon0 3>;
|
||||
assigned-clock-parents = <&timclk>,
|
||||
<&timclk>,
|
||||
<&timclk>,
|
||||
<&timclk>;
|
||||
};
|
||||
|
||||
i2c: i2c@10002000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "arm,versatile-i2c";
|
||||
reg = <0x10002000 0x1000>;
|
||||
|
||||
rtc@68 {
|
||||
compatible = "dallas,ds1338";
|
||||
reg = <0x68>;
|
||||
};
|
||||
};
|
||||
|
||||
serial0: serial@10009000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0x10009000 0x1000>;
|
||||
clocks = <&uartclk>, <&pclk>;
|
||||
clock-names = "uartclk", "apb_pclk";
|
||||
};
|
||||
|
||||
serial1: serial@1000a000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0x1000a000 0x1000>;
|
||||
clocks = <&uartclk>, <&pclk>;
|
||||
clock-names = "uartclk", "apb_pclk";
|
||||
};
|
||||
|
||||
serial2: serial@1000b000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0x1000b000 0x1000>;
|
||||
clocks = <&uartclk>, <&pclk>;
|
||||
clock-names = "uartclk", "apb_pclk";
|
||||
};
|
||||
|
||||
ssp: ssp@1000d000 {
|
||||
compatible = "arm,pl022", "arm,primecell";
|
||||
reg = <0x1000d000 0x1000>;
|
||||
clocks = <&sspclk>, <&pclk>;
|
||||
clock-names = "SSPCLK", "apb_pclk";
|
||||
};
|
||||
|
||||
wdog0: watchdog@1000f000 {
|
||||
compatible = "arm,sp805", "arm,primecell";
|
||||
reg = <0x1000f000 0x1000>;
|
||||
clocks = <&wdogclk>, <&pclk>;
|
||||
clock-names = "wdogclk", "apb_pclk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
wdog1: watchdog@10010000 {
|
||||
compatible = "arm,sp805", "arm,primecell";
|
||||
reg = <0x10010000 0x1000>;
|
||||
clocks = <&wdogclk>, <&pclk>;
|
||||
clock-names = "wdogclk", "apb_pclk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
timer01: timer@10011000 {
|
||||
compatible = "arm,sp804", "arm,primecell";
|
||||
reg = <0x10011000 0x1000>;
|
||||
clocks = <&sp810_syscon0 0>,
|
||||
<&sp810_syscon0 1>,
|
||||
<&pclk>;
|
||||
clock-names = "timerclk0",
|
||||
"timerclk1",
|
||||
"apb_pclk";
|
||||
};
|
||||
|
||||
timer23: timer@10012000 {
|
||||
compatible = "arm,sp804", "arm,primecell";
|
||||
reg = <0x10012000 0x1000>;
|
||||
clocks = <&sp810_syscon0 2>,
|
||||
<&sp810_syscon0 3>,
|
||||
<&pclk>;
|
||||
clock-names = "timerclk2",
|
||||
"timerclk3",
|
||||
"apb_pclk";
|
||||
};
|
||||
|
||||
gpio0: gpio@10013000 {
|
||||
compatible = "arm,pl061", "arm,primecell";
|
||||
reg = <0x10013000 0x1000>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
clocks = <&pclk>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
gpio1: gpio@10014000 {
|
||||
compatible = "arm,pl061", "arm,primecell";
|
||||
reg = <0x10014000 0x1000>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
clocks = <&pclk>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
gpio2: gpio@10015000 {
|
||||
compatible = "arm,pl061", "arm,primecell";
|
||||
reg = <0x10015000 0x1000>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
clocks = <&pclk>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
/* DVI serial bus control is at 10016000 */
|
||||
|
||||
rtc: rtc@10017000 {
|
||||
compatible = "arm,pl031", "arm,primecell";
|
||||
reg = <0x10017000 0x1000>;
|
||||
clocks = <&pclk>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
timer45: timer@10018000 {
|
||||
compatible = "arm,sp804", "arm,primecell";
|
||||
reg = <0x10018000 0x1000>;
|
||||
clocks = <&timclk>, <&timclk>, <&pclk>;
|
||||
clock-names = "timerclk4", "timerclk5", "apb_pclk";
|
||||
};
|
||||
|
||||
timer67: timer@10019000 {
|
||||
compatible = "arm,sp804", "arm,primecell";
|
||||
reg = <0x10019000 0x1000>;
|
||||
clocks = <&timclk>, <&timclk>, <&pclk>;
|
||||
clock-names = "timerclk6", "timerclk7", "apb_pclk";
|
||||
};
|
||||
|
||||
sp810_syscon1: sysctl@1001a000 {
|
||||
compatible = "arm,sp810", "arm,primecell";
|
||||
reg = <0x1001a000 0x1000>;
|
||||
clocks = <&refclk32khz>, <&timclk>, <&xtal24mhz>;
|
||||
clock-names = "refclk", "timclk", "apb_pclk";
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "timerclk4",
|
||||
"timerclk5",
|
||||
"timerclk6",
|
||||
"timerclk7";
|
||||
assigned-clocks = <&sp810_syscon1 0>,
|
||||
<&sp810_syscon1 1>,
|
||||
<&sp810_syscon1 2>,
|
||||
<&sp810_syscon1 3>;
|
||||
assigned-clock-parents = <&timclk>,
|
||||
<&timclk>,
|
||||
<&timclk>,
|
||||
<&timclk>;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
/* These peripherals are inside the FPGA */
|
||||
fpga {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "simple-bus";
|
||||
ranges;
|
||||
|
||||
aaci: aaci@10004000 {
|
||||
compatible = "arm,pl041", "arm,primecell";
|
||||
reg = <0x10004000 0x1000>;
|
||||
clocks = <&pclk>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
mmc: mmcsd@10005000 {
|
||||
compatible = "arm,pl18x", "arm,primecell";
|
||||
reg = <0x10005000 0x1000>;
|
||||
|
||||
/* Due to frequent FIFO overruns, use just 500 kHz */
|
||||
max-frequency = <500000>;
|
||||
bus-width = <4>;
|
||||
cap-sd-highspeed;
|
||||
cap-mmc-highspeed;
|
||||
clocks = <&mclk>, <&pclk>;
|
||||
clock-names = "mclk", "apb_pclk";
|
||||
vmmc-supply = <&vmmc>;
|
||||
cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
|
||||
wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
kmi0: kmi@10006000 {
|
||||
compatible = "arm,pl050", "arm,primecell";
|
||||
reg = <0x10006000 0x1000>;
|
||||
clocks = <&kmiclk>, <&pclk>;
|
||||
clock-names = "KMIREFCLK", "apb_pclk";
|
||||
};
|
||||
|
||||
kmi1: kmi@10007000 {
|
||||
compatible = "arm,pl050", "arm,primecell";
|
||||
reg = <0x10007000 0x1000>;
|
||||
clocks = <&kmiclk>, <&pclk>;
|
||||
clock-names = "KMIREFCLK", "apb_pclk";
|
||||
};
|
||||
|
||||
serial3: serial@1000c000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0x1000c000 0x1000>;
|
||||
clocks = <&uartclk>, <&pclk>;
|
||||
clock-names = "uartclk", "apb_pclk";
|
||||
};
|
||||
};
|
||||
|
||||
/* These peripherals are inside the NEC ISSP */
|
||||
issp {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "simple-bus";
|
||||
ranges;
|
||||
|
||||
clcd: clcd@10020000 {
|
||||
compatible = "arm,pl111", "arm,primecell";
|
||||
reg = <0x10020000 0x1000>;
|
||||
interrupt-names = "combined";
|
||||
clocks = <&oscclk4>, <&pclk>;
|
||||
clock-names = "clcdclk", "apb_pclk";
|
||||
|
||||
port {
|
||||
clcd_pads: endpoint {
|
||||
remote-endpoint = <&clcd_panel>;
|
||||
arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
|
||||
};
|
||||
};
|
||||
|
||||
panel {
|
||||
compatible = "panel-dpi";
|
||||
|
||||
port {
|
||||
clcd_panel: endpoint {
|
||||
remote-endpoint = <&clcd_pads>;
|
||||
};
|
||||
};
|
||||
|
||||
/* Standard 640x480 VGA timings */
|
||||
panel-timing {
|
||||
clock-frequency = <25175000>;
|
||||
hactive = <640>;
|
||||
hback-porch = <48>;
|
||||
hfront-porch = <16>;
|
||||
hsync-len = <96>;
|
||||
vactive = <480>;
|
||||
vback-porch = <33>;
|
||||
vfront-porch = <10>;
|
||||
vsync-len = <2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
64
sys/gnu/dts/arm/artpec6-devboard.dts
Normal file
64
sys/gnu/dts/arm/artpec6-devboard.dts
Normal file
@ -0,0 +1,64 @@
|
||||
/*
|
||||
* Axis ARTPEC-6 development board.
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public License
|
||||
* version 2. This program is licensed "as is" without any warranty of any
|
||||
* kind, whether express or implied.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "artpec6.dtsi"
|
||||
|
||||
/ {
|
||||
model = "ARTPEC-6 development board";
|
||||
compatible = "axis,artpec6-dev-board", "axis,artpec6";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
serial1 = &uart1;
|
||||
serial2 = &uart2;
|
||||
serial3 = &uart3;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial3:115200n8";
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x10000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ðernet {
|
||||
status = "okay";
|
||||
|
||||
phy-handle = <&phy1>;
|
||||
phy-mode = "gmii";
|
||||
|
||||
mdio {
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x0>;
|
||||
phy1: phy@0 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
device_type = "ethernet-phy";
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
211
sys/gnu/dts/arm/artpec6.dtsi
Normal file
211
sys/gnu/dts/arm/artpec6.dtsi
Normal file
@ -0,0 +1,211 @@
|
||||
/*
|
||||
* Device Tree Source for the Axis ARTPEC-6 SoC
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "axis,artpec6";
|
||||
interrupt-parent = <&intc>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
reg = <0>;
|
||||
next-level-cache = <&pl310>;
|
||||
};
|
||||
|
||||
cpu1: cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
reg = <1>;
|
||||
next-level-cache = <&pl310>;
|
||||
};
|
||||
};
|
||||
|
||||
syscon {
|
||||
compatible = "axis,artpec6-syscon", "syscon";
|
||||
reg = <0xf8000000 0x48>;
|
||||
};
|
||||
|
||||
psci {
|
||||
compatible = "arm,psci-0.2", "arm,psci";
|
||||
method = "smc";
|
||||
psci_version = <0x84000000>;
|
||||
cpu_on = <0x84000003>;
|
||||
system_reset = <0x84000009>;
|
||||
};
|
||||
|
||||
scu@faf00000 {
|
||||
compatible = "arm,cortex-a9-scu";
|
||||
reg = <0xfaf00000 0x58>;
|
||||
};
|
||||
|
||||
/* Main external clock driving CPU and peripherals */
|
||||
ext_clk: ext_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <50000000>;
|
||||
};
|
||||
|
||||
eth_phy_ref_clk: eth_phy_ref_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <125000000>;
|
||||
};
|
||||
|
||||
clkctrl: clkctrl@0xf8000000 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "axis,artpec6-clkctrl";
|
||||
reg = <0xf8000000 0x48>;
|
||||
clocks = <&ext_clk>;
|
||||
clock-names = "sys_refclk";
|
||||
};
|
||||
|
||||
gtimer@faf00200 {
|
||||
compatible = "arm,cortex-a9-global-timer";
|
||||
reg = <0xfaf00200 0x20>;
|
||||
interrupts = <GIC_PPI 11 0xf01>;
|
||||
clocks = <&clkctrl 1>;
|
||||
};
|
||||
|
||||
timer@faf00600 {
|
||||
compatible = "arm,cortex-a9-twd-timer";
|
||||
reg = <0xfaf00600 0x20>;
|
||||
interrupts = <GIC_PPI 13 0xf04>;
|
||||
clocks = <&clkctrl 1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
intc: interrupt-controller@faf01000 {
|
||||
interrupt-controller;
|
||||
compatible = "arm,cortex-a9-gic";
|
||||
#interrupt-cells = <3>;
|
||||
reg = < 0xfaf01000 0x1000 >, < 0xfaf00100 0x0100 >;
|
||||
};
|
||||
|
||||
pl310: cache-controller@faf10000 {
|
||||
compatible = "arm,pl310-cache";
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
reg = <0xfaf10000 0x1000>;
|
||||
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
|
||||
arm,data-latency = <1 1 1>;
|
||||
arm,tag-latency = <1 1 1>;
|
||||
arm,filter-ranges = <0x0 0x80000000>;
|
||||
};
|
||||
|
||||
pmu {
|
||||
compatible = "arm,cortex-a9-pmu";
|
||||
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&intc>;
|
||||
};
|
||||
|
||||
amba@0 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x1>;
|
||||
interrupt-parent = <&intc>;
|
||||
ranges;
|
||||
dma-ranges = <0x80000000 0x00000000 0x40000000>;
|
||||
dma-coherent;
|
||||
|
||||
ethernet: ethernet@f8010000 {
|
||||
clock-names = "phy_ref_clk", "apb_pclk";
|
||||
clocks = <ð_phy_ref_clk>,
|
||||
<&clkctrl 4>;
|
||||
compatible = "snps,dwc-qos-ethernet-4.10";
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg = <0xf8010000 0x4000>;
|
||||
|
||||
snps,write-requests = <2>;
|
||||
snps,read-requests = <16>;
|
||||
snps,txpbl = <8>;
|
||||
snps,rxpbl = <2>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart0: serial@f8036000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0xf8036000 0x1000>;
|
||||
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clkctrl 13>,
|
||||
<&clkctrl 12>;
|
||||
clock-names = "uart_clk", "apb_pclk";
|
||||
status = "disabled";
|
||||
};
|
||||
uart1: serial@f8037000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0xf8037000 0x1000>;
|
||||
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clkctrl 13>,
|
||||
<&clkctrl 12>;
|
||||
clock-names = "uart_clk", "apb_pclk";
|
||||
status = "disabled";
|
||||
};
|
||||
uart2: serial@f8038000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0xf8038000 0x1000>;
|
||||
interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clkctrl 13>,
|
||||
<&clkctrl 12>;
|
||||
clock-names = "uart_clk", "apb_pclk";
|
||||
status = "disabled";
|
||||
};
|
||||
uart3: serial@f8039000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0xf8039000 0x1000>;
|
||||
interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clkctrl 13>,
|
||||
<&clkctrl 12>;
|
||||
clock-names = "uart_clk", "apb_pclk";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
25
sys/gnu/dts/arm/aspeed-ast2500-evb.dts
Normal file
25
sys/gnu/dts/arm/aspeed-ast2500-evb.dts
Normal file
@ -0,0 +1,25 @@
|
||||
/dts-v1/;
|
||||
|
||||
#include "aspeed-g5.dtsi"
|
||||
|
||||
/ {
|
||||
model = "AST2500 EVB";
|
||||
compatible = "aspeed,ast2500";
|
||||
|
||||
aliases {
|
||||
serial4 = &uart5;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = &uart5;
|
||||
bootargs = "console=ttyS4,115200 earlyprintk";
|
||||
};
|
||||
|
||||
memory {
|
||||
reg = <0x80000000 0x20000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&uart5 {
|
||||
status = "okay";
|
||||
};
|
||||
25
sys/gnu/dts/arm/aspeed-bmc-opp-palmetto.dts
Normal file
25
sys/gnu/dts/arm/aspeed-bmc-opp-palmetto.dts
Normal file
@ -0,0 +1,25 @@
|
||||
/dts-v1/;
|
||||
|
||||
#include "aspeed-g4.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Palmetto BMC";
|
||||
compatible = "tyan,palmetto-bmc", "aspeed,ast2400";
|
||||
|
||||
aliases {
|
||||
serial4 = &uart5;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = &uart5;
|
||||
bootargs = "console=ttyS4,38400 earlyprintk";
|
||||
};
|
||||
|
||||
memory {
|
||||
reg = <0x40000000 0x10000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&uart5 {
|
||||
status = "okay";
|
||||
};
|
||||
161
sys/gnu/dts/arm/aspeed-g4.dtsi
Normal file
161
sys/gnu/dts/arm/aspeed-g4.dtsi
Normal file
@ -0,0 +1,161 @@
|
||||
#include "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Aspeed BMC";
|
||||
compatible = "aspeed,ast2400";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
interrupt-parent = <&vic>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
compatible = "arm,arm926ej-s";
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
clocks {
|
||||
clk_clkin: clk_clkin {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <48000000>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
ahb {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
vic: interrupt-controller@1e6c0080 {
|
||||
compatible = "aspeed,ast2400-vic";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
valid-sources = <0xffffffff 0x0007ffff>;
|
||||
reg = <0x1e6c0080 0x80>;
|
||||
};
|
||||
|
||||
apb {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
clk_hpll: clk_hpll@1e6e2070 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "aspeed,g4-hpll-clock";
|
||||
reg = <0x1e6e2070 0x4>;
|
||||
clocks = <&clk_clkin>;
|
||||
};
|
||||
|
||||
clk_apb: clk_apb@1e6e2008 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "aspeed,g4-apb-clock";
|
||||
reg = <0x1e6e2008 0x4>;
|
||||
clocks = <&clk_hpll>;
|
||||
};
|
||||
|
||||
clk_uart: clk_uart@1e6e2008 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "aspeed,uart-clock";
|
||||
reg = <0x1e6e202c 0x4>;
|
||||
};
|
||||
|
||||
sram@1e720000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0x1e720000 0x8000>; // 32K
|
||||
};
|
||||
|
||||
timer: timer@1e782000 {
|
||||
compatible = "aspeed,ast2400-timer";
|
||||
reg = <0x1e782000 0x90>;
|
||||
// The moxart_timer driver registers only one
|
||||
// interrupt and assumes it's for timer 1
|
||||
//interrupts = <16 17 18 35 36 37 38 39>;
|
||||
interrupts = <16>;
|
||||
clocks = <&clk_apb>;
|
||||
};
|
||||
|
||||
wdt1: wdt@1e785000 {
|
||||
compatible = "aspeed,wdt";
|
||||
reg = <0x1e785000 0x1c>;
|
||||
interrupts = <27>;
|
||||
};
|
||||
|
||||
wdt2: wdt@1e785020 {
|
||||
compatible = "aspeed,wdt";
|
||||
reg = <0x1e785020 0x1c>;
|
||||
interrupts = <27>;
|
||||
clocks = <&clk_apb>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart1: serial@1e783000 {
|
||||
compatible = "ns16550a";
|
||||
reg = <0x1e783000 0x1000>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <9>;
|
||||
clocks = <&clk_uart>;
|
||||
no-loopback-test;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart2: serial@1e78d000 {
|
||||
compatible = "ns16550a";
|
||||
reg = <0x1e78d000 0x1000>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <32>;
|
||||
clocks = <&clk_uart>;
|
||||
no-loopback-test;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart3: serial@1e78e000 {
|
||||
compatible = "ns16550a";
|
||||
reg = <0x1e78e000 0x1000>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <33>;
|
||||
clocks = <&clk_uart>;
|
||||
no-loopback-test;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart4: serial@1e78f000 {
|
||||
compatible = "ns16550a";
|
||||
reg = <0x1e78f000 0x1000>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <34>;
|
||||
clocks = <&clk_uart>;
|
||||
no-loopback-test;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart5: serial@1e784000 {
|
||||
compatible = "ns16550a";
|
||||
reg = <0x1e784000 0x1000>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <10>;
|
||||
clocks = <&clk_uart>;
|
||||
current-speed = <38400>;
|
||||
no-loopback-test;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart6: serial@1e787000 {
|
||||
compatible = "ns16550a";
|
||||
reg = <0x1e787000 0x1000>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <10>;
|
||||
clocks = <&clk_uart>;
|
||||
no-loopback-test;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
170
sys/gnu/dts/arm/aspeed-g5.dtsi
Normal file
170
sys/gnu/dts/arm/aspeed-g5.dtsi
Normal file
@ -0,0 +1,170 @@
|
||||
#include "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Aspeed BMC";
|
||||
compatible = "aspeed,ast2500";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
interrupt-parent = <&vic>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
compatible = "arm,arm1176jzf-s";
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
ahb {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
vic: interrupt-controller@1e6c0080 {
|
||||
compatible = "aspeed,ast2400-vic";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
valid-sources = <0xfefff7ff 0x0807ffff>;
|
||||
reg = <0x1e6c0080 0x80>;
|
||||
};
|
||||
|
||||
apb {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
clk_clkin: clk_clkin@1e6e2070 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "aspeed,g5-clkin-clock";
|
||||
reg = <0x1e6e2070 0x04>;
|
||||
};
|
||||
|
||||
clk_hpll: clk_hpll@1e6e2024 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "aspeed,g5-hpll-clock";
|
||||
reg = <0x1e6e2024 0x4>;
|
||||
clocks = <&clk_clkin>;
|
||||
};
|
||||
|
||||
clk_ahb: clk_ahb@1e6e2070 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "aspeed,g5-ahb-clock";
|
||||
reg = <0x1e6e2070 0x4>;
|
||||
clocks = <&clk_hpll>;
|
||||
};
|
||||
|
||||
clk_apb: clk_apb@1e6e2008 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "aspeed,g5-apb-clock";
|
||||
reg = <0x1e6e2008 0x4>;
|
||||
clocks = <&clk_hpll>;
|
||||
};
|
||||
|
||||
clk_uart: clk_uart@1e6e2008 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "aspeed,uart-clock";
|
||||
reg = <0x1e6e202c 0x4>;
|
||||
};
|
||||
|
||||
sram@1e720000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0x1e720000 0x9000>; // 36K
|
||||
};
|
||||
|
||||
timer: timer@1e782000 {
|
||||
compatible = "aspeed,ast2400-timer";
|
||||
reg = <0x1e782000 0x90>;
|
||||
// The moxart_timer driver registers only one
|
||||
// interrupt and assumes it's for timer 1
|
||||
//interrupts = <16 17 18 35 36 37 38 39>;
|
||||
interrupts = <16>;
|
||||
clocks = <&clk_apb>;
|
||||
};
|
||||
|
||||
wdt1: wdt@1e785000 {
|
||||
compatible = "aspeed,wdt";
|
||||
reg = <0x1e785000 0x1c>;
|
||||
interrupts = <27>;
|
||||
};
|
||||
|
||||
wdt2: wdt@1e785020 {
|
||||
compatible = "aspeed,wdt";
|
||||
reg = <0x1e785020 0x1c>;
|
||||
interrupts = <27>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
wdt3: wdt@1e785040 {
|
||||
compatible = "aspeed,wdt";
|
||||
reg = <0x1e785074 0x1c>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart1: serial@1e783000 {
|
||||
compatible = "ns16550a";
|
||||
reg = <0x1e783000 0x1000>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <9>;
|
||||
clocks = <&clk_uart>;
|
||||
no-loopback-test;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart2: serial@1e78d000 {
|
||||
compatible = "ns16550a";
|
||||
reg = <0x1e78d000 0x1000>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <32>;
|
||||
clocks = <&clk_uart>;
|
||||
no-loopback-test;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart3: serial@1e78e000 {
|
||||
compatible = "ns16550a";
|
||||
reg = <0x1e78e000 0x1000>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <33>;
|
||||
clocks = <&clk_uart>;
|
||||
no-loopback-test;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart4: serial@1e78f000 {
|
||||
compatible = "ns16550a";
|
||||
reg = <0x1e78f000 0x1000>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <34>;
|
||||
clocks = <&clk_uart>;
|
||||
no-loopback-test;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart5: serial@1e784000 {
|
||||
compatible = "ns16550a";
|
||||
reg = <0x1e784000 0x1000>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <10>;
|
||||
clocks = <&clk_uart>;
|
||||
current-speed = <38400>;
|
||||
no-loopback-test;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart6: serial@1e787000 {
|
||||
compatible = "ns16550a";
|
||||
reg = <0x1e787000 0x1000>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <10>;
|
||||
clocks = <&clk_uart>;
|
||||
no-loopback-test;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -303,6 +303,7 @@
|
||||
regulator-name = "mmc0-card-supply";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
gpio_keys {
|
||||
|
||||
@ -978,7 +978,7 @@
|
||||
|
||||
trng@fffcc000 {
|
||||
compatible = "atmel,at91sam9g45-trng";
|
||||
reg = <0xfffcc000 0x4000>;
|
||||
reg = <0xfffcc000 0x100>;
|
||||
interrupts = <6 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
clocks = <&trng_clk>;
|
||||
};
|
||||
|
||||
@ -215,7 +215,7 @@
|
||||
};
|
||||
|
||||
panel: panel {
|
||||
compatible = "qd,qd43003c0-40", "simple-panel";
|
||||
compatible = "qiaodian,qd43003c0-40", "simple-panel";
|
||||
backlight = <&backlight>;
|
||||
power-supply = <&panel_reg>;
|
||||
#address-cells = <1>;
|
||||
|
||||
@ -106,7 +106,7 @@
|
||||
|
||||
pmc: pmc@fffffc00 {
|
||||
compatible = "atmel,at91sam9x5-pmc", "syscon";
|
||||
reg = <0xfffffc00 0x100>;
|
||||
reg = <0xfffffc00 0x200>;
|
||||
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
|
||||
interrupt-controller;
|
||||
#address-cells = <1>;
|
||||
|
||||
28
sys/gnu/dts/arm/bcm2835-rpi-a.dts
Normal file
28
sys/gnu/dts/arm/bcm2835-rpi-a.dts
Normal file
@ -0,0 +1,28 @@
|
||||
/dts-v1/;
|
||||
#include "bcm2835.dtsi"
|
||||
#include "bcm2835-rpi.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "raspberrypi,model-a", "brcm,bcm2835";
|
||||
model = "Raspberry Pi Model A";
|
||||
|
||||
leds {
|
||||
act {
|
||||
gpios = <&gpio 16 1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&gpio {
|
||||
pinctrl-0 = <&gpioout &alt0 &i2s_alt2 &alt3>;
|
||||
|
||||
/* I2S interface */
|
||||
i2s_alt2: i2s_alt2 {
|
||||
brcm,pins = <28 29 30 31>;
|
||||
brcm,function = <BCM2835_FSEL_ALT2>;
|
||||
};
|
||||
};
|
||||
|
||||
&hdmi {
|
||||
hpd-gpios = <&gpio 46 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
115
sys/gnu/dts/arm/bcm47094-dlink-dir-885l.dts
Normal file
115
sys/gnu/dts/arm/bcm47094-dlink-dir-885l.dts
Normal file
@ -0,0 +1,115 @@
|
||||
/*
|
||||
* Broadcom BCM470X / BCM5301X ARM platform code.
|
||||
* DTS for D-Link DIR-885L
|
||||
*
|
||||
* Copyright (C) 2016 Rafał Miłecki <zajec5@gmail.com>
|
||||
*
|
||||
* Licensed under the GNU/GPL. See COPYING for details.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "bcm4708.dtsi"
|
||||
#include "bcm5301x-nand-cs0-bch8.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "dlink,dir-885l", "brcm,bcm47094", "brcm,bcm4708";
|
||||
model = "D-Link DIR-885L";
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttyS0,115200 earlycon";
|
||||
};
|
||||
|
||||
memory {
|
||||
reg = <0x00000000 0x08000000>;
|
||||
};
|
||||
|
||||
nand: nand@18028000 {
|
||||
nandcs@0 {
|
||||
partition@0 {
|
||||
label = "firmware";
|
||||
reg = <0x00000000 0x08000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
power-white {
|
||||
label = "bcm53xx:white:power";
|
||||
gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>;
|
||||
linux,default-trigger = "default-on";
|
||||
};
|
||||
|
||||
wan-white {
|
||||
label = "bcm53xx:white:wan";
|
||||
gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>;
|
||||
linux,default-trigger = "default-off";
|
||||
};
|
||||
|
||||
power-amber {
|
||||
label = "bcm53xx:amber:power";
|
||||
gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>;
|
||||
linux,default-trigger = "default-off";
|
||||
};
|
||||
|
||||
wan-amber {
|
||||
label = "bcm53xx:amber:wan";
|
||||
gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>;
|
||||
linux,default-trigger = "default-off";
|
||||
};
|
||||
|
||||
usb3-white {
|
||||
label = "bcm53xx:white:usb3";
|
||||
gpios = <&chipcommon 8 GPIO_ACTIVE_LOW>;
|
||||
linux,default-trigger = "default-off";
|
||||
};
|
||||
|
||||
2ghz {
|
||||
label = "bcm53xx:white:2ghz";
|
||||
gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>;
|
||||
linux,default-trigger = "default-off";
|
||||
};
|
||||
|
||||
5ghz {
|
||||
label = "bcm53xx:white:5ghz";
|
||||
gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>;
|
||||
linux,default-trigger = "default-off";
|
||||
};
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
wps {
|
||||
label = "WPS";
|
||||
linux,code = <KEY_WPS_BUTTON>;
|
||||
gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
/* Switch: router / extender */
|
||||
extender {
|
||||
label = "Extender";
|
||||
linux,code = <BTN_0>;
|
||||
gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
restart {
|
||||
label = "Reset";
|
||||
linux,code = <KEY_RESTART>;
|
||||
gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
clock-frequency = <125000000>;
|
||||
};
|
||||
|
||||
&usb3 {
|
||||
vcc-gpio = <&chipcommon 18 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
27
sys/gnu/dts/arm/dra7-dspeve-thermal.dtsi
Normal file
27
sys/gnu/dts/arm/dra7-dspeve-thermal.dtsi
Normal file
@ -0,0 +1,27 @@
|
||||
/*
|
||||
* Device Tree Source for DRA7x SoC DSPEVE thermal
|
||||
*
|
||||
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public License
|
||||
* version 2. This program is licensed "as is" without any warranty of any
|
||||
* kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/thermal/thermal.h>
|
||||
|
||||
dspeve_thermal: dspeve_thermal {
|
||||
polling-delay-passive = <250>; /* milliseconds */
|
||||
polling-delay = <500>; /* milliseconds */
|
||||
|
||||
/* sensor ID */
|
||||
thermal-sensors = <&bandgap 3>;
|
||||
|
||||
trips {
|
||||
dspeve_crit: dspeve_crit {
|
||||
temperature = <125000>; /* milliCelsius */
|
||||
hysteresis = <2000>; /* milliCelsius */
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
};
|
||||
27
sys/gnu/dts/arm/dra7-iva-thermal.dtsi
Normal file
27
sys/gnu/dts/arm/dra7-iva-thermal.dtsi
Normal file
@ -0,0 +1,27 @@
|
||||
/*
|
||||
* Device Tree Source for DRA7x SoC IVA thermal
|
||||
*
|
||||
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public License
|
||||
* version 2. This program is licensed "as is" without any warranty of any
|
||||
* kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/thermal/thermal.h>
|
||||
|
||||
iva_thermal: iva_thermal {
|
||||
polling-delay-passive = <250>; /* milliseconds */
|
||||
polling-delay = <500>; /* milliseconds */
|
||||
|
||||
/* sensor ID */
|
||||
thermal-sensors = <&bandgap 4>;
|
||||
|
||||
trips {
|
||||
iva_crit: iva_crit {
|
||||
temperature = <125000>; /* milliCelsius */
|
||||
hysteresis = <2000>; /* milliCelsius */
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
};
|
||||
817
sys/gnu/dts/arm/dra72-evm-common.dtsi
Normal file
817
sys/gnu/dts/arm/dra72-evm-common.dtsi
Normal file
@ -0,0 +1,817 @@
|
||||
/*
|
||||
* Copyright (C) 2014-2016 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
/dts-v1/;
|
||||
|
||||
#include "dra72x.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/clk/ti-dra7-atl.h>
|
||||
|
||||
/ {
|
||||
compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7";
|
||||
|
||||
aliases {
|
||||
display0 = &hdmi0;
|
||||
};
|
||||
|
||||
evm_3v3: fixedregulator-evm_3v3 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "evm_3v3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
aic_dvdd: fixedregulator-aic_dvdd {
|
||||
/* TPS77018DBVT */
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "aic_dvdd";
|
||||
vin-supply = <&evm_3v3>;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
evm_3v3_sd: fixedregulator-sd {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "evm_3v3_sd";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
enable-active-high;
|
||||
gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
extcon_usb1: extcon_usb1 {
|
||||
compatible = "linux,extcon-usb-gpio";
|
||||
id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
extcon_usb2: extcon_usb2 {
|
||||
compatible = "linux,extcon-usb-gpio";
|
||||
id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
hdmi0: connector {
|
||||
compatible = "hdmi-connector";
|
||||
label = "hdmi";
|
||||
|
||||
type = "a";
|
||||
|
||||
port {
|
||||
hdmi_connector_in: endpoint {
|
||||
remote-endpoint = <&tpd12s015_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
tpd12s015: encoder {
|
||||
compatible = "ti,tpd12s015";
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&tpd12s015_pins>;
|
||||
|
||||
gpios = <&pcf_hdmi 4 GPIO_ACTIVE_HIGH>, /* P4, CT CP HPD */
|
||||
<&pcf_hdmi 5 GPIO_ACTIVE_HIGH>, /* P5, LS OE */
|
||||
<&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
tpd12s015_in: endpoint {
|
||||
remote-endpoint = <&hdmi_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
tpd12s015_out: endpoint {
|
||||
remote-endpoint = <&hdmi_connector_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
sound0: sound0 {
|
||||
compatible = "simple-audio-card";
|
||||
simple-audio-card,name = "DRA7xx-EVM";
|
||||
simple-audio-card,widgets =
|
||||
"Headphone", "Headphone Jack",
|
||||
"Line", "Line Out",
|
||||
"Microphone", "Mic Jack",
|
||||
"Line", "Line In";
|
||||
simple-audio-card,routing =
|
||||
"Headphone Jack", "HPLOUT",
|
||||
"Headphone Jack", "HPROUT",
|
||||
"Line Out", "LLOUT",
|
||||
"Line Out", "RLOUT",
|
||||
"MIC3L", "Mic Jack",
|
||||
"MIC3R", "Mic Jack",
|
||||
"Mic Jack", "Mic Bias",
|
||||
"LINE1L", "Line In",
|
||||
"LINE1R", "Line In";
|
||||
simple-audio-card,format = "dsp_b";
|
||||
simple-audio-card,bitclock-master = <&sound0_master>;
|
||||
simple-audio-card,frame-master = <&sound0_master>;
|
||||
simple-audio-card,bitclock-inversion;
|
||||
|
||||
sound0_master: simple-audio-card,cpu {
|
||||
sound-dai = <&mcasp3>;
|
||||
system-clock-frequency = <5644800>;
|
||||
};
|
||||
|
||||
simple-audio-card,codec {
|
||||
sound-dai = <&tlv320aic3106>;
|
||||
clocks = <&atl_clkin2_ck>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dra7_pmx_core {
|
||||
i2c1_pins: pinmux_i2c1_pins {
|
||||
pinctrl-single,pins = <
|
||||
DRA7XX_CORE_IOPAD(0x3800, PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */
|
||||
DRA7XX_CORE_IOPAD(0x3804, PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */
|
||||
>;
|
||||
};
|
||||
|
||||
i2c5_pins: pinmux_i2c5_pins {
|
||||
pinctrl-single,pins = <
|
||||
DRA7XX_CORE_IOPAD(0x36b4, PIN_INPUT | MUX_MODE10) /* mcasp1_axr0.i2c5_sda */
|
||||
DRA7XX_CORE_IOPAD(0x36b8, PIN_INPUT | MUX_MODE10) /* mcasp1_axr1.i2c5_scl */
|
||||
>;
|
||||
};
|
||||
|
||||
i2c5_pins: pinmux_i2c5_pins {
|
||||
pinctrl-single,pins = <
|
||||
DRA7XX_CORE_IOPAD(0x36b4, PIN_INPUT | MUX_MODE10) /* mcasp1_axr0.i2c5_sda */
|
||||
DRA7XX_CORE_IOPAD(0x36b8, PIN_INPUT | MUX_MODE10) /* mcasp1_axr1.i2c5_scl */
|
||||
>;
|
||||
};
|
||||
|
||||
nand_default: nand_default {
|
||||
pinctrl-single,pins = <
|
||||
DRA7XX_CORE_IOPAD(0x3400, PIN_INPUT | MUX_MODE0) /* gpmc_ad0 */
|
||||
DRA7XX_CORE_IOPAD(0x3404, PIN_INPUT | MUX_MODE0) /* gpmc_ad1 */
|
||||
DRA7XX_CORE_IOPAD(0x3408, PIN_INPUT | MUX_MODE0) /* gpmc_ad2 */
|
||||
DRA7XX_CORE_IOPAD(0x340c, PIN_INPUT | MUX_MODE0) /* gpmc_ad3 */
|
||||
DRA7XX_CORE_IOPAD(0x3410, PIN_INPUT | MUX_MODE0) /* gpmc_ad4 */
|
||||
DRA7XX_CORE_IOPAD(0x3414, PIN_INPUT | MUX_MODE0) /* gpmc_ad5 */
|
||||
DRA7XX_CORE_IOPAD(0x3418, PIN_INPUT | MUX_MODE0) /* gpmc_ad6 */
|
||||
DRA7XX_CORE_IOPAD(0x341c, PIN_INPUT | MUX_MODE0) /* gpmc_ad7 */
|
||||
DRA7XX_CORE_IOPAD(0x3420, PIN_INPUT | MUX_MODE0) /* gpmc_ad8 */
|
||||
DRA7XX_CORE_IOPAD(0x3424, PIN_INPUT | MUX_MODE0) /* gpmc_ad9 */
|
||||
DRA7XX_CORE_IOPAD(0x3428, PIN_INPUT | MUX_MODE0) /* gpmc_ad10 */
|
||||
DRA7XX_CORE_IOPAD(0x342c, PIN_INPUT | MUX_MODE0) /* gpmc_ad11 */
|
||||
DRA7XX_CORE_IOPAD(0x3430, PIN_INPUT | MUX_MODE0) /* gpmc_ad12 */
|
||||
DRA7XX_CORE_IOPAD(0x3434, PIN_INPUT | MUX_MODE0) /* gpmc_ad13 */
|
||||
DRA7XX_CORE_IOPAD(0x3438, PIN_INPUT | MUX_MODE0) /* gpmc_ad14 */
|
||||
DRA7XX_CORE_IOPAD(0x343c, PIN_INPUT | MUX_MODE0) /* gpmc_ad15 */
|
||||
DRA7XX_CORE_IOPAD(0x34b4, PIN_OUTPUT | MUX_MODE0) /* gpmc_cs0 */
|
||||
DRA7XX_CORE_IOPAD(0x34c4, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */
|
||||
DRA7XX_CORE_IOPAD(0x34cc, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */
|
||||
DRA7XX_CORE_IOPAD(0x34c8, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */
|
||||
DRA7XX_CORE_IOPAD(0x34d0, PIN_OUTPUT | MUX_MODE0) /* gpmc_ben0 */
|
||||
DRA7XX_CORE_IOPAD(0x34d8, PIN_INPUT | MUX_MODE0) /* gpmc_wait0 */
|
||||
>;
|
||||
};
|
||||
|
||||
usb1_pins: pinmux_usb1_pins {
|
||||
pinctrl-single,pins = <
|
||||
DRA7XX_CORE_IOPAD(0x3680, PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */
|
||||
>;
|
||||
};
|
||||
|
||||
usb2_pins: pinmux_usb2_pins {
|
||||
pinctrl-single,pins = <
|
||||
DRA7XX_CORE_IOPAD(0x3684, PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */
|
||||
>;
|
||||
};
|
||||
|
||||
tps65917_pins_default: tps65917_pins_default {
|
||||
pinctrl-single,pins = <
|
||||
DRA7XX_CORE_IOPAD(0x3824, PIN_INPUT_PULLUP | MUX_MODE1) /* wakeup3.sys_nirq1 */
|
||||
>;
|
||||
};
|
||||
|
||||
mmc1_pins_default: mmc1_pins_default {
|
||||
pinctrl-single,pins = <
|
||||
DRA7XX_CORE_IOPAD(0x376c, PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio219 */
|
||||
DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
|
||||
DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
|
||||
DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
|
||||
DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
|
||||
DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
|
||||
DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
|
||||
>;
|
||||
};
|
||||
|
||||
mmc2_pins_default: mmc2_pins_default {
|
||||
pinctrl-single,pins = <
|
||||
DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
|
||||
DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
|
||||
DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
|
||||
DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
|
||||
DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
|
||||
DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
|
||||
DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
|
||||
DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
|
||||
DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
|
||||
DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
|
||||
>;
|
||||
};
|
||||
|
||||
dcan1_pins_default: dcan1_pins_default {
|
||||
pinctrl-single,pins = <
|
||||
DRA7XX_CORE_IOPAD(0x37d0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
|
||||
DRA7XX_CORE_IOPAD(0x3818, PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */
|
||||
>;
|
||||
};
|
||||
|
||||
dcan1_pins_sleep: dcan1_pins_sleep {
|
||||
pinctrl-single,pins = <
|
||||
DRA7XX_CORE_IOPAD(0x37d0, MUX_MODE15 | PULL_UP) /* dcan1_tx.off */
|
||||
DRA7XX_CORE_IOPAD(0x3818, MUX_MODE15 | PULL_UP) /* wakeup0.off */
|
||||
>;
|
||||
};
|
||||
|
||||
hdmi_pins: pinmux_hdmi_pins {
|
||||
pinctrl-single,pins = <
|
||||
DRA7XX_CORE_IOPAD(0x3808, PIN_INPUT | MUX_MODE1) /* i2c2_sda.hdmi1_ddc_scl */
|
||||
DRA7XX_CORE_IOPAD(0x380c, PIN_INPUT | MUX_MODE1) /* i2c2_scl.hdmi1_ddc_sda */
|
||||
>;
|
||||
};
|
||||
|
||||
tpd12s015_pins: pinmux_tpd12s015_pins {
|
||||
pinctrl-single,pins = <
|
||||
DRA7XX_CORE_IOPAD(0x37b8, PIN_INPUT_PULLDOWN | MUX_MODE14) /* gpio7_12 HPD */
|
||||
>;
|
||||
};
|
||||
|
||||
atl_pins: pinmux_atl_pins {
|
||||
pinctrl-single,pins = <
|
||||
DRA7XX_CORE_IOPAD(0x3698, PIN_OUTPUT | MUX_MODE5) /* xref_clk1.atl_clk1 */
|
||||
DRA7XX_CORE_IOPAD(0x369c, PIN_OUTPUT | MUX_MODE5) /* xref_clk2.atl_clk2 */
|
||||
>;
|
||||
};
|
||||
|
||||
mcasp3_pins: pinmux_mcasp3_pins {
|
||||
pinctrl-single,pins = <
|
||||
DRA7XX_CORE_IOPAD(0x3724, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_aclkx */
|
||||
DRA7XX_CORE_IOPAD(0x3728, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_fsx */
|
||||
DRA7XX_CORE_IOPAD(0x372c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr0 */
|
||||
DRA7XX_CORE_IOPAD(0x3730, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr1 */
|
||||
>;
|
||||
};
|
||||
|
||||
mcasp3_sleep_pins: pinmux_mcasp3_sleep_pins {
|
||||
pinctrl-single,pins = <
|
||||
DRA7XX_CORE_IOPAD(0x3724, PIN_INPUT_PULLDOWN | MUX_MODE15)
|
||||
DRA7XX_CORE_IOPAD(0x3728, PIN_INPUT_PULLDOWN | MUX_MODE15)
|
||||
DRA7XX_CORE_IOPAD(0x372c, PIN_INPUT_PULLDOWN | MUX_MODE15)
|
||||
DRA7XX_CORE_IOPAD(0x3730, PIN_INPUT_PULLDOWN | MUX_MODE15)
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c1_pins>;
|
||||
clock-frequency = <400000>;
|
||||
|
||||
tps65917: tps65917@58 {
|
||||
compatible = "ti,tps65917";
|
||||
reg = <0x58>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&tps65917_pins_default>;
|
||||
|
||||
interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
ti,system-power-controller;
|
||||
|
||||
tps65917_pmic {
|
||||
compatible = "ti,tps65917-pmic";
|
||||
|
||||
tps65917_regulators: regulators {
|
||||
smps1_reg: smps1 {
|
||||
/* VDD_MPU */
|
||||
regulator-name = "smps1";
|
||||
regulator-min-microvolt = <850000>;
|
||||
regulator-max-microvolt = <1250000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
smps2_reg: smps2 {
|
||||
/* VDD_CORE */
|
||||
regulator-name = "smps2";
|
||||
regulator-min-microvolt = <850000>;
|
||||
regulator-max-microvolt = <1150000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
smps3_reg: smps3 {
|
||||
/* VDD_GPU IVA DSPEVE */
|
||||
regulator-name = "smps3";
|
||||
regulator-min-microvolt = <850000>;
|
||||
regulator-max-microvolt = <1250000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
smps4_reg: smps4 {
|
||||
/* VDDS1V8 */
|
||||
regulator-name = "smps4";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
smps5_reg: smps5 {
|
||||
/* VDD_DDR */
|
||||
regulator-name = "smps5";
|
||||
regulator-min-microvolt = <1350000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo1_reg: ldo1 {
|
||||
/* LDO1_OUT --> SDIO */
|
||||
regulator-name = "ldo1";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-allow-bypass;
|
||||
};
|
||||
|
||||
ldo3_reg: ldo3 {
|
||||
/* VDDA_1V8_PHY */
|
||||
regulator-name = "ldo3";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo5_reg: ldo5 {
|
||||
/* VDDA_1V8_PLL */
|
||||
regulator-name = "ldo5";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
ldo4_reg: ldo4 {
|
||||
/* VDDA_3V_USB: VDDA_USBHS33 */
|
||||
regulator-name = "ldo4";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
tps65917_power_button {
|
||||
compatible = "ti,palmas-pwrbutton";
|
||||
interrupt-parent = <&tps65917>;
|
||||
interrupts = <1 IRQ_TYPE_NONE>;
|
||||
wakeup-source;
|
||||
ti,palmas-long-press-seconds = <6>;
|
||||
};
|
||||
};
|
||||
|
||||
pcf_gpio_21: gpio@21 {
|
||||
compatible = "ti,pcf8575", "nxp,pcf8575";
|
||||
reg = <0x21>;
|
||||
lines-initial-states = <0x1408>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
tlv320aic3106: tlv320aic3106@19 {
|
||||
#sound-dai-cells = <0>;
|
||||
compatible = "ti,tlv320aic3106";
|
||||
reg = <0x19>;
|
||||
adc-settle-ms = <40>;
|
||||
ai3x-micbias-vg = <1>; /* 2.0V */
|
||||
status = "okay";
|
||||
|
||||
/* Regulators */
|
||||
AVDD-supply = <&evm_3v3>;
|
||||
IOVDD-supply = <&evm_3v3>;
|
||||
DRVDD-supply = <&evm_3v3>;
|
||||
DVDD-supply = <&aic_dvdd>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c5 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c5_pins>;
|
||||
clock-frequency = <400000>;
|
||||
|
||||
pcf_hdmi: pcf8575@26 {
|
||||
compatible = "ti,pcf8575", "nxp,pcf8575";
|
||||
reg = <0x26>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
/*
|
||||
* initial state is used here to keep the mdio interface
|
||||
* selected on RU89 through SEL_VIN4_MUX_S0, VIN2_S1 and
|
||||
* VIN2_S0 driven high otherwise Ethernet stops working
|
||||
* VIN6_SEL_S0 is low, thus selecting McASP3 over VIN6
|
||||
*/
|
||||
lines-initial-states = <0x0f2b>;
|
||||
|
||||
p1 {
|
||||
/* vin6_sel_s0: high: VIN6, low: audio */
|
||||
gpio-hog;
|
||||
gpios = <1 GPIO_ACTIVE_HIGH>;
|
||||
output-low;
|
||||
line-name = "vin6_sel_s0";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
status = "okay";
|
||||
interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&dra7_pmx_core 0x3e0>;
|
||||
};
|
||||
|
||||
&elm {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpmc {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&nand_default>;
|
||||
ranges = <0 0 0x08000000 0x01000000>; /* minimum GPMC partition = 16MB */
|
||||
nand@0,0 {
|
||||
/* To use NAND, DIP switch SW5 must be set like so:
|
||||
* SW5.1 (NAND_SELn) = ON (LOW)
|
||||
* SW5.9 (GPMC_WPN) = OFF (HIGH)
|
||||
*/
|
||||
compatible = "ti,omap2-nand";
|
||||
reg = <0 0 4>; /* device IO registers */
|
||||
interrupt-parent = <&gpmc>;
|
||||
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
|
||||
<1 IRQ_TYPE_NONE>; /* termcount */
|
||||
rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */
|
||||
ti,nand-ecc-opt = "bch8";
|
||||
ti,elm-id = <&elm>;
|
||||
nand-bus-width = <16>;
|
||||
gpmc,device-width = <2>;
|
||||
gpmc,sync-clk-ps = <0>;
|
||||
gpmc,cs-on-ns = <0>;
|
||||
gpmc,cs-rd-off-ns = <80>;
|
||||
gpmc,cs-wr-off-ns = <80>;
|
||||
gpmc,adv-on-ns = <0>;
|
||||
gpmc,adv-rd-off-ns = <60>;
|
||||
gpmc,adv-wr-off-ns = <60>;
|
||||
gpmc,we-on-ns = <10>;
|
||||
gpmc,we-off-ns = <50>;
|
||||
gpmc,oe-on-ns = <4>;
|
||||
gpmc,oe-off-ns = <40>;
|
||||
gpmc,access-ns = <40>;
|
||||
gpmc,wr-access-ns = <80>;
|
||||
gpmc,rd-cycle-ns = <80>;
|
||||
gpmc,wr-cycle-ns = <80>;
|
||||
gpmc,bus-turnaround-ns = <0>;
|
||||
gpmc,cycle2cycle-delay-ns = <0>;
|
||||
gpmc,clk-activation-ns = <0>;
|
||||
gpmc,wr-data-mux-bus-ns = <0>;
|
||||
/* MTD partition table */
|
||||
/* All SPL-* partitions are sized to minimal length
|
||||
* which can be independently programmable. For
|
||||
* NAND flash this is equal to size of erase-block */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
partition@0 {
|
||||
label = "NAND.SPL";
|
||||
reg = <0x00000000 0x000020000>;
|
||||
};
|
||||
partition@1 {
|
||||
label = "NAND.SPL.backup1";
|
||||
reg = <0x00020000 0x00020000>;
|
||||
};
|
||||
partition@2 {
|
||||
label = "NAND.SPL.backup2";
|
||||
reg = <0x00040000 0x00020000>;
|
||||
};
|
||||
partition@3 {
|
||||
label = "NAND.SPL.backup3";
|
||||
reg = <0x00060000 0x00020000>;
|
||||
};
|
||||
partition@4 {
|
||||
label = "NAND.u-boot-spl-os";
|
||||
reg = <0x00080000 0x00040000>;
|
||||
};
|
||||
partition@5 {
|
||||
label = "NAND.u-boot";
|
||||
reg = <0x000c0000 0x00100000>;
|
||||
};
|
||||
partition@6 {
|
||||
label = "NAND.u-boot-env";
|
||||
reg = <0x001c0000 0x00020000>;
|
||||
};
|
||||
partition@7 {
|
||||
label = "NAND.u-boot-env.backup1";
|
||||
reg = <0x001e0000 0x00020000>;
|
||||
};
|
||||
partition@8 {
|
||||
label = "NAND.kernel";
|
||||
reg = <0x00200000 0x00800000>;
|
||||
};
|
||||
partition@9 {
|
||||
label = "NAND.file-system";
|
||||
reg = <0x00a00000 0x0f600000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&usb2_phy1 {
|
||||
phy-supply = <&ldo4_reg>;
|
||||
};
|
||||
|
||||
&usb2_phy2 {
|
||||
phy-supply = <&ldo4_reg>;
|
||||
};
|
||||
|
||||
&omap_dwc3_1 {
|
||||
extcon = <&extcon_usb1>;
|
||||
};
|
||||
|
||||
&omap_dwc3_2 {
|
||||
extcon = <&extcon_usb2>;
|
||||
};
|
||||
|
||||
&usb1 {
|
||||
dr_mode = "peripheral";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&usb1_pins>;
|
||||
};
|
||||
|
||||
&usb2 {
|
||||
dr_mode = "host";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&usb2_pins>;
|
||||
};
|
||||
|
||||
&mmc1 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mmc1_pins_default>;
|
||||
vmmc-supply = <&evm_3v3_sd>;
|
||||
vmmc_aux-supply = <&ldo1_reg>;
|
||||
bus-width = <4>;
|
||||
/*
|
||||
* SDCD signal is not being used here - using the fact that GPIO mode
|
||||
* is a viable alternative
|
||||
*/
|
||||
cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;
|
||||
max-frequency = <192000000>;
|
||||
};
|
||||
|
||||
&mmc2 {
|
||||
/* SW5-3 in ON position */
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mmc2_pins_default>;
|
||||
|
||||
vmmc-supply = <&evm_3v3>;
|
||||
bus-width = <8>;
|
||||
ti,non-removable;
|
||||
max-frequency = <192000000>;
|
||||
};
|
||||
|
||||
&dra7_pmx_core {
|
||||
cpsw_default: cpsw_default {
|
||||
pinctrl-single,pins = <
|
||||
/* Slave 2 */
|
||||
DRA7XX_CORE_IOPAD(0x3598, PIN_OUTPUT | MUX_MODE3) /* vin2a_d12.rgmii1_txc */
|
||||
DRA7XX_CORE_IOPAD(0x359c, PIN_OUTPUT | MUX_MODE3) /* vin2a_d13.rgmii1_tctl */
|
||||
DRA7XX_CORE_IOPAD(0x35a0, PIN_OUTPUT | MUX_MODE3) /* vin2a_d14.rgmii1_td3 */
|
||||
DRA7XX_CORE_IOPAD(0x35a4, PIN_OUTPUT | MUX_MODE3) /* vin2a_d15.rgmii1_td2 */
|
||||
DRA7XX_CORE_IOPAD(0x35a8, PIN_OUTPUT | MUX_MODE3) /* vin2a_d16.rgmii1_td1 */
|
||||
DRA7XX_CORE_IOPAD(0x35ac, PIN_OUTPUT | MUX_MODE3) /* vin2a_d17.rgmii1_td0 */
|
||||
DRA7XX_CORE_IOPAD(0x35b0, PIN_INPUT | MUX_MODE3) /* vin2a_d18.rgmii1_rclk */
|
||||
DRA7XX_CORE_IOPAD(0x35b4, PIN_INPUT | MUX_MODE3) /* vin2a_d19.rgmii1_rctl */
|
||||
DRA7XX_CORE_IOPAD(0x35b8, PIN_INPUT | MUX_MODE3) /* vin2a_d20.rgmii1_rd3 */
|
||||
DRA7XX_CORE_IOPAD(0x35bc, PIN_INPUT | MUX_MODE3) /* vin2a_d21.rgmii1_rd2 */
|
||||
DRA7XX_CORE_IOPAD(0x35c0, PIN_INPUT | MUX_MODE3) /* vin2a_d22.rgmii1_rd1 */
|
||||
DRA7XX_CORE_IOPAD(0x35c4, PIN_INPUT | MUX_MODE3) /* vin2a_d23.rgmii1_rd0 */
|
||||
>;
|
||||
|
||||
};
|
||||
|
||||
cpsw_sleep: cpsw_sleep {
|
||||
pinctrl-single,pins = <
|
||||
/* Slave 2 */
|
||||
DRA7XX_CORE_IOPAD(0x3598, MUX_MODE15)
|
||||
DRA7XX_CORE_IOPAD(0x359c, MUX_MODE15)
|
||||
DRA7XX_CORE_IOPAD(0x35a0, MUX_MODE15)
|
||||
DRA7XX_CORE_IOPAD(0x35a4, MUX_MODE15)
|
||||
DRA7XX_CORE_IOPAD(0x35a8, MUX_MODE15)
|
||||
DRA7XX_CORE_IOPAD(0x35ac, MUX_MODE15)
|
||||
DRA7XX_CORE_IOPAD(0x35b0, MUX_MODE15)
|
||||
DRA7XX_CORE_IOPAD(0x35b4, MUX_MODE15)
|
||||
DRA7XX_CORE_IOPAD(0x35b8, MUX_MODE15)
|
||||
DRA7XX_CORE_IOPAD(0x35bc, MUX_MODE15)
|
||||
DRA7XX_CORE_IOPAD(0x35c0, MUX_MODE15)
|
||||
DRA7XX_CORE_IOPAD(0x35c4, MUX_MODE15)
|
||||
>;
|
||||
};
|
||||
|
||||
davinci_mdio_default: davinci_mdio_default {
|
||||
pinctrl-single,pins = <
|
||||
/* MDIO */
|
||||
DRA7XX_CORE_IOPAD(0x363c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_d.mdio_d */
|
||||
DRA7XX_CORE_IOPAD(0x3640, PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
|
||||
>;
|
||||
};
|
||||
|
||||
davinci_mdio_sleep: davinci_mdio_sleep {
|
||||
pinctrl-single,pins = <
|
||||
DRA7XX_CORE_IOPAD(0x363c, MUX_MODE15)
|
||||
DRA7XX_CORE_IOPAD(0x3640, MUX_MODE15)
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&mac {
|
||||
status = "okay";
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&cpsw_default>;
|
||||
pinctrl-1 = <&cpsw_sleep>;
|
||||
};
|
||||
|
||||
&davinci_mdio {
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&davinci_mdio_default>;
|
||||
pinctrl-1 = <&davinci_mdio_sleep>;
|
||||
};
|
||||
|
||||
&dcan1 {
|
||||
status = "ok";
|
||||
pinctrl-names = "default", "sleep", "active";
|
||||
pinctrl-0 = <&dcan1_pins_sleep>;
|
||||
pinctrl-1 = <&dcan1_pins_sleep>;
|
||||
pinctrl-2 = <&dcan1_pins_default>;
|
||||
};
|
||||
|
||||
&qspi {
|
||||
status = "okay";
|
||||
|
||||
spi-max-frequency = <64000000>;
|
||||
m25p80@0 {
|
||||
compatible = "s25fl256s1";
|
||||
spi-max-frequency = <64000000>;
|
||||
reg = <0>;
|
||||
spi-tx-bus-width = <1>;
|
||||
spi-rx-bus-width = <4>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
/* MTD partition table.
|
||||
* The ROM checks the first four physical blocks
|
||||
* for a valid file to boot and the flash here is
|
||||
* 64KiB block size.
|
||||
*/
|
||||
partition@0 {
|
||||
label = "QSPI.SPL";
|
||||
reg = <0x00000000 0x000010000>;
|
||||
};
|
||||
partition@1 {
|
||||
label = "QSPI.SPL.backup1";
|
||||
reg = <0x00010000 0x00010000>;
|
||||
};
|
||||
partition@2 {
|
||||
label = "QSPI.SPL.backup2";
|
||||
reg = <0x00020000 0x00010000>;
|
||||
};
|
||||
partition@3 {
|
||||
label = "QSPI.SPL.backup3";
|
||||
reg = <0x00030000 0x00010000>;
|
||||
};
|
||||
partition@4 {
|
||||
label = "QSPI.u-boot";
|
||||
reg = <0x00040000 0x00100000>;
|
||||
};
|
||||
partition@5 {
|
||||
label = "QSPI.u-boot-spl-os";
|
||||
reg = <0x00140000 0x00080000>;
|
||||
};
|
||||
partition@6 {
|
||||
label = "QSPI.u-boot-env";
|
||||
reg = <0x001c0000 0x00010000>;
|
||||
};
|
||||
partition@7 {
|
||||
label = "QSPI.u-boot-env.backup1";
|
||||
reg = <0x001d0000 0x0010000>;
|
||||
};
|
||||
partition@8 {
|
||||
label = "QSPI.kernel";
|
||||
reg = <0x001e0000 0x0800000>;
|
||||
};
|
||||
partition@9 {
|
||||
label = "QSPI.file-system";
|
||||
reg = <0x009e0000 0x01620000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dss {
|
||||
status = "ok";
|
||||
|
||||
vdda_video-supply = <&ldo5_reg>;
|
||||
};
|
||||
|
||||
&hdmi {
|
||||
status = "ok";
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&hdmi_pins>;
|
||||
|
||||
port {
|
||||
hdmi_out: endpoint {
|
||||
remote-endpoint = <&tpd12s015_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&atl {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&atl_pins>;
|
||||
|
||||
assigned-clocks = <&abe_dpll_sys_clk_mux>,
|
||||
<&atl_gfclk_mux>,
|
||||
<&dpll_abe_ck>,
|
||||
<&dpll_abe_m2x2_ck>,
|
||||
<&atl_clkin2_ck>;
|
||||
assigned-clock-parents = <&sys_clkin2>, <&dpll_abe_m2_ck>;
|
||||
assigned-clock-rates = <0>, <0>, <180633600>, <361267200>, <5644800>;
|
||||
|
||||
status = "okay";
|
||||
|
||||
atl2 {
|
||||
bws = <DRA7_ATL_WS_MCASP2_FSX>;
|
||||
aws = <DRA7_ATL_WS_MCASP3_FSX>;
|
||||
};
|
||||
};
|
||||
|
||||
&mcasp3 {
|
||||
#sound-dai-cells = <0>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&mcasp3_pins>;
|
||||
pinctrl-1 = <&mcasp3_sleep_pins>;
|
||||
|
||||
assigned-clocks = <&mcasp3_ahclkx_mux>;
|
||||
assigned-clock-parents = <&atl_clkin2_ck>;
|
||||
|
||||
status = "okay";
|
||||
|
||||
op-mode = <0>; /* MCASP_IIS_MODE */
|
||||
tdm-slots = <2>;
|
||||
/* 4 serializer */
|
||||
serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
|
||||
1 2 0 0
|
||||
>;
|
||||
tx-num-evt = <32>;
|
||||
rx-num-evt = <32>;
|
||||
};
|
||||
|
||||
&mailbox5 {
|
||||
status = "okay";
|
||||
mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
|
||||
status = "okay";
|
||||
};
|
||||
mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox6 {
|
||||
status = "okay";
|
||||
mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
73
sys/gnu/dts/arm/dra72-evm-revc.dts
Normal file
73
sys/gnu/dts/arm/dra72-evm-revc.dts
Normal file
@ -0,0 +1,73 @@
|
||||
/*
|
||||
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
#include "dra72-evm-common.dtsi"
|
||||
#include <dt-bindings/net/ti-dp83867.h>
|
||||
|
||||
/ {
|
||||
model = "TI DRA722 Rev C EVM";
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x80000000 0x0 0x80000000>; /* 2GB */
|
||||
};
|
||||
};
|
||||
|
||||
&tps65917_regulators {
|
||||
ldo2_reg: ldo2 {
|
||||
/* LDO2_OUT --> VDDA_1V8_PHY2 */
|
||||
regulator-name = "ldo2";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
};
|
||||
|
||||
&hdmi {
|
||||
vdda-supply = <&ldo2_reg>;
|
||||
};
|
||||
|
||||
&pcf_gpio_21 {
|
||||
interrupt-parent = <&gpio3>;
|
||||
interrupts = <30 IRQ_TYPE_EDGE_FALLING>;
|
||||
};
|
||||
|
||||
&mac {
|
||||
mode-gpios = <&pcf_gpio_21 4 GPIO_ACTIVE_LOW>,
|
||||
<&pcf_hdmi 9 GPIO_ACTIVE_LOW>, /* P11 */
|
||||
<&pcf_hdmi 10 GPIO_ACTIVE_LOW>; /* P12 */
|
||||
dual_emac;
|
||||
};
|
||||
|
||||
&cpsw_emac0 {
|
||||
phy_id = <&davinci_mdio>, <2>;
|
||||
phy-mode = "rgmii-id";
|
||||
dual_emac_res_vlan = <1>;
|
||||
};
|
||||
|
||||
&cpsw_emac1 {
|
||||
phy_id = <&davinci_mdio>, <3>;
|
||||
phy-mode = "rgmii-id";
|
||||
dual_emac_res_vlan = <2>;
|
||||
};
|
||||
|
||||
&davinci_mdio {
|
||||
dp83867_0: ethernet-phy@2 {
|
||||
reg = <2>;
|
||||
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
|
||||
ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_NS>;
|
||||
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
|
||||
};
|
||||
|
||||
dp83867_1: ethernet-phy@3 {
|
||||
reg = <3>;
|
||||
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
|
||||
ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_NS>;
|
||||
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
|
||||
};
|
||||
};
|
||||
27
sys/gnu/dts/arm/exynos-syscon-restart.dtsi
Normal file
27
sys/gnu/dts/arm/exynos-syscon-restart.dtsi
Normal file
@ -0,0 +1,27 @@
|
||||
/*
|
||||
* Samsung's Exynos SoC syscon reboot/poweroff nodes common definition.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/ {
|
||||
soc {
|
||||
compatible = "simple-bus";
|
||||
|
||||
poweroff: syscon-poweroff {
|
||||
compatible = "syscon-poweroff";
|
||||
regmap = <&pmu_system_controller>;
|
||||
offset = <0x330C>; /* PS_HOLD_CONTROL */
|
||||
mask = <0x5200>; /* reset value */
|
||||
};
|
||||
|
||||
reboot: syscon-reboot {
|
||||
compatible = "syscon-reboot";
|
||||
regmap = <&pmu_system_controller>;
|
||||
offset = <0x0400>; /* SWRESET */
|
||||
mask = <0x1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
43
sys/gnu/dts/arm/exynos3250-artik5-eval.dts
Normal file
43
sys/gnu/dts/arm/exynos3250-artik5-eval.dts
Normal file
@ -0,0 +1,43 @@
|
||||
/*
|
||||
* Samsung's Exynos3250 based ARTIK5 evaluation board device tree source
|
||||
*
|
||||
* Copyright (c) 2016 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* Device tree source file for Samsung's ARTIK5 evaluation board
|
||||
* which is based on Samsung Exynos3250 SoC.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "exynos3250-artik5.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Samsung ARTIK5 evaluation board";
|
||||
compatible = "samsung,artik5-eval", "samsung,artik5",
|
||||
"samsung,exynos3250", "samsung,exynos3";
|
||||
};
|
||||
|
||||
&mshc_2 {
|
||||
num-slots = <1>;
|
||||
cap-sd-highspeed;
|
||||
disable-wp;
|
||||
vqmmc-supply = <&ldo3_reg>;
|
||||
card-detect-delay = <200>;
|
||||
clock-frequency = <100000000>;
|
||||
clock-freq-min-max = <400000 100000000>;
|
||||
samsung,dw-mshc-ciu-div = <1>;
|
||||
samsung,dw-mshc-sdr-timing = <0 1>;
|
||||
samsung,dw-mshc-ddr-timing = <1 2>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sd2_cmd &sd2_clk &sd2_cd &sd2_bus1 &sd2_bus4>;
|
||||
bus-width = <4>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&serial_2 {
|
||||
status = "okay";
|
||||
};
|
||||
334
sys/gnu/dts/arm/exynos3250-artik5.dtsi
Normal file
334
sys/gnu/dts/arm/exynos3250-artik5.dtsi
Normal file
@ -0,0 +1,334 @@
|
||||
/*
|
||||
* Samsung's Exynos3250 based ARTIK5 module device tree source
|
||||
*
|
||||
* Copyright (c) 2016 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* Device tree source file for Samsung's ARTIK5 module which is based on
|
||||
* Samsung Exynos3250 SoC.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include "exynos3250.dtsi"
|
||||
#include <dt-bindings/clock/samsung,s2mps11.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
/ {
|
||||
compatible = "samsung,artik5", "samsung,exynos3250", "samsung,exynos3";
|
||||
|
||||
chosen {
|
||||
stdout-path = &serial_2;
|
||||
};
|
||||
|
||||
memory {
|
||||
reg = <0x40000000 0x1ff00000>;
|
||||
};
|
||||
|
||||
firmware@0205f000 {
|
||||
compatible = "samsung,secure-firmware";
|
||||
reg = <0x0205f000 0x1000>;
|
||||
};
|
||||
|
||||
thermal-zones {
|
||||
cpu_thermal: cpu-thermal {
|
||||
cooling-maps {
|
||||
map0 {
|
||||
/* Corresponds to 500MHz */
|
||||
cooling-device = <&cpu0 5 5>;
|
||||
};
|
||||
map1 {
|
||||
/* Corresponds to 200MHz */
|
||||
cooling-device = <&cpu0 8 8>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&adc {
|
||||
vdd-supply = <&ldo7_reg>;
|
||||
assigned-clocks = <&cmu CLK_SCLK_TSADC>;
|
||||
assigned-clock-rates = <6000000>;
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
cpu0-supply = <&buck2_reg>;
|
||||
};
|
||||
|
||||
&i2c_0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
samsung,i2c-sda-delay = <100>;
|
||||
samsung,i2c-slave-addr = <0x10>;
|
||||
samsung,i2c-max-bus-freq = <100000>;
|
||||
status = "okay";
|
||||
|
||||
s2mps14_pmic@66 {
|
||||
compatible = "samsung,s2mps14-pmic";
|
||||
interrupt-parent = <&gpx3>;
|
||||
interrupts = <5 IRQ_TYPE_NONE>;
|
||||
reg = <0x66>;
|
||||
|
||||
s2mps14_osc: clocks {
|
||||
compatible = "samsung,s2mps14-clk";
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "s2mps14_ap", "unused",
|
||||
"s2mps14_bt";
|
||||
};
|
||||
|
||||
regulators {
|
||||
ldo1_reg: LDO1 {
|
||||
/* VDD_ALIVE15x */
|
||||
regulator-name = "VLDO1_1.0V";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo2_reg: LDO2 {
|
||||
/* VDDQM176 ~ VDDQM185 */
|
||||
regulator-name = "VLDO2_1.2V";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo3_reg: LDO3 {
|
||||
/*
|
||||
* VDD1_E106 ~ VDD1_E111
|
||||
* DVDD_RTC_AP, DVDD_MMC2_AP
|
||||
*/
|
||||
regulator-name = "VLDO3_1.8V";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo4_reg: LDO4 {
|
||||
/* AVDD_PLL1120 ~ AVDD_PLL11201 */
|
||||
regulator-name = "VLDO4_1.8V";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo5_reg: LDO5 {
|
||||
/* VDDI_PLL_ISO141 ~ VDDI_PLL_ISO142 */
|
||||
regulator-name = "VLDO5_1.0V";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo6_reg: LDO6 {
|
||||
/* VDD_USB, VDD10_HSIC */
|
||||
regulator-name = "VLDO6_1.0V";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo7_reg: LDO7 {
|
||||
/*
|
||||
* VDD18P, AVDD18_TS, AVDD18_HSIC, AVDD_PLL2,
|
||||
* AVDD_ADC, AVDD_ABB_0, M4S_VDD18
|
||||
*/
|
||||
regulator-name = "VLDO7_1.8V";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo8_reg: LDO8 {
|
||||
/* AVDD33_UOTG */
|
||||
regulator-name = "VLDO8_3.0V";
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo9_reg: LDO9 {
|
||||
/* VDDQ_E86 ~ VDDQ_E105*/
|
||||
regulator-name = "VLDO9_1.2V";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo10_reg: LDO10 {
|
||||
regulator-name = "VLDO10_1.0V";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
};
|
||||
|
||||
ldo11_reg: LDO11 {
|
||||
/* VDD74 ~ VDD75 */
|
||||
regulator-name = "VLDO11_1.8V";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
samsung,ext-control-gpios = <&gpk0 2 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
ldo12_reg: LDO12 {
|
||||
/* VDD72 ~ VDD73 */
|
||||
regulator-name = "VLDO12_2.8V";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
samsung,ext-control-gpios = <&gpk0 2 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
ldo13_reg: LDO13 {
|
||||
regulator-name = "VLDO13_2.8V";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
};
|
||||
|
||||
ldo14_reg: LDO14 {
|
||||
regulator-name = "VLDO14_2.7V";
|
||||
regulator-min-microvolt = <2700000>;
|
||||
regulator-max-microvolt = <2700000>;
|
||||
};
|
||||
|
||||
ldo15_reg: LDO15 {
|
||||
regulator-name = "VLDO_3.3V";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
ldo16_reg: LDO16 {
|
||||
regulator-name = "VLDO16_3.3V";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
ldo17_reg: LDO17 {
|
||||
regulator-name = "VLDO17_3.0V";
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
};
|
||||
|
||||
ldo18_reg: LDO18 {
|
||||
/* DVDD_MMC2_AP */
|
||||
regulator-name = "VLDO18_2.8V";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
};
|
||||
|
||||
ldo19_reg: LDO19 {
|
||||
regulator-name = "VLDO19_1.8V";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
ldo20_reg: LDO20 {
|
||||
regulator-name = "VLDO20_1.8V";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
ldo21_reg: LDO21 {
|
||||
regulator-name = "VLDO21_1.25V";
|
||||
regulator-min-microvolt = <1250000>;
|
||||
regulator-max-microvolt = <1250000>;
|
||||
};
|
||||
|
||||
ldo22_reg: LDO22 {
|
||||
regulator-name = "VLDO22_1.2V";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
};
|
||||
|
||||
ldo23_reg: LDO23 {
|
||||
/* Xi2c3_SDA/SCL, Xi2c7_SDA/SCL, WLAN_SDIO */
|
||||
regulator-name = "VLDO23_1.8V";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
ldo24_reg: LDO24 {
|
||||
regulator-name = "VLDO24_3.0V";
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
};
|
||||
|
||||
ldo25_reg: LDO25 {
|
||||
regulator-name = "VLDO25_3.0V";
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
};
|
||||
|
||||
buck1_reg: BUCK1 {
|
||||
/* VDD_MIF */
|
||||
regulator-name = "VBUCK1_1.0V";
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
buck2_reg: BUCK2 {
|
||||
/* VDD_CPU */
|
||||
regulator-name = "VBUCK2_1.2V";
|
||||
regulator-min-microvolt = <850000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
buck3_reg: BUCK3 {
|
||||
/* VDD_G3D */
|
||||
regulator-name = "VBUCK3_1.0V";
|
||||
regulator-min-microvolt = <850000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
buck4_reg: BUCK4 {
|
||||
regulator-name = "VBUCK4_1.95V";
|
||||
regulator-min-microvolt = <1950000>;
|
||||
regulator-max-microvolt = <1950000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
buck5_reg: BUCK5 {
|
||||
regulator-name = "VBUCK5_1.35V";
|
||||
regulator-min-microvolt = <1350000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&mshc_0 {
|
||||
num-slots = <1>;
|
||||
non-removable;
|
||||
cap-mmc-highspeed;
|
||||
card-detect-delay = <200>;
|
||||
vmmc-supply = <&ldo12_reg>;
|
||||
clock-frequency = <100000000>;
|
||||
clock-freq-min-max = <400000 100000000>;
|
||||
samsung,dw-mshc-ciu-div = <1>;
|
||||
samsung,dw-mshc-sdr-timing = <0 1>;
|
||||
samsung,dw-mshc-ddr-timing = <1 2>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>;
|
||||
bus-width = <8>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rtc {
|
||||
clocks = <&cmu CLK_RTC>, <&s2mps14_osc S2MPS11_CLK_AP>;
|
||||
clock-names = "rtc", "rtc_src";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&xusbxti {
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
50
sys/gnu/dts/arm/exynos4412-ppmu-common.dtsi
Normal file
50
sys/gnu/dts/arm/exynos4412-ppmu-common.dtsi
Normal file
@ -0,0 +1,50 @@
|
||||
/*
|
||||
* Device tree sources for Exynos4412 PPMU common device tree
|
||||
*
|
||||
* Copyright (C) 2015 Samsung Electronics
|
||||
* Author: Chanwoo Choi <cw00.choi@samsung.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
&ppmu_dmc0 {
|
||||
status = "okay";
|
||||
|
||||
events {
|
||||
ppmu_dmc0_3: ppmu-event3-dmc0 {
|
||||
event-name = "ppmu-event3-dmc0";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&ppmu_dmc1 {
|
||||
status = "okay";
|
||||
|
||||
events {
|
||||
ppmu_dmc1_3: ppmu-event3-dmc1 {
|
||||
event-name = "ppmu-event3-dmc1";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&ppmu_leftbus {
|
||||
status = "okay";
|
||||
|
||||
events {
|
||||
ppmu_leftbus_3: ppmu-event3-leftbus {
|
||||
event-name = "ppmu-event3-leftbus";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&ppmu_rightbus {
|
||||
status = "okay";
|
||||
|
||||
events {
|
||||
ppmu_rightbus_3: ppmu-event3-rightbus {
|
||||
event-name = "ppmu-event3-rightbus";
|
||||
};
|
||||
};
|
||||
};
|
||||
406
sys/gnu/dts/arm/exynos5410-pinctrl.dtsi
Normal file
406
sys/gnu/dts/arm/exynos5410-pinctrl.dtsi
Normal file
@ -0,0 +1,406 @@
|
||||
/*
|
||||
* Exynos5410 SoC pin-mux and pin-config device tree source
|
||||
*
|
||||
* Copyright (c) 2013 Hardkernel Co., Ltd.
|
||||
* http://www.hardkernel.com
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
&pinctrl_0 {
|
||||
gpa0: gpa0 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpa1: gpa1 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpa2: gpa2 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpb0: gpb0 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpb1: gpb1 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpb2: gpb2 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpb3: gpb3 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpc0: gpc0 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpc3: gpc3 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpc1: gpc1 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpc2: gpc2 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpm5: gpm5 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
gpd1: gpd1 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpe0: gpe0 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpe1: gpe1 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpf0: gpf0 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpf1: gpf1 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpg0: gpg0 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpg1: gpg1 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpg2: gpg2 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gph0: gph0 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gph1: gph1 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpm7: gpm7 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
gpy0: gpy0 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
gpy1: gpy1 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
gpy2: gpy2 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
gpy3: gpy3 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
gpy4: gpy4 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
gpy5: gpy5 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
gpy6: gpy6 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
gpy7: gpy7 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
gpx0: gpx0 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&combiner>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <23 0>,
|
||||
<24 0>,
|
||||
<25 0>,
|
||||
<25 1>,
|
||||
<26 0>,
|
||||
<26 1>,
|
||||
<27 0>,
|
||||
<27 1>;
|
||||
};
|
||||
|
||||
gpx1: gpx1 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&combiner>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <28 0>,
|
||||
<28 1>,
|
||||
<29 0>,
|
||||
<29 1>,
|
||||
<30 0>,
|
||||
<30 1>,
|
||||
<31 0>,
|
||||
<31 1>;
|
||||
};
|
||||
|
||||
gpx2: gpx2 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpx3: gpx3 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl_1 {
|
||||
gpj0: gpj0 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpj1: gpj1 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpj2: gpj2 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpj3: gpj3 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpj4: gpj4 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpk0: gpk0 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpk1: gpk1 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpk2: gpk2 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpk3: gpk3 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl_2 {
|
||||
gpv0: gpv0 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpv1: gpv1 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpv2: gpv2 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpv3: gpv3 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpv4: gpv4 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl_3 {
|
||||
gpz: gpz {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
};
|
||||
126
sys/gnu/dts/arm/exynos5420-cpus.dtsi
Normal file
126
sys/gnu/dts/arm/exynos5420-cpus.dtsi
Normal file
@ -0,0 +1,126 @@
|
||||
/*
|
||||
* SAMSUNG EXYNOS5420 SoC cpu device tree source
|
||||
*
|
||||
* Copyright (c) 2015 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* This file provides desired ordering for Exynos5420 and Exynos5800
|
||||
* boards: CPU[0123] being the A15.
|
||||
*
|
||||
* The Exynos5420, 5422 and 5800 actually share the same CPU configuration
|
||||
* but particular boards choose different booting order.
|
||||
*
|
||||
* Exynos5420 and Exynos5800 always boot from Cortex-A15. On Exynos5422
|
||||
* booting cluster (big or LITTLE) is chosen by IROM code by reading
|
||||
* the gpg2-1 GPIO. By default all Exynos5422 based boards choose booting
|
||||
* from the LITTLE: Cortex-A7.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/ {
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <0x0>;
|
||||
clocks = <&clock CLK_ARM_CLK>;
|
||||
clock-frequency = <1800000000>;
|
||||
cci-control-port = <&cci_control1>;
|
||||
operating-points-v2 = <&cluster_a15_opp_table>;
|
||||
cooling-min-level = <0>;
|
||||
cooling-max-level = <11>;
|
||||
#cooling-cells = <2>; /* min followed by max */
|
||||
};
|
||||
|
||||
cpu1: cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <0x1>;
|
||||
clock-frequency = <1800000000>;
|
||||
cci-control-port = <&cci_control1>;
|
||||
operating-points-v2 = <&cluster_a15_opp_table>;
|
||||
cooling-min-level = <0>;
|
||||
cooling-max-level = <11>;
|
||||
#cooling-cells = <2>; /* min followed by max */
|
||||
};
|
||||
|
||||
cpu2: cpu@2 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <0x2>;
|
||||
clock-frequency = <1800000000>;
|
||||
cci-control-port = <&cci_control1>;
|
||||
operating-points-v2 = <&cluster_a15_opp_table>;
|
||||
cooling-min-level = <0>;
|
||||
cooling-max-level = <11>;
|
||||
#cooling-cells = <2>; /* min followed by max */
|
||||
};
|
||||
|
||||
cpu3: cpu@3 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <0x3>;
|
||||
clock-frequency = <1800000000>;
|
||||
cci-control-port = <&cci_control1>;
|
||||
operating-points-v2 = <&cluster_a15_opp_table>;
|
||||
cooling-min-level = <0>;
|
||||
cooling-max-level = <11>;
|
||||
#cooling-cells = <2>; /* min followed by max */
|
||||
};
|
||||
|
||||
cpu4: cpu@100 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x100>;
|
||||
clocks = <&clock CLK_KFC_CLK>;
|
||||
clock-frequency = <1000000000>;
|
||||
cci-control-port = <&cci_control0>;
|
||||
operating-points-v2 = <&cluster_a7_opp_table>;
|
||||
cooling-min-level = <0>;
|
||||
cooling-max-level = <7>;
|
||||
#cooling-cells = <2>; /* min followed by max */
|
||||
};
|
||||
|
||||
cpu5: cpu@101 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x101>;
|
||||
clock-frequency = <1000000000>;
|
||||
cci-control-port = <&cci_control0>;
|
||||
operating-points-v2 = <&cluster_a7_opp_table>;
|
||||
cooling-min-level = <0>;
|
||||
cooling-max-level = <7>;
|
||||
#cooling-cells = <2>; /* min followed by max */
|
||||
};
|
||||
|
||||
cpu6: cpu@102 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x102>;
|
||||
clock-frequency = <1000000000>;
|
||||
cci-control-port = <&cci_control0>;
|
||||
operating-points-v2 = <&cluster_a7_opp_table>;
|
||||
cooling-min-level = <0>;
|
||||
cooling-max-level = <7>;
|
||||
#cooling-cells = <2>; /* min followed by max */
|
||||
};
|
||||
|
||||
cpu7: cpu@103 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x103>;
|
||||
clock-frequency = <1000000000>;
|
||||
cci-control-port = <&cci_control0>;
|
||||
operating-points-v2 = <&cluster_a7_opp_table>;
|
||||
cooling-min-level = <0>;
|
||||
cooling-max-level = <7>;
|
||||
#cooling-cells = <2>; /* min followed by max */
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -107,7 +107,7 @@
|
||||
label = "Power Button";
|
||||
gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
|
||||
linux,code = <KEY_POWER>;
|
||||
gpio-key,wakeup;
|
||||
wakeup-source;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
@ -156,7 +156,7 @@
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_esdhc2>;
|
||||
cap-sdio-irq;
|
||||
enable-sdio-wakeup;
|
||||
wakeup-source;
|
||||
keep-power-in-suspend;
|
||||
max-frequency = <50000000>;
|
||||
no-1-8-v;
|
||||
|
||||
@ -41,7 +41,7 @@
|
||||
label = "BP1";
|
||||
gpios = <&gpio3 31 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <256>;
|
||||
gpio-key,wakeup;
|
||||
wakeup-source;
|
||||
linux,input-type = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -69,21 +69,21 @@
|
||||
label = "Home";
|
||||
gpios = <&gpio5 10 0>;
|
||||
linux,code = <102>; /* KEY_HOME */
|
||||
gpio-key,wakeup;
|
||||
wakeup-source;
|
||||
};
|
||||
|
||||
back {
|
||||
label = "Back";
|
||||
gpios = <&gpio5 11 0>;
|
||||
linux,code = <158>; /* KEY_BACK */
|
||||
gpio-key,wakeup;
|
||||
wakeup-source;
|
||||
};
|
||||
|
||||
program {
|
||||
label = "Program";
|
||||
gpios = <&gpio5 12 0>;
|
||||
linux,code = <362>; /* KEY_PROGRAM */
|
||||
gpio-key,wakeup;
|
||||
wakeup-source;
|
||||
};
|
||||
|
||||
volume-up {
|
||||
|
||||
@ -84,6 +84,15 @@
|
||||
regulator-max-microvolt = <5000000>;
|
||||
gpio = <&gpio1 2 0>;
|
||||
};
|
||||
|
||||
reg_usb_otg_vbus: regulator@4 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <4>;
|
||||
regulator-name = "usb_otg_vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
gpio = <&gpio1 4 0>;
|
||||
};
|
||||
};
|
||||
|
||||
sound {
|
||||
@ -168,6 +177,12 @@
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usbotg: usbotggrp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_GPIO_4__GPIO1_4 0x000b0
|
||||
>;
|
||||
};
|
||||
|
||||
led_pin_gpio: led_gpio@0 {
|
||||
fsl,pins = <
|
||||
MX53_PAD_PATA_DATA8__GPIO2_8 0x80000000
|
||||
@ -351,6 +366,10 @@
|
||||
};
|
||||
|
||||
&usbotg {
|
||||
dr_mode = "peripheral";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usbotg>;
|
||||
dr_mode = "otg";
|
||||
vbus-supply = <®_usb_otg_vbus>;
|
||||
disable-over-current;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@ -59,22 +59,22 @@
|
||||
|
||||
power {
|
||||
label = "Power Button";
|
||||
gpios = <&gpio1 8 0>;
|
||||
linux,code = <116>; /* KEY_POWER */
|
||||
gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_POWER>;
|
||||
};
|
||||
|
||||
volume-up {
|
||||
label = "Volume Up";
|
||||
gpios = <&gpio2 14 0>;
|
||||
linux,code = <115>; /* KEY_VOLUMEUP */
|
||||
gpio-key,wakeup;
|
||||
gpios = <&gpio2 14 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_VOLUMEUP>;
|
||||
wakeup-source;
|
||||
};
|
||||
|
||||
volume-down {
|
||||
label = "Volume Down";
|
||||
gpios = <&gpio2 15 0>;
|
||||
linux,code = <114>; /* KEY_VOLUMEDOWN */
|
||||
gpio-key,wakeup;
|
||||
gpios = <&gpio2 15 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_VOLUMEDOWN>;
|
||||
wakeup-source;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
@ -231,7 +231,7 @@
|
||||
interrupts = <26 0>;
|
||||
gpios = <&gpio3 26 GPIO_ACTIVE_LOW>;
|
||||
ti,x-plate-ohms = <660>;
|
||||
linux,wakeup;
|
||||
wakeup-source;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
@ -101,7 +101,7 @@
|
||||
interrupt-parent = <&gpio3>;
|
||||
interrupts = <23 0>;
|
||||
wakeup-gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
|
||||
linux,wakeup;
|
||||
wakeup-source;
|
||||
};
|
||||
};
|
||||
|
||||
@ -126,7 +126,7 @@
|
||||
interrupt-parent = <&gpio3>;
|
||||
interrupts = <22 0>;
|
||||
wakeup-gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>;
|
||||
linux,wakeup;
|
||||
wakeup-source;
|
||||
};
|
||||
};
|
||||
|
||||
@ -183,13 +183,14 @@
|
||||
status = "okay";
|
||||
|
||||
lvds0: lvds-channel@0 {
|
||||
fsl,data-mapping = "jeida";
|
||||
fsl,data-width = <24>;
|
||||
fsl,data-mapping = "spwg";
|
||||
fsl,data-width = <18>;
|
||||
status = "okay";
|
||||
|
||||
display-timings {
|
||||
native-mode = <&lvds_timing0>;
|
||||
lvds_timing0: hsd100pxn1 {
|
||||
native-mode = <&lvds0_timing0>;
|
||||
|
||||
lvds0_timing0: hsd100pxn1 {
|
||||
clock-frequency = <65000000>;
|
||||
hactive = <1024>;
|
||||
vactive = <768>;
|
||||
@ -202,19 +203,36 @@
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <0>;
|
||||
pixelclk-active = <1>;
|
||||
};
|
||||
|
||||
lvds0_timing1: nl12880bc20 {
|
||||
clock-frequency = <71000000>;
|
||||
hactive = <1280>;
|
||||
vactive = <800>;
|
||||
hback-porch = <50>;
|
||||
hsync-len = <60>;
|
||||
hfront-porch = <50>;
|
||||
vback-porch = <5>;
|
||||
vsync-len = <13>;
|
||||
vfront-porch = <5>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
lvds1: lvds-channel@1 {
|
||||
fsl,data-mapping = "jeida";
|
||||
fsl,data-width = <24>;
|
||||
fsl,data-mapping = "spwg";
|
||||
fsl,data-width = <18>;
|
||||
status = "okay";
|
||||
|
||||
display-timings {
|
||||
native-mode = <&lvds_timing1>;
|
||||
lvds_timing1: hsd100pxn1 {
|
||||
native-mode = <&lvds1_timing0>;
|
||||
|
||||
lvds1_timing0: hsd100pxn1 {
|
||||
clock-frequency = <65000000>;
|
||||
hactive = <1024>;
|
||||
vactive = <768>;
|
||||
@ -227,7 +245,7 @@
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <0>;
|
||||
pixelclk-active = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -37,7 +37,7 @@
|
||||
compatible = "fixed-clock";
|
||||
reg = <0>;
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <27000000>;
|
||||
clock-frequency = <26000000>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -50,7 +50,7 @@
|
||||
label = "Power Button";
|
||||
gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>;
|
||||
linux,code = <116>; /* KEY_POWER */
|
||||
gpio-key,wakeup;
|
||||
wakeup-source;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
@ -114,7 +114,7 @@
|
||||
codec: sgtl5000@0a {
|
||||
compatible = "fsl,sgtl5000";
|
||||
reg = <0x0a>;
|
||||
clocks = <&clks 201>;
|
||||
clocks = <&clks IMX6QDL_CLK_CKO>;
|
||||
VDDA-supply = <®_2p5v>;
|
||||
VDDIO-supply = <®_3p3v>;
|
||||
};
|
||||
|
||||
@ -1,12 +1,42 @@
|
||||
/*
|
||||
* Copyright 2014 Lothar Waßmann <LW@KARO-electronics.de>
|
||||
* Copyright 2014-2016 Lothar Waßmann <LW@KARO-electronics.de>
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 at the following locations:
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
237
sys/gnu/dts/arm/imx6dl-tx6s-8034.dts
Normal file
237
sys/gnu/dts/arm/imx6dl-tx6s-8034.dts
Normal file
@ -0,0 +1,237 @@
|
||||
/*
|
||||
* Copyright 2015-2016 Lothar Waßmann <LW@KARO-electronics.de>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "imx6dl.dtsi"
|
||||
#include "imx6qdl-tx6.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Ka-Ro electronics TX6S-8034 Module";
|
||||
compatible = "karo,imx6dl-tx6dl", "fsl,imx6dl";
|
||||
|
||||
aliases {
|
||||
display = &display;
|
||||
ipu1 = &ipu1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
/delete-node/ cpu@1;
|
||||
};
|
||||
|
||||
backlight: backlight {
|
||||
compatible = "pwm-backlight";
|
||||
pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_lcd0_pwr>;
|
||||
enable-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>;
|
||||
power-supply = <®_lcd1_pwr>;
|
||||
/*
|
||||
* a poor man's way to create a 1:1 relationship between
|
||||
* the PWM value and the actual duty cycle
|
||||
*/
|
||||
brightness-levels = < 0 1 2 3 4 5 6 7 8 9
|
||||
10 11 12 13 14 15 16 17 18 19
|
||||
20 21 22 23 24 25 26 27 28 29
|
||||
30 31 32 33 34 35 36 37 38 39
|
||||
40 41 42 43 44 45 46 47 48 49
|
||||
50 51 52 53 54 55 56 57 58 59
|
||||
60 61 62 63 64 65 66 67 68 69
|
||||
70 71 72 73 74 75 76 77 78 79
|
||||
80 81 82 83 84 85 86 87 88 89
|
||||
90 91 92 93 94 95 96 97 98 99
|
||||
100>;
|
||||
default-brightness-level = <50>;
|
||||
};
|
||||
|
||||
display: display@di0 {
|
||||
compatible = "fsl,imx-parallel-display";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_disp0_2>;
|
||||
interface-pix-fmt = "rgb24";
|
||||
status = "okay";
|
||||
|
||||
port {
|
||||
display0_in: endpoint {
|
||||
remote-endpoint = <&ipu1_di0_disp0>;
|
||||
};
|
||||
};
|
||||
|
||||
display-timings {
|
||||
native-mode = <&vga>;
|
||||
|
||||
vga: VGA {
|
||||
clock-frequency = <25200000>;
|
||||
hactive = <640>;
|
||||
vactive = <480>;
|
||||
hback-porch = <48>;
|
||||
hsync-len = <96>;
|
||||
hfront-porch = <16>;
|
||||
vback-porch = <31>;
|
||||
vsync-len = <2>;
|
||||
vfront-porch = <12>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <0>;
|
||||
};
|
||||
|
||||
ETV570 {
|
||||
clock-frequency = <25200000>;
|
||||
hactive = <640>;
|
||||
vactive = <480>;
|
||||
hback-porch = <114>;
|
||||
hsync-len = <30>;
|
||||
hfront-porch = <16>;
|
||||
vback-porch = <32>;
|
||||
vsync-len = <3>;
|
||||
vfront-porch = <10>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <0>;
|
||||
};
|
||||
|
||||
ET0350 {
|
||||
clock-frequency = <6413760>;
|
||||
hactive = <320>;
|
||||
vactive = <240>;
|
||||
hback-porch = <34>;
|
||||
hsync-len = <34>;
|
||||
hfront-porch = <20>;
|
||||
vback-porch = <15>;
|
||||
vsync-len = <3>;
|
||||
vfront-porch = <4>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <0>;
|
||||
};
|
||||
|
||||
ET0430 {
|
||||
clock-frequency = <9009000>;
|
||||
hactive = <480>;
|
||||
vactive = <272>;
|
||||
hback-porch = <2>;
|
||||
hsync-len = <41>;
|
||||
hfront-porch = <2>;
|
||||
vback-porch = <2>;
|
||||
vsync-len = <10>;
|
||||
vfront-porch = <2>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <1>;
|
||||
};
|
||||
|
||||
ET0500 {
|
||||
clock-frequency = <33264000>;
|
||||
hactive = <800>;
|
||||
vactive = <480>;
|
||||
hback-porch = <88>;
|
||||
hsync-len = <128>;
|
||||
hfront-porch = <40>;
|
||||
vback-porch = <33>;
|
||||
vsync-len = <2>;
|
||||
vfront-porch = <10>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <0>;
|
||||
};
|
||||
|
||||
ET0700 { /* same as ET0500 */
|
||||
clock-frequency = <33264000>;
|
||||
hactive = <800>;
|
||||
vactive = <480>;
|
||||
hback-porch = <88>;
|
||||
hsync-len = <128>;
|
||||
hfront-porch = <40>;
|
||||
vback-porch = <33>;
|
||||
vsync-len = <2>;
|
||||
vfront-porch = <10>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <0>;
|
||||
};
|
||||
|
||||
ETQ570 {
|
||||
clock-frequency = <6596040>;
|
||||
hactive = <320>;
|
||||
vactive = <240>;
|
||||
hback-porch = <38>;
|
||||
hsync-len = <30>;
|
||||
hfront-porch = <30>;
|
||||
vback-porch = <16>;
|
||||
vsync-len = <3>;
|
||||
vfront-porch = <4>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&ds1339 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&pinctrl_usdhc1 {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD1_CMD__SD1_CMD 0x070b1
|
||||
MX6QDL_PAD_SD1_CLK__SD1_CLK 0x070b1
|
||||
MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x070b1
|
||||
MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x070b1
|
||||
MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x070b1
|
||||
MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x070b1
|
||||
MX6QDL_PAD_SD3_CMD__GPIO7_IO02 0x170b0 /* SD1 CD */
|
||||
>;
|
||||
};
|
||||
|
||||
&ipu1_di0_disp0 {
|
||||
remote-endpoint = <&display0_in>;
|
||||
};
|
||||
|
||||
®_lcd0_pwr {
|
||||
status = "disabled";
|
||||
};
|
||||
253
sys/gnu/dts/arm/imx6dl-tx6s-8035.dts
Normal file
253
sys/gnu/dts/arm/imx6dl-tx6s-8035.dts
Normal file
@ -0,0 +1,253 @@
|
||||
/*
|
||||
* Copyright 2015-2016 Lothar Waßmann <LW@KARO-electronics.de>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "imx6dl.dtsi"
|
||||
#include "imx6qdl-tx6.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Ka-Ro electronics TX6S-8035 Module";
|
||||
compatible = "karo,imx6dl-tx6dl", "fsl,imx6dl";
|
||||
|
||||
aliases {
|
||||
display = &display;
|
||||
ipu1 = &ipu1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
/delete-node/ cpu@1;
|
||||
};
|
||||
|
||||
backlight: backlight {
|
||||
compatible = "pwm-backlight";
|
||||
pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_lcd0_pwr>;
|
||||
enable-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>;
|
||||
power-supply = <®_lcd1_pwr>;
|
||||
/*
|
||||
* a poor man's way to create a 1:1 relationship between
|
||||
* the PWM value and the actual duty cycle
|
||||
*/
|
||||
brightness-levels = < 0 1 2 3 4 5 6 7 8 9
|
||||
10 11 12 13 14 15 16 17 18 19
|
||||
20 21 22 23 24 25 26 27 28 29
|
||||
30 31 32 33 34 35 36 37 38 39
|
||||
40 41 42 43 44 45 46 47 48 49
|
||||
50 51 52 53 54 55 56 57 58 59
|
||||
60 61 62 63 64 65 66 67 68 69
|
||||
70 71 72 73 74 75 76 77 78 79
|
||||
80 81 82 83 84 85 86 87 88 89
|
||||
90 91 92 93 94 95 96 97 98 99
|
||||
100>;
|
||||
default-brightness-level = <50>;
|
||||
};
|
||||
|
||||
display: display@di0 {
|
||||
compatible = "fsl,imx-parallel-display";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_disp0_2>;
|
||||
interface-pix-fmt = "rgb24";
|
||||
status = "okay";
|
||||
|
||||
port {
|
||||
display0_in: endpoint {
|
||||
remote-endpoint = <&ipu1_di0_disp0>;
|
||||
};
|
||||
};
|
||||
|
||||
display-timings {
|
||||
native-mode = <&vga>;
|
||||
|
||||
vga: VGA {
|
||||
clock-frequency = <25200000>;
|
||||
hactive = <640>;
|
||||
vactive = <480>;
|
||||
hback-porch = <48>;
|
||||
hsync-len = <96>;
|
||||
hfront-porch = <16>;
|
||||
vback-porch = <31>;
|
||||
vsync-len = <2>;
|
||||
vfront-porch = <12>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <0>;
|
||||
};
|
||||
|
||||
ETV570 {
|
||||
clock-frequency = <25200000>;
|
||||
hactive = <640>;
|
||||
vactive = <480>;
|
||||
hback-porch = <114>;
|
||||
hsync-len = <30>;
|
||||
hfront-porch = <16>;
|
||||
vback-porch = <32>;
|
||||
vsync-len = <3>;
|
||||
vfront-porch = <10>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <0>;
|
||||
};
|
||||
|
||||
ET0350 {
|
||||
clock-frequency = <6413760>;
|
||||
hactive = <320>;
|
||||
vactive = <240>;
|
||||
hback-porch = <34>;
|
||||
hsync-len = <34>;
|
||||
hfront-porch = <20>;
|
||||
vback-porch = <15>;
|
||||
vsync-len = <3>;
|
||||
vfront-porch = <4>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <0>;
|
||||
};
|
||||
|
||||
ET0430 {
|
||||
clock-frequency = <9009000>;
|
||||
hactive = <480>;
|
||||
vactive = <272>;
|
||||
hback-porch = <2>;
|
||||
hsync-len = <41>;
|
||||
hfront-porch = <2>;
|
||||
vback-porch = <2>;
|
||||
vsync-len = <10>;
|
||||
vfront-porch = <2>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <1>;
|
||||
};
|
||||
|
||||
ET0500 {
|
||||
clock-frequency = <33264000>;
|
||||
hactive = <800>;
|
||||
vactive = <480>;
|
||||
hback-porch = <88>;
|
||||
hsync-len = <128>;
|
||||
hfront-porch = <40>;
|
||||
vback-porch = <33>;
|
||||
vsync-len = <2>;
|
||||
vfront-porch = <10>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <0>;
|
||||
};
|
||||
|
||||
ET0700 { /* same as ET0500 */
|
||||
clock-frequency = <33264000>;
|
||||
hactive = <800>;
|
||||
vactive = <480>;
|
||||
hback-porch = <88>;
|
||||
hsync-len = <128>;
|
||||
hfront-porch = <40>;
|
||||
vback-porch = <33>;
|
||||
vsync-len = <2>;
|
||||
vfront-porch = <10>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <0>;
|
||||
};
|
||||
|
||||
ETQ570 {
|
||||
clock-frequency = <6596040>;
|
||||
hactive = <320>;
|
||||
vactive = <240>;
|
||||
hback-porch = <38>;
|
||||
hsync-len = <30>;
|
||||
hfront-porch = <30>;
|
||||
vback-porch = <16>;
|
||||
vsync-len = <3>;
|
||||
vfront-porch = <4>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&ds1339 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&gpmi {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&ipu1_di0_disp0 {
|
||||
remote-endpoint = <&display0_in>;
|
||||
};
|
||||
|
||||
®_lcd0_pwr {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&usdhc4 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usdhc4>;
|
||||
bus-width = <4>;
|
||||
non-removable;
|
||||
no-1-8-v;
|
||||
fsl,wp-controller;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl_usdhc4: usdhc4grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD4_CMD__SD4_CMD 0x070b1
|
||||
MX6QDL_PAD_SD4_CLK__SD4_CLK 0x070b1
|
||||
MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x070b1
|
||||
MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x070b1
|
||||
MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x070b1
|
||||
MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x070b1
|
||||
MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x0b0b1
|
||||
>;
|
||||
};
|
||||
};
|
||||
@ -1,12 +1,42 @@
|
||||
/*
|
||||
* Copyright 2014 Lothar Waßmann <LW@KARO-electronics.de>
|
||||
* Copyright 2014-2016 Lothar Waßmann <LW@KARO-electronics.de>
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 at the following locations:
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
248
sys/gnu/dts/arm/imx6dl-tx6u-8033.dts
Normal file
248
sys/gnu/dts/arm/imx6dl-tx6u-8033.dts
Normal file
@ -0,0 +1,248 @@
|
||||
/*
|
||||
* Copyright 2014-2016 Lothar Waßmann <LW@KARO-electronics.de>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "imx6dl.dtsi"
|
||||
#include "imx6qdl-tx6.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Ka-Ro electronics TX6U-8033 Module";
|
||||
compatible = "karo,imx6dl-tx6dl", "fsl,imx6dl";
|
||||
|
||||
aliases {
|
||||
display = &display;
|
||||
};
|
||||
|
||||
backlight: backlight {
|
||||
compatible = "pwm-backlight";
|
||||
pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_lcd0_pwr>;
|
||||
enable-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>;
|
||||
power-supply = <®_lcd1_pwr>;
|
||||
/*
|
||||
* a poor man's way to create a 1:1 relationship between
|
||||
* the PWM value and the actual duty cycle
|
||||
*/
|
||||
brightness-levels = < 0 1 2 3 4 5 6 7 8 9
|
||||
10 11 12 13 14 15 16 17 18 19
|
||||
20 21 22 23 24 25 26 27 28 29
|
||||
30 31 32 33 34 35 36 37 38 39
|
||||
40 41 42 43 44 45 46 47 48 49
|
||||
50 51 52 53 54 55 56 57 58 59
|
||||
60 61 62 63 64 65 66 67 68 69
|
||||
70 71 72 73 74 75 76 77 78 79
|
||||
80 81 82 83 84 85 86 87 88 89
|
||||
90 91 92 93 94 95 96 97 98 99
|
||||
100>;
|
||||
default-brightness-level = <50>;
|
||||
};
|
||||
|
||||
display: display@di0 {
|
||||
compatible = "fsl,imx-parallel-display";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_disp0_2>;
|
||||
interface-pix-fmt = "rgb24";
|
||||
status = "okay";
|
||||
|
||||
port {
|
||||
display0_in: endpoint {
|
||||
remote-endpoint = <&ipu1_di0_disp0>;
|
||||
};
|
||||
};
|
||||
|
||||
display-timings {
|
||||
native-mode = <&vga>;
|
||||
|
||||
vga: VGA {
|
||||
clock-frequency = <25200000>;
|
||||
hactive = <640>;
|
||||
vactive = <480>;
|
||||
hback-porch = <48>;
|
||||
hsync-len = <96>;
|
||||
hfront-porch = <16>;
|
||||
vback-porch = <31>;
|
||||
vsync-len = <2>;
|
||||
vfront-porch = <12>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <0>;
|
||||
};
|
||||
|
||||
ETV570 {
|
||||
clock-frequency = <25200000>;
|
||||
hactive = <640>;
|
||||
vactive = <480>;
|
||||
hback-porch = <114>;
|
||||
hsync-len = <30>;
|
||||
hfront-porch = <16>;
|
||||
vback-porch = <32>;
|
||||
vsync-len = <3>;
|
||||
vfront-porch = <10>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <0>;
|
||||
};
|
||||
|
||||
ET0350 {
|
||||
clock-frequency = <6413760>;
|
||||
hactive = <320>;
|
||||
vactive = <240>;
|
||||
hback-porch = <34>;
|
||||
hsync-len = <34>;
|
||||
hfront-porch = <20>;
|
||||
vback-porch = <15>;
|
||||
vsync-len = <3>;
|
||||
vfront-porch = <4>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <0>;
|
||||
};
|
||||
|
||||
ET0430 {
|
||||
clock-frequency = <9009000>;
|
||||
hactive = <480>;
|
||||
vactive = <272>;
|
||||
hback-porch = <2>;
|
||||
hsync-len = <41>;
|
||||
hfront-porch = <2>;
|
||||
vback-porch = <2>;
|
||||
vsync-len = <10>;
|
||||
vfront-porch = <2>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <1>;
|
||||
};
|
||||
|
||||
ET0500 {
|
||||
clock-frequency = <33264000>;
|
||||
hactive = <800>;
|
||||
vactive = <480>;
|
||||
hback-porch = <88>;
|
||||
hsync-len = <128>;
|
||||
hfront-porch = <40>;
|
||||
vback-porch = <33>;
|
||||
vsync-len = <2>;
|
||||
vfront-porch = <10>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <0>;
|
||||
};
|
||||
|
||||
ET0700 { /* same as ET0500 */
|
||||
clock-frequency = <33264000>;
|
||||
hactive = <800>;
|
||||
vactive = <480>;
|
||||
hback-porch = <88>;
|
||||
hsync-len = <128>;
|
||||
hfront-porch = <40>;
|
||||
vback-porch = <33>;
|
||||
vsync-len = <2>;
|
||||
vfront-porch = <10>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <0>;
|
||||
};
|
||||
|
||||
ETQ570 {
|
||||
clock-frequency = <6596040>;
|
||||
hactive = <320>;
|
||||
vactive = <240>;
|
||||
hback-porch = <38>;
|
||||
hsync-len = <30>;
|
||||
hfront-porch = <30>;
|
||||
vback-porch = <16>;
|
||||
vsync-len = <3>;
|
||||
vfront-porch = <4>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&ds1339 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&gpmi {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&ipu1_di0_disp0 {
|
||||
remote-endpoint = <&display0_in>;
|
||||
};
|
||||
|
||||
®_lcd0_pwr {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&usdhc4 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usdhc4>;
|
||||
bus-width = <4>;
|
||||
non-removable;
|
||||
no-1-8-v;
|
||||
fsl,wp-controller;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl_usdhc4: usdhc4grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD4_CMD__SD4_CMD 0x070b1
|
||||
MX6QDL_PAD_SD4_CLK__SD4_CLK 0x070b1
|
||||
MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x070b1
|
||||
MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x070b1
|
||||
MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x070b1
|
||||
MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x070b1
|
||||
MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x0b0b1
|
||||
>;
|
||||
};
|
||||
};
|
||||
@ -1,12 +1,42 @@
|
||||
/*
|
||||
* Copyright 2014 Lothar Waßmann <LW@KARO-electronics.de>
|
||||
* Copyright 2014-2016 Lothar Waßmann <LW@KARO-electronics.de>
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 at the following locations:
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
@ -77,17 +107,7 @@
|
||||
interrupt-parent = <&gpio3>;
|
||||
interrupts = <22 0>;
|
||||
wakeup-gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>;
|
||||
linux,wakeup;
|
||||
};
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
imx6dl-tx6u-811x {
|
||||
pinctrl_eeti: eetigrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b1 /* Interrupt */
|
||||
>;
|
||||
};
|
||||
wakeup-source;
|
||||
};
|
||||
};
|
||||
|
||||
@ -148,3 +168,11 @@
|
||||
&pwm1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl_eeti: eetigrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b1 /* Interrupt */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
255
sys/gnu/dts/arm/imx6dl-tx6u-81xx-mb7.dts
Normal file
255
sys/gnu/dts/arm/imx6dl-tx6u-81xx-mb7.dts
Normal file
@ -0,0 +1,255 @@
|
||||
/*
|
||||
* Copyright 2016 Lothar Waßmann <LW@KARO-electronics.de>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "imx6dl.dtsi"
|
||||
#include "imx6qdl-tx6.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Ka-Ro electronics TX6U-81xx Module on MB7 baseboard";
|
||||
compatible = "karo,imx6dl-tx6dl", "fsl,imx6dl";
|
||||
|
||||
aliases {
|
||||
display = &lvds0;
|
||||
lvds0 = &lvds0;
|
||||
lvds1 = &lvds1;
|
||||
};
|
||||
|
||||
backlight0: backlight0 {
|
||||
compatible = "pwm-backlight";
|
||||
pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>;
|
||||
power-supply = <®_lcd0_pwr>;
|
||||
/*
|
||||
* a poor man's way to create a 1:1 relationship between
|
||||
* the PWM value and the actual duty cycle
|
||||
*/
|
||||
brightness-levels = < 0 1 2 3 4 5 6 7 8 9
|
||||
10 11 12 13 14 15 16 17 18 19
|
||||
20 21 22 23 24 25 26 27 28 29
|
||||
30 31 32 33 34 35 36 37 38 39
|
||||
40 41 42 43 44 45 46 47 48 49
|
||||
50 51 52 53 54 55 56 57 58 59
|
||||
60 61 62 63 64 65 66 67 68 69
|
||||
70 71 72 73 74 75 76 77 78 79
|
||||
80 81 82 83 84 85 86 87 88 89
|
||||
90 91 92 93 94 95 96 97 98 99
|
||||
100>;
|
||||
default-brightness-level = <50>;
|
||||
};
|
||||
|
||||
backlight1: backlight1 {
|
||||
compatible = "pwm-backlight";
|
||||
pwms = <&pwm1 0 500000 PWM_POLARITY_INVERTED>;
|
||||
power-supply = <®_lcd1_pwr>;
|
||||
/*
|
||||
* a poor man's way to create a 1:1 relationship between
|
||||
* the PWM value and the actual duty cycle
|
||||
*/
|
||||
brightness-levels = < 0 1 2 3 4 5 6 7 8 9
|
||||
10 11 12 13 14 15 16 17 18 19
|
||||
20 21 22 23 24 25 26 27 28 29
|
||||
30 31 32 33 34 35 36 37 38 39
|
||||
40 41 42 43 44 45 46 47 48 49
|
||||
50 51 52 53 54 55 56 57 58 59
|
||||
60 61 62 63 64 65 66 67 68 69
|
||||
70 71 72 73 74 75 76 77 78 79
|
||||
80 81 82 83 84 85 86 87 88 89
|
||||
90 91 92 93 94 95 96 97 98 99
|
||||
100>;
|
||||
default-brightness-level = <50>;
|
||||
};
|
||||
};
|
||||
|
||||
&can1 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&can2 {
|
||||
xceiver-supply = <®_3v3>;
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
polytouch1: eeti@04 {
|
||||
compatible = "eeti,egalax_ts";
|
||||
reg = <0x04>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_eeti>;
|
||||
interrupts-extended = <&gpio3 22 IRQ_TYPE_EDGE_FALLING>;
|
||||
wakeup-gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>;
|
||||
wakeup-source;
|
||||
};
|
||||
};
|
||||
|
||||
&kpp {
|
||||
status = "disabled"; /* pads partially clash with backlight1 PWM */
|
||||
};
|
||||
|
||||
&ldb {
|
||||
status = "okay";
|
||||
|
||||
lvds0: lvds-channel@0 {
|
||||
fsl,data-mapping = "spwg";
|
||||
fsl,data-width = <18>;
|
||||
status = "okay";
|
||||
|
||||
display-timings {
|
||||
native-mode = <&lvds0_timing1>;
|
||||
|
||||
lvds0_timing0: hsd100pxn1 {
|
||||
clock-frequency = <65000000>;
|
||||
hactive = <1024>;
|
||||
vactive = <768>;
|
||||
hback-porch = <220>;
|
||||
hfront-porch = <40>;
|
||||
vback-porch = <21>;
|
||||
vfront-porch = <7>;
|
||||
hsync-len = <60>;
|
||||
vsync-len = <10>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <1>;
|
||||
};
|
||||
|
||||
lvds0_timing1: VGA {
|
||||
clock-frequency = <25200000>;
|
||||
hactive = <640>;
|
||||
vactive = <480>;
|
||||
hback-porch = <48>;
|
||||
hfront-porch = <16>;
|
||||
vback-porch = <31>;
|
||||
vfront-porch = <12>;
|
||||
hsync-len = <96>;
|
||||
vsync-len = <2>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <0>;
|
||||
};
|
||||
|
||||
lvds0_timing2: nl12880bc20 {
|
||||
clock-frequency = <71000000>;
|
||||
hactive = <1280>;
|
||||
vactive = <800>;
|
||||
hback-porch = <50>;
|
||||
hfront-porch = <50>;
|
||||
vback-porch = <5>;
|
||||
vfront-porch = <5>;
|
||||
hsync-len = <60>;
|
||||
vsync-len = <13>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
lvds1: lvds-channel@1 {
|
||||
fsl,data-mapping = "spwg";
|
||||
fsl,data-width = <18>;
|
||||
status = "okay";
|
||||
|
||||
display-timings {
|
||||
native-mode = <&lvds1_timing2>;
|
||||
|
||||
lvds1_timing0: hsd100pxn1 {
|
||||
clock-frequency = <65000000>;
|
||||
hactive = <1024>;
|
||||
vactive = <768>;
|
||||
hback-porch = <220>;
|
||||
hfront-porch = <40>;
|
||||
vback-porch = <21>;
|
||||
vfront-porch = <7>;
|
||||
hsync-len = <60>;
|
||||
vsync-len = <10>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <1>;
|
||||
};
|
||||
|
||||
lvds1_timing1: VGA {
|
||||
clock-frequency = <25200000>;
|
||||
hactive = <640>;
|
||||
vactive = <480>;
|
||||
hback-porch = <48>;
|
||||
hfront-porch = <16>;
|
||||
vback-porch = <31>;
|
||||
vfront-porch = <12>;
|
||||
hsync-len = <96>;
|
||||
vsync-len = <2>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <0>;
|
||||
};
|
||||
|
||||
lvds1_timing2: nl12880bc20 {
|
||||
clock-frequency = <71000000>;
|
||||
hactive = <1280>;
|
||||
vactive = <800>;
|
||||
hback-porch = <50>;
|
||||
hfront-porch = <50>;
|
||||
vback-porch = <5>;
|
||||
vfront-porch = <5>;
|
||||
hsync-len = <60>;
|
||||
vsync-len = <13>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pwm1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl_eeti: eetigrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b1 /* Interrupt */
|
||||
>;
|
||||
};
|
||||
};
|
||||
@ -13,7 +13,7 @@
|
||||
#include "imx6qdl-wandboard-revb1.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Wandboard i.MX6 Dual Lite Board";
|
||||
model = "Wandboard i.MX6 Dual Lite Board rev B1";
|
||||
compatible = "wand,imx6dl-wandboard", "fsl,imx6dl";
|
||||
|
||||
memory {
|
||||
|
||||
@ -30,7 +30,7 @@
|
||||
/* kHz uV */
|
||||
996000 1250000
|
||||
792000 1175000
|
||||
396000 1075000
|
||||
396000 1150000
|
||||
>;
|
||||
fsl,soc-operating-points = <
|
||||
/* ARM kHz SOC-PU uV */
|
||||
|
||||
318
sys/gnu/dts/arm/imx6q-apalis-ixora.dts
Normal file
318
sys/gnu/dts/arm/imx6q-apalis-ixora.dts
Normal file
@ -0,0 +1,318 @@
|
||||
/*
|
||||
* Copyright 2014-2016 Toradex AG
|
||||
* Copyright 2012 Freescale Semiconductor, Inc.
|
||||
* Copyright 2011 Linaro Ltd.
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include "imx6q.dtsi"
|
||||
#include "imx6qdl-apalis.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Toradex Apalis iMX6Q/D Module on Ixora Carrier Board";
|
||||
compatible = "toradex,apalis_imx6q-ixora", "toradex,apalis_imx6q",
|
||||
"fsl,imx6q";
|
||||
|
||||
aliases {
|
||||
i2c0 = &i2cddc;
|
||||
i2c1 = &i2c1;
|
||||
i2c2 = &i2c2;
|
||||
i2c3 = &i2c3;
|
||||
};
|
||||
|
||||
aliases {
|
||||
rtc0 = &rtc_i2c;
|
||||
rtc1 = &snvs_rtc;
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_gpio_keys>;
|
||||
|
||||
wakeup {
|
||||
label = "Wake-Up";
|
||||
gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_WAKEUP>;
|
||||
debounce-interval = <10>;
|
||||
wakeup-source;
|
||||
};
|
||||
};
|
||||
|
||||
lcd_display: display@di0 {
|
||||
compatible = "fsl,imx-parallel-display";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interface-pix-fmt = "rgb24";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ipu1_lcdif>;
|
||||
status = "okay";
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
lcd_display_in: endpoint {
|
||||
remote-endpoint = <&ipu1_di0_disp1>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
lcd_display_out: endpoint {
|
||||
remote-endpoint = <&lcd_panel_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
panel: panel {
|
||||
/*
|
||||
* edt,et057090dhu: EDT 5.7" LCD TFT
|
||||
* edt,et070080dh6: EDT 7.0" LCD TFT
|
||||
*/
|
||||
compatible = "edt,et057090dhu";
|
||||
backlight = <&backlight>;
|
||||
|
||||
port {
|
||||
lcd_panel_in: endpoint {
|
||||
remote-endpoint = <&lcd_display_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_leds_ixora>;
|
||||
|
||||
led4-green {
|
||||
label = "LED_4_GREEN";
|
||||
gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
led4-red {
|
||||
label = "LED_4_RED";
|
||||
gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
led5-green {
|
||||
label = "LED_5_GREEN";
|
||||
gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
led5-red {
|
||||
label = "LED_5_RED";
|
||||
gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
pwmleds {
|
||||
compatible = "pwm-leds";
|
||||
|
||||
ledpwm1 {
|
||||
label = "PWM1";
|
||||
pwms = <&pwm1 0 50000>;
|
||||
max-brightness = <255>;
|
||||
};
|
||||
|
||||
ledpwm2 {
|
||||
label = "PWM2";
|
||||
pwms = <&pwm2 0 50000>;
|
||||
max-brightness = <255>;
|
||||
};
|
||||
|
||||
ledpwm3 {
|
||||
label = "PWM3";
|
||||
pwms = <&pwm3 0 50000>;
|
||||
max-brightness = <255>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&backlight {
|
||||
brightness-levels = <0 127 191 223 239 247 251 255>;
|
||||
default-brightness-level = <1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&can1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&can2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hdmi {
|
||||
ddc-i2c-bus = <&i2cddc>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2cddc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* GEN1_I2C: I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier board) */
|
||||
&i2c1 {
|
||||
status = "okay";
|
||||
|
||||
eeprom@50 {
|
||||
compatible = "atmel,24c02";
|
||||
reg = <0x50>;
|
||||
};
|
||||
|
||||
/* M41T0M6 real time clock on carrier board */
|
||||
rtc_i2c: rtc@68 {
|
||||
compatible = "st,m41t00";
|
||||
reg = <0x68>;
|
||||
};
|
||||
};
|
||||
|
||||
&ipu1_di0_disp1 {
|
||||
remote-endpoint = <&lcd_display_in>;
|
||||
};
|
||||
|
||||
&ldb {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie {
|
||||
/* active-high meaning opposite of regular PERST# active-low polarity */
|
||||
reset-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>;
|
||||
reset-gpio-active-high;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm4 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
®_usb_otg_vbus {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
®_usb_host_vbus {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sata {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sound_spdif {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&spdif {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart4 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart5 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbh1 {
|
||||
vbus-supply = <®_usb_host_vbus>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbotg {
|
||||
vbus-supply = <®_usb_otg_vbus>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* SD1 */
|
||||
&usdhc2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_sd_cd>;
|
||||
cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
/*
|
||||
* Mux the Apalis GPIOs
|
||||
* GPIO5, 6 used by optional fusion_F0710A kernel module
|
||||
*/
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_apalis_gpio1 &pinctrl_apalis_gpio2
|
||||
&pinctrl_apalis_gpio3 &pinctrl_apalis_gpio4
|
||||
&pinctrl_apalis_gpio5 &pinctrl_apalis_gpio6
|
||||
&pinctrl_apalis_gpio7 &pinctrl_apalis_gpio8
|
||||
>;
|
||||
|
||||
pinctrl_leds_ixora: ledsixoragrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x1b0b0
|
||||
MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0x1b0b0
|
||||
MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
|
||||
MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
|
||||
>;
|
||||
};
|
||||
};
|
||||
91
sys/gnu/dts/arm/imx6q-b450v3.dts
Normal file
91
sys/gnu/dts/arm/imx6q-b450v3.dts
Normal file
@ -0,0 +1,91 @@
|
||||
/*
|
||||
* Copyright 2015 Timesys Corporation.
|
||||
* Copyright 2015 General Electric Company
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "imx6q-bx50v3.dtsi"
|
||||
|
||||
/ {
|
||||
model = "General Electric B450v3";
|
||||
compatible = "ge,imx6q-b450v3", "advantech,imx6q-ba16", "fsl,imx6q";
|
||||
|
||||
chosen {
|
||||
stdout-path = &uart3;
|
||||
};
|
||||
|
||||
panel-lvds0 {
|
||||
compatible = "innolux,g121x1-l03";
|
||||
backlight = <&backlight_lvds>;
|
||||
power-supply = <®_lvds>;
|
||||
|
||||
port {
|
||||
panel_in_lvds0: endpoint {
|
||||
remote-endpoint = <&lvds0_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&clks {
|
||||
assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
|
||||
<&clks IMX6QDL_CLK_LDB_DI1_SEL>;
|
||||
assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
|
||||
<&clks IMX6QDL_CLK_PLL3_USB_OTG>;
|
||||
};
|
||||
|
||||
&ldb {
|
||||
status = "okay";
|
||||
|
||||
lvds0: lvds-channel@0 {
|
||||
fsl,data-mapping = "spwg";
|
||||
fsl,data-width = <24>;
|
||||
status = "okay";
|
||||
|
||||
port@4 {
|
||||
reg = <4>;
|
||||
|
||||
lvds0_out: endpoint {
|
||||
remote-endpoint = <&panel_in_lvds0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
91
sys/gnu/dts/arm/imx6q-b650v3.dts
Normal file
91
sys/gnu/dts/arm/imx6q-b650v3.dts
Normal file
@ -0,0 +1,91 @@
|
||||
/*
|
||||
* Copyright 2015 Timesys Corporation.
|
||||
* Copyright 2015 General Electric Company
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "imx6q-bx50v3.dtsi"
|
||||
|
||||
/ {
|
||||
model = "General Electric B650v3";
|
||||
compatible = "ge,imx6q-b650v3", "advantech,imx6q-ba16", "fsl,imx6q";
|
||||
|
||||
chosen {
|
||||
stdout-path = &uart3;
|
||||
};
|
||||
|
||||
panel-lvds0 {
|
||||
compatible = "innolux,g121x1-l03";
|
||||
backlight = <&backlight_lvds>;
|
||||
power-supply = <®_lvds>;
|
||||
|
||||
port {
|
||||
panel_in_lvds0: endpoint {
|
||||
remote-endpoint = <&lvds0_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&clks {
|
||||
assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
|
||||
<&clks IMX6QDL_CLK_LDB_DI1_SEL>;
|
||||
assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
|
||||
<&clks IMX6QDL_CLK_PLL3_USB_OTG>;
|
||||
};
|
||||
|
||||
&ldb {
|
||||
status = "okay";
|
||||
|
||||
lvds0: lvds-channel@0 {
|
||||
fsl,data-mapping = "spwg";
|
||||
fsl,data-width = <24>;
|
||||
status = "okay";
|
||||
|
||||
port@4 {
|
||||
reg = <4>;
|
||||
|
||||
lvds0_out: endpoint {
|
||||
remote-endpoint = <&panel_in_lvds0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
144
sys/gnu/dts/arm/imx6q-b850v3.dts
Normal file
144
sys/gnu/dts/arm/imx6q-b850v3.dts
Normal file
@ -0,0 +1,144 @@
|
||||
/*
|
||||
* Copyright 2015 Timesys Corporation.
|
||||
* Copyright 2015 General Electric Company
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "imx6q-bx50v3.dtsi"
|
||||
|
||||
/ {
|
||||
model = "General Electric B850v3";
|
||||
compatible = "ge,imx6q-b850v3", "advantech,imx6q-ba16", "fsl,imx6q";
|
||||
|
||||
chosen {
|
||||
stdout-path = &uart3;
|
||||
};
|
||||
};
|
||||
|
||||
&clks {
|
||||
assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
|
||||
<&clks IMX6QDL_CLK_LDB_DI1_SEL>,
|
||||
<&clks IMX6QDL_CLK_IPU1_DI0_PRE_SEL>,
|
||||
<&clks IMX6QDL_CLK_IPU1_DI1_PRE_SEL>;
|
||||
assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
|
||||
<&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
|
||||
<&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
|
||||
<&clks IMX6QDL_CLK_PLL2_PFD2_396M>;
|
||||
};
|
||||
|
||||
&ldb {
|
||||
fsl,dual-channel;
|
||||
status = "okay";
|
||||
|
||||
lvds0: lvds-channel@0 {
|
||||
fsl,data-mapping = "spwg";
|
||||
fsl,data-width = <24>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
pca9547_ddc: mux@70 {
|
||||
compatible = "nxp,pca9547";
|
||||
reg = <0x70>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
mux2_i2c1: i2c@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x0>;
|
||||
};
|
||||
|
||||
mux2_i2c2: i2c@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x1>;
|
||||
};
|
||||
|
||||
mux2_i2c3: i2c@2 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x2>;
|
||||
};
|
||||
|
||||
mux2_i2c4: i2c@3 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x3>;
|
||||
};
|
||||
|
||||
mux2_i2c5: i2c@4 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x4>;
|
||||
};
|
||||
|
||||
mux2_i2c6: i2c@5 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x5>;
|
||||
};
|
||||
|
||||
mux2_i2c7: i2c@6 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x6>;
|
||||
};
|
||||
|
||||
mux2_i2c8: i2c@7 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x7>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&hdmi {
|
||||
ddc-i2c-bus = <&mux2_i2c1>;
|
||||
};
|
||||
|
||||
&mux1_i2c1 {
|
||||
ads7830@4a {
|
||||
compatible = "ti,ads7830";
|
||||
reg = <0x4a>;
|
||||
};
|
||||
};
|
||||
634
sys/gnu/dts/arm/imx6q-ba16.dtsi
Normal file
634
sys/gnu/dts/arm/imx6q-ba16.dtsi
Normal file
@ -0,0 +1,634 @@
|
||||
/*
|
||||
* Support for imx6 based Advantech DMS-BA16 Qseven module
|
||||
*
|
||||
* Copyright 2015 Timesys Corporation.
|
||||
* Copyright 2015 General Electric Company
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#include "imx6q.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/ {
|
||||
memory {
|
||||
reg = <0x10000000 0x40000000>;
|
||||
};
|
||||
|
||||
backlight_lvds: backlight {
|
||||
compatible = "pwm-backlight";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_display>;
|
||||
pwms = <&pwm1 0 5000000>;
|
||||
brightness-levels = < 0 1 2 3 4 5 6 7 8 9
|
||||
10 11 12 13 14 15 16 17 18 19
|
||||
20 21 22 23 24 25 26 27 28 29
|
||||
30 31 32 33 34 35 36 37 38 39
|
||||
40 41 42 43 44 45 46 47 48 49
|
||||
50 51 52 53 54 55 56 57 58 59
|
||||
60 61 62 63 64 65 66 67 68 69
|
||||
70 71 72 73 74 75 76 77 78 79
|
||||
80 81 82 83 84 85 86 87 88 89
|
||||
90 91 92 93 94 95 96 97 98 99
|
||||
100 101 102 103 104 105 106 107 108 109
|
||||
110 111 112 113 114 115 116 117 118 119
|
||||
120 121 122 123 124 125 126 127 128 129
|
||||
130 131 132 133 134 135 136 137 138 139
|
||||
140 141 142 143 144 145 146 147 148 149
|
||||
150 151 152 153 154 155 156 157 158 159
|
||||
160 161 162 163 164 165 166 167 168 169
|
||||
170 171 172 173 174 175 176 177 178 179
|
||||
180 181 182 183 184 185 186 187 188 189
|
||||
190 191 192 193 194 195 196 197 198 199
|
||||
200 201 202 203 204 205 206 207 208 209
|
||||
210 211 212 213 214 215 216 217 218 219
|
||||
220 221 222 223 224 225 226 227 228 229
|
||||
230 231 232 233 234 235 236 237 238 239
|
||||
240 241 242 243 244 245 246 247 248 249
|
||||
250 251 252 253 254 255>;
|
||||
default-brightness-level = <255>;
|
||||
enable-gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
reg_1p8v: regulator-1p8v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "1P8V";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_3p3v: regulator-3p3v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "3P3V";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_lvds: regulator-lvds {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "lvds_ppen";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
reg_usb_h1_vbus: regulator-usbh1vbus {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "usb_h1_vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
};
|
||||
|
||||
reg_usb_otg_vbus: regulator-usbotgvbus {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "usb_otg_vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&audmux {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_audmux>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ecspi1 {
|
||||
fsl,spi-num-chipselects = <1>;
|
||||
cs-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ecspi1>;
|
||||
status = "okay";
|
||||
|
||||
flash: n25q032@0 {
|
||||
compatible = "jedec,spi-nor";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
spi-max-frequency = <20000000>;
|
||||
reg = <0>;
|
||||
|
||||
partition@0 {
|
||||
label = "U-Boot";
|
||||
reg = <0x0 0xc0000>;
|
||||
};
|
||||
|
||||
partition@c0000 {
|
||||
label = "env";
|
||||
reg = <0xc0000 0x10000>;
|
||||
};
|
||||
|
||||
partition@d0000 {
|
||||
label = "spare";
|
||||
reg = <0xd0000 0x130000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&fec {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_enet>;
|
||||
phy-mode = "rgmii";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hdmi {
|
||||
ddc-i2c-bus = <&i2c2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
clock-frequency = <100000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
clock-frequency = <100000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
clock-frequency = <100000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c3>;
|
||||
status = "okay";
|
||||
|
||||
pmic@58 {
|
||||
compatible = "dlg,da9063";
|
||||
reg = <0x58>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pmic>;
|
||||
interrupt-parent = <&gpio7>;
|
||||
interrupts = <13 IRQ_TYPE_LEVEL_LOW>;
|
||||
|
||||
onkey {
|
||||
compatible = "dlg,da9063-onkey";
|
||||
};
|
||||
|
||||
regulators {
|
||||
vdd_bcore1: bcore1 {
|
||||
regulator-min-microvolt = <1420000>;
|
||||
regulator-max-microvolt = <1420000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vdd_bcore2: bcore2 {
|
||||
regulator-min-microvolt = <1420000>;
|
||||
regulator-max-microvolt = <1420000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vdd_bpro: bpro {
|
||||
regulator-min-microvolt = <1500000>;
|
||||
regulator-max-microvolt = <1500000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vdd_bmem: bmem {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vdd_bio: bio {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vdd_bperi: bperi {
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vdd_ldo1: ldo1 {
|
||||
regulator-min-microvolt = <600000>;
|
||||
regulator-max-microvolt = <1860000>;
|
||||
};
|
||||
|
||||
vdd_ldo2: ldo2 {
|
||||
regulator-min-microvolt = <600000>;
|
||||
regulator-max-microvolt = <1860000>;
|
||||
};
|
||||
|
||||
vdd_ldo3: ldo3 {
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <3440000>;
|
||||
};
|
||||
|
||||
vdd_ldo4: ldo4 {
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <3440000>;
|
||||
};
|
||||
|
||||
vdd_ldo5: ldo5 {
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <3600000>;
|
||||
};
|
||||
|
||||
vdd_ldo6: ldo6 {
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <3600000>;
|
||||
};
|
||||
|
||||
vdd_ldo7: ldo7 {
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <3600000>;
|
||||
};
|
||||
|
||||
vdd_ldo8: ldo8 {
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <3600000>;
|
||||
};
|
||||
|
||||
vdd_ldo9: ldo9 {
|
||||
regulator-min-microvolt = <950000>;
|
||||
regulator-max-microvolt = <3600000>;
|
||||
};
|
||||
|
||||
vdd_ldo10: ldo10 {
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <3600000>;
|
||||
};
|
||||
|
||||
vdd_ldo11: ldo11 {
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <3600000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
rtc@32 {
|
||||
compatible = "epson,rx8010";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_rtc>;
|
||||
reg = <0x32>;
|
||||
interrupt-parent = <&gpio4>;
|
||||
interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
&pcie {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pcie>;
|
||||
reset-gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>;
|
||||
fsl,tx-swing-full = <103>;
|
||||
fsl,tx-swing-low = <103>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pwm1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pwm2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&sata {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ssi1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart3>;
|
||||
fsl,uart-has-rtscts;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart4 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart4>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbh1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usbhub>;
|
||||
vbus-supply = <®_usb_h1_vbus>;
|
||||
reset-gpios = <&gpio7 11 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbotg {
|
||||
vbus-supply = <®_usb_otg_vbus>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usbotg>;
|
||||
disable-over-current;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usdhc2>;
|
||||
cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
|
||||
no-1-8-v;
|
||||
keep-power-in-suspend;
|
||||
wakeup-source;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usdhc3 &pinctrl_usdhc3_reset>;
|
||||
bus-width = <8>;
|
||||
vmmc-supply = <&vdd_bperi>;
|
||||
non-removable;
|
||||
keep-power-in-suspend;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wdog1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_wdog>;
|
||||
fsl,ext-reset-output;
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_hog>;
|
||||
|
||||
pinctrl_audmux: audmuxgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0
|
||||
MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x130b0
|
||||
MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0
|
||||
MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_display: dispgrp {
|
||||
fsl,pins = <
|
||||
/* BLEN_OUT */
|
||||
MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0
|
||||
/* LVDS_PPEN_OUT */
|
||||
MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_ecspi1: ecspi1grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
|
||||
MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
|
||||
MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
|
||||
/* SPI1 CS */
|
||||
MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_ecspi5: ecspi5grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD1_DAT0__ECSPI5_MISO 0x1b0b0
|
||||
MX6QDL_PAD_SD1_CMD__ECSPI5_MOSI 0x1b0b0
|
||||
MX6QDL_PAD_SD1_CLK__ECSPI5_SCLK 0x1b0b0
|
||||
MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_enet: enetgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0
|
||||
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0
|
||||
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0
|
||||
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0
|
||||
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0
|
||||
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0
|
||||
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0
|
||||
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0
|
||||
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0
|
||||
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
|
||||
/* FEC Reset */
|
||||
MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0
|
||||
/* AR8033 Interrupt */
|
||||
MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_hog: hoggrp {
|
||||
fsl,pins = <
|
||||
/* GPIO 0-7 */
|
||||
MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0
|
||||
MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
|
||||
MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
|
||||
MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0
|
||||
MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0
|
||||
MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x1b0b0
|
||||
MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0
|
||||
MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x1b0b0
|
||||
/* SUS_S3_OUT to CPLD */
|
||||
MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c1: i2c1grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
|
||||
MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c2: i2c2grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
|
||||
MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c3: i2c3grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
|
||||
MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pcie: pciegrp {
|
||||
fsl,pins = <
|
||||
/* PCIe Reset */
|
||||
MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0
|
||||
/* PCIe Wake */
|
||||
MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pmic: pmicgrp {
|
||||
fsl,pins = <
|
||||
/* PMIC Interrupt */
|
||||
MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pwm1: pwm1grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pwm2: pwm2grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_rtc: rtcgrp {
|
||||
fsl,pins = <
|
||||
/* RTC_INT */
|
||||
MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart3: uart3grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
|
||||
MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
|
||||
MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1
|
||||
MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart4: uart4grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
|
||||
MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usbhub: usbhubgrp {
|
||||
fsl,pins = <
|
||||
/* HUB_RESET */
|
||||
MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usbotg: usbotggrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2: usdhc2grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
|
||||
MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
|
||||
MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
|
||||
MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
|
||||
MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
|
||||
MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
|
||||
/* uSDHC2 CD */
|
||||
MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3: usdhc3grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
|
||||
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
|
||||
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
|
||||
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
|
||||
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
|
||||
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
|
||||
MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
|
||||
MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
|
||||
MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
|
||||
MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3_reset: usdhc3grp-reset {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD3_RST__SD3_RESET 0x170F9
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc4: usdhc4grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
|
||||
MX6QDL_PAD_SD4_CLK__SD4_CLK 0x17059
|
||||
MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
|
||||
MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
|
||||
MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
|
||||
MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
|
||||
MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
|
||||
MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
|
||||
MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
|
||||
MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
|
||||
/* uSDHC4 CD */
|
||||
MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x1b0b0
|
||||
/* uSDHC4 SDIO PWR */
|
||||
MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x1b0b0
|
||||
/* uSDHC4 SDIO WP */
|
||||
MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0
|
||||
/* uSDHC4 SDIO LED */
|
||||
MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_wdog: wdoggrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_GPIO_9__WDOG1_B 0x1b0b0
|
||||
>;
|
||||
};
|
||||
};
|
||||
225
sys/gnu/dts/arm/imx6q-bx50v3.dtsi
Normal file
225
sys/gnu/dts/arm/imx6q-bx50v3.dtsi
Normal file
@ -0,0 +1,225 @@
|
||||
/*
|
||||
* Copyright 2015 Timesys Corporation.
|
||||
* Copyright 2015 General Electric Company
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#include "imx6q-ba16.dtsi"
|
||||
|
||||
/ {
|
||||
clocks {
|
||||
mclk: clock@0 {
|
||||
compatible = "fixed-clock";
|
||||
reg = <0>;
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <22000000>;
|
||||
};
|
||||
};
|
||||
|
||||
reg_wl18xx_vmmc: regulator-wl18xx {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vwl1807";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
gpio = <&pca9539 3 GPIO_ACTIVE_HIGH>;
|
||||
startup-delay-us = <70000>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
reg_wlan: regulator-wlan {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "3P3V_wlan";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
gpio = <&gpio6 14 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
sound {
|
||||
compatible = "fsl,imx6q-ba16-sgtl5000",
|
||||
"fsl,imx-audio-sgtl5000";
|
||||
model = "imx6q-ba16-sgtl5000";
|
||||
ssi-controller = <&ssi1>;
|
||||
audio-codec = <&sgtl5000>;
|
||||
audio-routing =
|
||||
"MIC_IN", "Mic Jack",
|
||||
"Mic Jack", "Mic Bias",
|
||||
"LINE_IN", "Line In Jack",
|
||||
"Headphone Jack", "HP_OUT";
|
||||
mux-int-port = <1>;
|
||||
mux-ext-port = <4>;
|
||||
};
|
||||
};
|
||||
|
||||
&ecspi5 {
|
||||
fsl,spi-num-chipselects = <1>;
|
||||
cs-gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ecspi5>;
|
||||
status = "okay";
|
||||
|
||||
m25_eeprom: m25p80@0 {
|
||||
compatible = "atmel,at25";
|
||||
spi-max-frequency = <20000000>;
|
||||
size = <0x8000>;
|
||||
pagesize = <64>;
|
||||
reg = <0>;
|
||||
address-width = <16>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
pca9547: mux@70 {
|
||||
compatible = "nxp,pca9547";
|
||||
reg = <0x70>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
mux1_i2c1: i2c@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x0>;
|
||||
|
||||
ads7830: ads7830@48 {
|
||||
compatible = "ti,ads7830";
|
||||
reg = <0x48>;
|
||||
};
|
||||
|
||||
mma8453: mma8453@1c {
|
||||
compatible = "fsl,mma8453";
|
||||
reg = <0x1c>;
|
||||
};
|
||||
};
|
||||
|
||||
mux1_i2c2: i2c@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x1>;
|
||||
|
||||
eeprom: eeprom@50 {
|
||||
compatible = "atmel,24c08";
|
||||
reg = <0x50>;
|
||||
};
|
||||
|
||||
mpl3115: mpl3115@60 {
|
||||
compatible = "fsl,mpl3115";
|
||||
reg = <0x60>;
|
||||
};
|
||||
};
|
||||
|
||||
mux1_i2c3: i2c@2 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x2>;
|
||||
};
|
||||
|
||||
mux1_i2c4: i2c@3 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x3>;
|
||||
|
||||
sgtl5000: codec@0a {
|
||||
compatible = "fsl,sgtl5000";
|
||||
reg = <0x0a>;
|
||||
clocks = <&mclk>;
|
||||
VDDA-supply = <®_1p8v>;
|
||||
VDDIO-supply = <®_3p3v>;
|
||||
};
|
||||
};
|
||||
|
||||
mux1_i2c5: i2c@4 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x4>;
|
||||
|
||||
pca9539: pca9539@74 {
|
||||
compatible = "nxp,pca9539";
|
||||
reg = <0x74>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&gpio2>;
|
||||
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
mux1_i2c6: i2c@5 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x5>;
|
||||
};
|
||||
|
||||
mux1_i2c7: i2c@6 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x6>;
|
||||
};
|
||||
|
||||
mux1_i2c8: i2c@7 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x7>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&usdhc4 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usdhc4>;
|
||||
bus-width = <4>;
|
||||
vmmc-supply = <®_wl18xx_vmmc>;
|
||||
no-1-8-v;
|
||||
non-removable;
|
||||
wakeup-source;
|
||||
keep-power-in-suspend;
|
||||
cap-power-off-card;
|
||||
max-frequency = <25000000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "okay";
|
||||
|
||||
wlcore: wlcore@2 {
|
||||
compatible = "ti,wl1837";
|
||||
reg = <2>;
|
||||
interrupt-parent = <&gpio2>;
|
||||
interrupts = <6 IRQ_TYPE_LEVEL_HIGH>;
|
||||
tcxo-clock-frequency = <26000000>;
|
||||
};
|
||||
};
|
||||
502
sys/gnu/dts/arm/imx6q-evi.dts
Normal file
502
sys/gnu/dts/arm/imx6q-evi.dts
Normal file
@ -0,0 +1,502 @@
|
||||
/*
|
||||
* Copyright 2016 United Western Technologies.
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "imx6q.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
/ {
|
||||
model = "Uniwest Evi";
|
||||
compatible = "uniwest,imx6q-evi", "fsl,imx6q";
|
||||
|
||||
memory {
|
||||
reg = <0x10000000 0x40000000>;
|
||||
};
|
||||
|
||||
reg_usbh1_vbus: regulator-usbhubreset {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "usbh1_vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
enable-active-high;
|
||||
startup-delay-us = <2>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usbh1_hubreset>;
|
||||
gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
reg_usb_otg_vbus: regulator-usbotgvbus {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "usb_otg_vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usbotgvbus>;
|
||||
gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
panel {
|
||||
compatible = "sharp,lq101k1ly04";
|
||||
|
||||
port {
|
||||
panel_in: endpoint {
|
||||
remote-endpoint = <&lvds0_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&ecspi1 {
|
||||
fsl,spi-num-chipselects = <1>;
|
||||
cs-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1cs>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ecspi3 {
|
||||
fsl,spi-num-chipselects = <3>;
|
||||
cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>,
|
||||
<&gpio4 25 GPIO_ACTIVE_LOW>,
|
||||
<&gpio4 26 GPIO_ACTIVE_LOW>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ecspi3 &pinctrl_ecspi3cs>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ecspi5 {
|
||||
fsl,spi-num-chipselects = <4>;
|
||||
cs-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>,
|
||||
<&gpio1 13 GPIO_ACTIVE_LOW>,
|
||||
<&gpio1 12 GPIO_ACTIVE_LOW>,
|
||||
<&gpio2 9 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ecspi5 &pinctrl_ecspi5cs>;
|
||||
status = "okay";
|
||||
|
||||
eeprom: m95m02@1 {
|
||||
compatible = "st,m95m02", "atmel,at25";
|
||||
size = <262144>;
|
||||
pagesize = <256>;
|
||||
address-width = <24>;
|
||||
spi-max-frequency = <5000000>;
|
||||
reg = <1>;
|
||||
};
|
||||
|
||||
pb_rtc: rtc@3 {
|
||||
compatible = "nxp,rtc-pcf2123";
|
||||
spi-max-frequency = <2450000>;
|
||||
spi-cs-high;
|
||||
reg = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
&fec {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_enet>;
|
||||
phy-mode = "rgmii";
|
||||
phy-reset-gpios = <&gpio1 25 0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpmi {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_gpminand>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c2>;
|
||||
clock-frequency = <100000>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
pinctrl-names = "default", "gpio";
|
||||
pinctrl-0 = <&pinctrl_i2c3>;
|
||||
pinctrl-1 = <&pinctrl_i2c3_gpio>;
|
||||
clock-frequency = <100000>;
|
||||
scl-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
|
||||
sda-gpios = <&gpio7 11 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
|
||||
battery: sbs-battery@b {
|
||||
compatible = "sbs,sbs-battery";
|
||||
reg = <0x0b>;
|
||||
sbs,poll-retry-count = <100>;
|
||||
sbs,i2c-retry-count = <100>;
|
||||
};
|
||||
};
|
||||
|
||||
&ldb {
|
||||
status = "okay";
|
||||
|
||||
lvds0: lvds-channel@0 {
|
||||
status = "okay";
|
||||
|
||||
port@4 {
|
||||
reg = <4>;
|
||||
lvds0_out: endpoint {
|
||||
remote-endpoint = <&panel_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&ssi1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbh1 {
|
||||
vbus-supply = <®_usbh1_vbus>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usbh1>;
|
||||
dr_mode = "host";
|
||||
disable-over-current;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbotg {
|
||||
vbus-supply = <®_usb_otg_vbus>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usbotg>;
|
||||
disable-over-current;
|
||||
dr_mode = "otg";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usdhc1>;
|
||||
non-removable;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&weim {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0 0x08000000 0x08000000>;
|
||||
fsl,weim-cs-gpr = <&gpr>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_weimfpga &pinctrl_weimcs>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_hog>;
|
||||
|
||||
pinctrl_hog: hoggrp {
|
||||
fsl,pins = <
|
||||
/* pwr mcu alert irq */
|
||||
MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0
|
||||
/* remainder ???? */
|
||||
MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_ecspi1: ecspi1grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1
|
||||
MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1
|
||||
MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_ecspi1cs: ecspi1csgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_ecspi3: ecspi3grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x10068
|
||||
MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x10068
|
||||
MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x1f068
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_ecspi3cs: ecspi3csgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x1b0b0
|
||||
MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x1b0b0
|
||||
MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x1b0b0
|
||||
MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_ecspi5: ecspi5grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD2_CLK__ECSPI5_SCLK 0x100b1
|
||||
MX6QDL_PAD_SD2_CMD__ECSPI5_MOSI 0x100b1
|
||||
MX6QDL_PAD_SD2_DAT0__ECSPI5_MISO 0x100b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_ecspi5cs: ecspi5csgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x1b0b0
|
||||
MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x1b0b0
|
||||
MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x1b0b0
|
||||
MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_enet: enetgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
|
||||
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
|
||||
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
|
||||
MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x4001b0a8
|
||||
MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_gpminand: gpminandgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
|
||||
MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
|
||||
MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
|
||||
MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
|
||||
MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
|
||||
MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
|
||||
MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
|
||||
MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
|
||||
MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
|
||||
MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
|
||||
MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
|
||||
MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
|
||||
MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
|
||||
MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
|
||||
MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
|
||||
MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
|
||||
MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c2: i2c2grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
|
||||
MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c3: i2c3grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
|
||||
MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c3_gpio: i2c3gpiogrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x4001b8b1
|
||||
MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x4001b8b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_weimcs: weimcsgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1
|
||||
MX6QDL_PAD_EIM_CS1__EIM_CS1_B 0xb0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_weimfpga: weimfpgagrp {
|
||||
fsl,pins = <
|
||||
/* weim misc */
|
||||
MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1
|
||||
MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1
|
||||
MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060
|
||||
MX6QDL_PAD_EIM_BCLK__EIM_BCLK 0xb0b1
|
||||
MX6QDL_PAD_EIM_LBA__EIM_LBA_B 0xb0b1
|
||||
MX6QDL_PAD_EIM_EB0__EIM_EB0_B 0xb0b1
|
||||
MX6QDL_PAD_EIM_EB1__EIM_EB1_B 0xb0b1
|
||||
MX6QDL_PAD_EIM_EB2__EIM_EB2_B 0xb0b1
|
||||
MX6QDL_PAD_EIM_EB3__EIM_EB3_B 0xb0b1
|
||||
/* weim data */
|
||||
MX6QDL_PAD_CSI0_DATA_EN__EIM_DATA00 0x1b0b0
|
||||
MX6QDL_PAD_CSI0_VSYNC__EIM_DATA01 0x1b0b0
|
||||
MX6QDL_PAD_CSI0_DAT4__EIM_DATA02 0x1b0b0
|
||||
MX6QDL_PAD_CSI0_DAT5__EIM_DATA03 0x1b0b0
|
||||
MX6QDL_PAD_CSI0_DAT6__EIM_DATA04 0x1b0b0
|
||||
MX6QDL_PAD_CSI0_DAT7__EIM_DATA05 0x1b0b0
|
||||
MX6QDL_PAD_CSI0_DAT8__EIM_DATA06 0x1b0b0
|
||||
MX6QDL_PAD_CSI0_DAT9__EIM_DATA07 0x1b0b0
|
||||
MX6QDL_PAD_CSI0_DAT12__EIM_DATA08 0x1b0b0
|
||||
MX6QDL_PAD_CSI0_DAT13__EIM_DATA09 0x1b0b0
|
||||
MX6QDL_PAD_CSI0_DAT14__EIM_DATA10 0x1b0b0
|
||||
MX6QDL_PAD_CSI0_DAT15__EIM_DATA11 0x1b0b0
|
||||
MX6QDL_PAD_CSI0_DAT16__EIM_DATA12 0x1b0b0
|
||||
MX6QDL_PAD_CSI0_DAT17__EIM_DATA13 0x1b0b0
|
||||
MX6QDL_PAD_CSI0_DAT18__EIM_DATA14 0x1b0b0
|
||||
MX6QDL_PAD_CSI0_DAT19__EIM_DATA15 0x1b0b0
|
||||
MX6QDL_PAD_EIM_D16__EIM_DATA16 0x1b0b0
|
||||
MX6QDL_PAD_EIM_D17__EIM_DATA17 0x1b0b0
|
||||
MX6QDL_PAD_EIM_D18__EIM_DATA18 0x1b0b0
|
||||
MX6QDL_PAD_EIM_D19__EIM_DATA19 0x1b0b0
|
||||
MX6QDL_PAD_EIM_D20__EIM_DATA20 0x1b0b0
|
||||
MX6QDL_PAD_EIM_D21__EIM_DATA21 0x1b0b0
|
||||
MX6QDL_PAD_EIM_D22__EIM_DATA22 0x1b0b0
|
||||
MX6QDL_PAD_EIM_D23__EIM_DATA23 0x1b0b0
|
||||
MX6QDL_PAD_EIM_D24__EIM_DATA24 0x1b0b0
|
||||
MX6QDL_PAD_EIM_D25__EIM_DATA25 0x1b0b0
|
||||
MX6QDL_PAD_EIM_D26__EIM_DATA26 0x1b0b0
|
||||
MX6QDL_PAD_EIM_D27__EIM_DATA27 0x1b0b0
|
||||
MX6QDL_PAD_EIM_D28__EIM_DATA28 0x1b0b0
|
||||
MX6QDL_PAD_EIM_D29__EIM_DATA29 0x1b0b0
|
||||
MX6QDL_PAD_EIM_D30__EIM_DATA30 0x1b0b0
|
||||
MX6QDL_PAD_EIM_D31__EIM_DATA31 0x1b0b0
|
||||
/* weim address */
|
||||
MX6QDL_PAD_EIM_A25__EIM_ADDR25 0xb0b1
|
||||
MX6QDL_PAD_EIM_A24__EIM_ADDR24 0xb0b1
|
||||
MX6QDL_PAD_EIM_A23__EIM_ADDR23 0xb0b1
|
||||
MX6QDL_PAD_EIM_A22__EIM_ADDR22 0xb0b1
|
||||
MX6QDL_PAD_EIM_A21__EIM_ADDR21 0xb0b1
|
||||
MX6QDL_PAD_EIM_A20__EIM_ADDR20 0xb0b1
|
||||
MX6QDL_PAD_EIM_A19__EIM_ADDR19 0xb0b1
|
||||
MX6QDL_PAD_EIM_A18__EIM_ADDR18 0xb0b1
|
||||
MX6QDL_PAD_EIM_A17__EIM_ADDR17 0xb0b1
|
||||
MX6QDL_PAD_EIM_A16__EIM_ADDR16 0xb0b1
|
||||
MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1
|
||||
MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1
|
||||
MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1
|
||||
MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1
|
||||
MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1
|
||||
MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1
|
||||
MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1
|
||||
MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1
|
||||
MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1
|
||||
MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1
|
||||
MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1
|
||||
MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1
|
||||
MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1
|
||||
MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1
|
||||
MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1
|
||||
MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart1: uart1grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
|
||||
MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart2: uart2grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD3_DAT5__UART2_TX_DATA 0x1b0b1
|
||||
MX6QDL_PAD_SD3_DAT4__UART2_RX_DATA 0x1b0b1
|
||||
MX6QDL_PAD_SD3_CLK__UART2_RTS_B 0x1b0b1
|
||||
MX6QDL_PAD_SD3_CMD__UART2_CTS_B 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usbh1: usbh1grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_GPIO_3__USB_H1_OC 0x1b0b0
|
||||
/* usbh1_b OC */
|
||||
MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usbh1_hubreset: usbh1hubresetgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usbotg: usbotggrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
|
||||
MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usbotgvbus: usbotgvbusgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x000b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1: usdhc1grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
|
||||
MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
|
||||
MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
|
||||
MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
|
||||
MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
|
||||
MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
|
||||
>;
|
||||
};
|
||||
};
|
||||
@ -44,7 +44,7 @@
|
||||
label = "recovery";
|
||||
gpios = <&gpio3 16 1>;
|
||||
linux,code = <0x198>; /* KEY_RESTART */
|
||||
gpio-key,wakeup;
|
||||
wakeup-source;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -327,7 +327,7 @@
|
||||
codec: sgtl5000@0a {
|
||||
compatible = "fsl,sgtl5000";
|
||||
reg = <0x0a>;
|
||||
clocks = <&clks 201>;
|
||||
clocks = <&clks IMX6QDL_CLK_CKO>;
|
||||
VDDA-supply = <&sw4_reg>;
|
||||
VDDIO-supply = <®_3p3v>;
|
||||
};
|
||||
|
||||
78
sys/gnu/dts/arm/imx6q-icore-rqs.dts
Normal file
78
sys/gnu/dts/arm/imx6q-icore-rqs.dts
Normal file
@ -0,0 +1,78 @@
|
||||
/*
|
||||
* Copyright (C) 2015 Amarula Solutions B.V.
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "imx6q.dtsi"
|
||||
#include "imx6qdl-icore-rqs.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Engicam i.CoreM6 Quad SOM";
|
||||
compatible = "engicam,imx6-icore-rqs", "fsl,imx6q";
|
||||
|
||||
sound {
|
||||
compatible = "fsl,imx-audio-sgtl5000";
|
||||
model = "imx-audio-sgtl5000";
|
||||
ssi-controller = <&ssi1>;
|
||||
audio-codec = <&codec>;
|
||||
audio-routing =
|
||||
"MIC_IN", "Mic Jack",
|
||||
"Mic Jack", "Mic Bias",
|
||||
"Headphone Jack", "HP_OUT";
|
||||
mux-int-port = <1>;
|
||||
mux-ext-port = <4>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
codec: sgtl5000@0a {
|
||||
compatible = "fsl,sgtl5000";
|
||||
reg = <0x0a>;
|
||||
clocks = <&clks IMX6QDL_CLK_CKO>;
|
||||
VDDA-supply = <®_2p5v>;
|
||||
VDDIO-supply = <®_3p3v>;
|
||||
VDDD-supply = <®_1p8v>;
|
||||
};
|
||||
};
|
||||
|
||||
&sata {
|
||||
status = "okay";
|
||||
};
|
||||
403
sys/gnu/dts/arm/imx6q-marsboard.dts
Normal file
403
sys/gnu/dts/arm/imx6q-marsboard.dts
Normal file
@ -0,0 +1,403 @@
|
||||
/*
|
||||
* Copyright (C) 2016 Sergio Prado (sergio.prado@e-labworks.com)
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "imx6q.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/ {
|
||||
model = "Embest MarS Board i.MX6Dual";
|
||||
compatible = "embest,imx6q-marsboard", "fsl,imx6q";
|
||||
|
||||
memory {
|
||||
reg = <0x10000000 0x40000000>;
|
||||
};
|
||||
|
||||
reg_3p3v: regulator-3p3v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "3P3V";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
reg_usb_otg_vbus: regulator-usb-otg-vbus {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "usb_otg_vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_led>;
|
||||
|
||||
user1 {
|
||||
label = "imx6:green:user1";
|
||||
gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
|
||||
default-state = "off";
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
|
||||
user2 {
|
||||
label = "imx6:green:user2";
|
||||
gpios = <&gpio3 28 GPIO_ACTIVE_LOW>;
|
||||
default-state = "off";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&audmux {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_audmux>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ecspi1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ecspi1>;
|
||||
cs-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>;
|
||||
fsl,spi-num-chipselects = <1>;
|
||||
status = "okay";
|
||||
|
||||
m25p80@0 {
|
||||
compatible = "microchip,sst25vf016b";
|
||||
spi-max-frequency = <20000000>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&fec {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_enet>;
|
||||
phy-mode = "rgmii";
|
||||
phy-reset-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hdmi {
|
||||
ddc-i2c-bus = <&i2c2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
clock-frequency = <100000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
clock-frequency = <100000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
clock-frequency = <100000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pwm1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pwm2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pwm3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm4 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pwm4>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart4 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart4>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart5 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart5>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbh1 {
|
||||
dr_mode = "host";
|
||||
disable-over-current;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbotg {
|
||||
vbus-supply = <®_usb_otg_vbus>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usbotg>;
|
||||
dr_mode = "otg";
|
||||
disable-over-current;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usdhc2>;
|
||||
vmmc-supply = <®_3p3v>;
|
||||
cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
|
||||
wp-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usdhc3>;
|
||||
vmmc-supply = <®_3p3v>;
|
||||
non-removable;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
|
||||
pinctrl_audmux: audmuxgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
|
||||
MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
|
||||
MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
|
||||
MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
|
||||
MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* CAM_MCLK */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_ecspi1: ecspi1grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
|
||||
MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
|
||||
MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
|
||||
MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x000b1 /* CS0 */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_enet: enetgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
|
||||
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
|
||||
/* AR8035 CLK_25M --> ENET_REF_CLK (V22) */
|
||||
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x0a0b1
|
||||
/* AR8035 pin strapping: IO voltage: pull up */
|
||||
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
|
||||
/* AR8035 pin strapping: PHYADDR#0: pull down */
|
||||
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x130b0
|
||||
/* AR8035 pin strapping: PHYADDR#1: pull down */
|
||||
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x130b0
|
||||
/* AR8035 pin strapping: MODE#1: pull up */
|
||||
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
|
||||
/* AR8035 pin strapping: MODE#3: pull up */
|
||||
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
|
||||
/* AR8035 pin strapping: MODE#0: pull down */
|
||||
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x130b0
|
||||
/* GPIO16 -> AR8035 25MHz */
|
||||
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
|
||||
/* RGMII_nRST */
|
||||
MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x130b0
|
||||
/* AR8035 interrupt */
|
||||
MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x180b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c1: i2c1grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
|
||||
MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c2: i2c2grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
|
||||
MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c3: i2c3grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
|
||||
MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_led: ledgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b1 /* LED1 */
|
||||
MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x1b0b1 /* LED2 */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pwm1: pwm1grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pwm2: pwm2grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_DISP0_DAT9__PWM2_OUT 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pwm3: pwm3grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pwm4: pwm4grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart1: uart1grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
|
||||
MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart2: uart2grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
|
||||
MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart3: uart3grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
|
||||
MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart4: uart4grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
|
||||
MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart5: uart5grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
|
||||
MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usbotg: usbotggrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
|
||||
MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0
|
||||
MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x000b0 /* USB OTG POWER ENABLE */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2: usdhc2grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
|
||||
MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
|
||||
MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
|
||||
MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
|
||||
MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
|
||||
MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
|
||||
MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* CD */
|
||||
MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1f0b0 /* WP */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3: usdhc3grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17009
|
||||
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10009
|
||||
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17009
|
||||
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17009
|
||||
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17009
|
||||
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17009
|
||||
MX6QDL_PAD_SD3_RST__SD3_RESET 0x17009
|
||||
>;
|
||||
};
|
||||
};
|
||||
@ -1,12 +1,42 @@
|
||||
/*
|
||||
* Copyright 2014 Lothar Waßmann <LW@KARO-electronics.de>
|
||||
* Copyright 2014-2016 Lothar Waßmann <LW@KARO-electronics.de>
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 at the following locations:
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
@ -1,12 +1,42 @@
|
||||
/*
|
||||
* Copyright 2014 Lothar Waßmann <LW@KARO-electronics.de>
|
||||
* Copyright 2014-2016 Lothar Waßmann <LW@KARO-electronics.de>
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 at the following locations:
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
@ -1,12 +1,42 @@
|
||||
/*
|
||||
* Copyright 2014 Lothar Waßmann <LW@KARO-electronics.de>
|
||||
* Copyright 2014-2016 Lothar Waßmann <LW@KARO-electronics.de>
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 at the following locations:
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
@ -94,22 +124,6 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
imx6qdl-tx6 {
|
||||
pinctrl_usdhc4: usdhc4grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD4_CMD__SD4_CMD 0x070b1
|
||||
MX6QDL_PAD_SD4_CLK__SD4_CLK 0x070b1
|
||||
MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x070b1
|
||||
MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x070b1
|
||||
MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x070b1
|
||||
MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x070b1
|
||||
MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x0b0b1
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&ipu1_di0_disp0 {
|
||||
remote-endpoint = <&display0_in>;
|
||||
};
|
||||
@ -134,3 +148,17 @@
|
||||
fsl,wp-controller;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl_usdhc4: usdhc4grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD4_CMD__SD4_CMD 0x070b1
|
||||
MX6QDL_PAD_SD4_CLK__SD4_CLK 0x070b1
|
||||
MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x070b1
|
||||
MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x070b1
|
||||
MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x070b1
|
||||
MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x070b1
|
||||
MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x0b0b1
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -1,12 +1,42 @@
|
||||
/*
|
||||
* Copyright 2014 Lothar Waßmann <LW@KARO-electronics.de>
|
||||
* Copyright 2014-2016 Lothar Waßmann <LW@KARO-electronics.de>
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 at the following locations:
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
@ -180,22 +210,6 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
imx6qdl-tx6 {
|
||||
pinctrl_usdhc4: usdhc4grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD4_CMD__SD4_CMD 0x070b1
|
||||
MX6QDL_PAD_SD4_CLK__SD4_CLK 0x070b1
|
||||
MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x070b1
|
||||
MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x070b1
|
||||
MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x070b1
|
||||
MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x070b1
|
||||
MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x0b0b1
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&ipu1_di0_disp0 {
|
||||
remote-endpoint = <&display0_in>;
|
||||
};
|
||||
@ -208,3 +222,17 @@
|
||||
fsl,wp-controller;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl_usdhc4: usdhc4grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD4_CMD__SD4_CMD 0x070b1
|
||||
MX6QDL_PAD_SD4_CLK__SD4_CLK 0x070b1
|
||||
MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x070b1
|
||||
MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x070b1
|
||||
MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x070b1
|
||||
MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x070b1
|
||||
MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x0b0b1
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
252
sys/gnu/dts/arm/imx6q-tx6q-1036.dts
Normal file
252
sys/gnu/dts/arm/imx6q-tx6q-1036.dts
Normal file
@ -0,0 +1,252 @@
|
||||
/*
|
||||
* Copyright 2014-2016 Lothar Waßmann <LW@KARO-electronics.de>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "imx6q.dtsi"
|
||||
#include "imx6qdl-tx6.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Ka-Ro electronics TX6Q-1036 Module";
|
||||
compatible = "karo,imx6q-tx6q", "fsl,imx6q";
|
||||
|
||||
aliases {
|
||||
display = &display;
|
||||
};
|
||||
|
||||
backlight: backlight {
|
||||
compatible = "pwm-backlight";
|
||||
pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_lcd0_pwr>;
|
||||
enable-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>;
|
||||
power-supply = <®_lcd1_pwr>;
|
||||
/*
|
||||
* a poor man's way to create a 1:1 relationship between
|
||||
* the PWM value and the actual duty cycle
|
||||
*/
|
||||
brightness-levels = < 0 1 2 3 4 5 6 7 8 9
|
||||
10 11 12 13 14 15 16 17 18 19
|
||||
20 21 22 23 24 25 26 27 28 29
|
||||
30 31 32 33 34 35 36 37 38 39
|
||||
40 41 42 43 44 45 46 47 48 49
|
||||
50 51 52 53 54 55 56 57 58 59
|
||||
60 61 62 63 64 65 66 67 68 69
|
||||
70 71 72 73 74 75 76 77 78 79
|
||||
80 81 82 83 84 85 86 87 88 89
|
||||
90 91 92 93 94 95 96 97 98 99
|
||||
100>;
|
||||
default-brightness-level = <50>;
|
||||
};
|
||||
|
||||
display: display@di0 {
|
||||
compatible = "fsl,imx-parallel-display";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_disp0_2>;
|
||||
interface-pix-fmt = "rgb24";
|
||||
status = "okay";
|
||||
|
||||
port {
|
||||
display0_in: endpoint {
|
||||
remote-endpoint = <&ipu1_di0_disp0>;
|
||||
};
|
||||
};
|
||||
|
||||
display-timings {
|
||||
native-mode = <&vga>;
|
||||
|
||||
vga: VGA {
|
||||
clock-frequency = <25200000>;
|
||||
hactive = <640>;
|
||||
vactive = <480>;
|
||||
hback-porch = <48>;
|
||||
hsync-len = <96>;
|
||||
hfront-porch = <16>;
|
||||
vback-porch = <31>;
|
||||
vsync-len = <2>;
|
||||
vfront-porch = <12>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <0>;
|
||||
};
|
||||
|
||||
ETV570 {
|
||||
clock-frequency = <25200000>;
|
||||
hactive = <640>;
|
||||
vactive = <480>;
|
||||
hback-porch = <114>;
|
||||
hsync-len = <30>;
|
||||
hfront-porch = <16>;
|
||||
vback-porch = <32>;
|
||||
vsync-len = <3>;
|
||||
vfront-porch = <10>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <0>;
|
||||
};
|
||||
|
||||
ET0350 {
|
||||
clock-frequency = <6413760>;
|
||||
hactive = <320>;
|
||||
vactive = <240>;
|
||||
hback-porch = <34>;
|
||||
hsync-len = <34>;
|
||||
hfront-porch = <20>;
|
||||
vback-porch = <15>;
|
||||
vsync-len = <3>;
|
||||
vfront-porch = <4>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <0>;
|
||||
};
|
||||
|
||||
ET0430 {
|
||||
clock-frequency = <9009000>;
|
||||
hactive = <480>;
|
||||
vactive = <272>;
|
||||
hback-porch = <2>;
|
||||
hsync-len = <41>;
|
||||
hfront-porch = <2>;
|
||||
vback-porch = <2>;
|
||||
vsync-len = <10>;
|
||||
vfront-porch = <2>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <1>;
|
||||
};
|
||||
|
||||
ET0500 {
|
||||
clock-frequency = <33264000>;
|
||||
hactive = <800>;
|
||||
vactive = <480>;
|
||||
hback-porch = <88>;
|
||||
hsync-len = <128>;
|
||||
hfront-porch = <40>;
|
||||
vback-porch = <33>;
|
||||
vsync-len = <2>;
|
||||
vfront-porch = <10>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <0>;
|
||||
};
|
||||
|
||||
ET0700 { /* same as ET0500 */
|
||||
clock-frequency = <33264000>;
|
||||
hactive = <800>;
|
||||
vactive = <480>;
|
||||
hback-porch = <88>;
|
||||
hsync-len = <128>;
|
||||
hfront-porch = <40>;
|
||||
vback-porch = <33>;
|
||||
vsync-len = <2>;
|
||||
vfront-porch = <10>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <0>;
|
||||
};
|
||||
|
||||
ETQ570 {
|
||||
clock-frequency = <6596040>;
|
||||
hactive = <320>;
|
||||
vactive = <240>;
|
||||
hback-porch = <38>;
|
||||
hsync-len = <30>;
|
||||
hfront-porch = <30>;
|
||||
vback-porch = <16>;
|
||||
vsync-len = <3>;
|
||||
vfront-porch = <4>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&ds1339 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&gpmi {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&ipu1_di0_disp0 {
|
||||
remote-endpoint = <&display0_in>;
|
||||
};
|
||||
|
||||
&ipu2 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
®_lcd0_pwr {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&usdhc4 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usdhc4>;
|
||||
bus-width = <4>;
|
||||
non-removable;
|
||||
no-1-8-v;
|
||||
fsl,wp-controller;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl_usdhc4: usdhc4grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD4_CMD__SD4_CMD 0x070b1
|
||||
MX6QDL_PAD_SD4_CLK__SD4_CLK 0x070b1
|
||||
MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x070b1
|
||||
MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x070b1
|
||||
MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x070b1
|
||||
MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x070b1
|
||||
MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x0b0b1
|
||||
>;
|
||||
};
|
||||
};
|
||||
@ -1,12 +1,42 @@
|
||||
/*
|
||||
* Copyright 2014 Lothar Waßmann <LW@KARO-electronics.de>
|
||||
* Copyright 2014-2016 Lothar Waßmann <LW@KARO-electronics.de>
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 at the following locations:
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
@ -77,17 +107,7 @@
|
||||
interrupt-parent = <&gpio3>;
|
||||
interrupts = <22 0>;
|
||||
wakeup-gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>;
|
||||
linux,wakeup;
|
||||
};
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
imx6q-tx6q-1110 {
|
||||
pinctrl_eeti: eetigrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b1 /* Interrupt */
|
||||
>;
|
||||
};
|
||||
wakeup-source;
|
||||
};
|
||||
};
|
||||
|
||||
@ -152,3 +172,11 @@
|
||||
&sata {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl_eeti: eetigrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b1 /* Interrupt */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
264
sys/gnu/dts/arm/imx6q-tx6q-11x0-mb7.dts
Normal file
264
sys/gnu/dts/arm/imx6q-tx6q-11x0-mb7.dts
Normal file
@ -0,0 +1,264 @@
|
||||
/*
|
||||
* Copyright 2016 Lothar Waßmann <LW@KARO-electronics.de>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "imx6q.dtsi"
|
||||
#include "imx6qdl-tx6.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Ka-Ro electronics TX6Q-1110/-1130 Module on MB7 baseboard";
|
||||
compatible = "karo,imx6q-tx6q", "fsl,imx6q";
|
||||
|
||||
aliases {
|
||||
display = &lvds0;
|
||||
ipu1 = &ipu2;
|
||||
lvds0 = &lvds0;
|
||||
lvds1 = &lvds1;
|
||||
};
|
||||
|
||||
backlight0: backlight0 {
|
||||
compatible = "pwm-backlight";
|
||||
pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>;
|
||||
power-supply = <®_lcd0_pwr>;
|
||||
/*
|
||||
* a poor man's way to create a 1:1 relationship between
|
||||
* the PWM value and the actual duty cycle
|
||||
*/
|
||||
brightness-levels = < 0 1 2 3 4 5 6 7 8 9
|
||||
10 11 12 13 14 15 16 17 18 19
|
||||
20 21 22 23 24 25 26 27 28 29
|
||||
30 31 32 33 34 35 36 37 38 39
|
||||
40 41 42 43 44 45 46 47 48 49
|
||||
50 51 52 53 54 55 56 57 58 59
|
||||
60 61 62 63 64 65 66 67 68 69
|
||||
70 71 72 73 74 75 76 77 78 79
|
||||
80 81 82 83 84 85 86 87 88 89
|
||||
90 91 92 93 94 95 96 97 98 99
|
||||
100>;
|
||||
default-brightness-level = <50>;
|
||||
};
|
||||
|
||||
backlight1: backlight1 {
|
||||
compatible = "pwm-backlight";
|
||||
pwms = <&pwm1 0 500000 PWM_POLARITY_INVERTED>;
|
||||
power-supply = <®_lcd1_pwr>;
|
||||
/*
|
||||
* a poor man's way to create a 1:1 relationship between
|
||||
* the PWM value and the actual duty cycle
|
||||
*/
|
||||
brightness-levels = < 0 1 2 3 4 5 6 7 8 9
|
||||
10 11 12 13 14 15 16 17 18 19
|
||||
20 21 22 23 24 25 26 27 28 29
|
||||
30 31 32 33 34 35 36 37 38 39
|
||||
40 41 42 43 44 45 46 47 48 49
|
||||
50 51 52 53 54 55 56 57 58 59
|
||||
60 61 62 63 64 65 66 67 68 69
|
||||
70 71 72 73 74 75 76 77 78 79
|
||||
80 81 82 83 84 85 86 87 88 89
|
||||
90 91 92 93 94 95 96 97 98 99
|
||||
100>;
|
||||
default-brightness-level = <50>;
|
||||
};
|
||||
};
|
||||
|
||||
&can1 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&can2 {
|
||||
xceiver-supply = <®_3v3>;
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
polytouch1: eeti@04 {
|
||||
compatible = "eeti,egalax_ts";
|
||||
reg = <0x04>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_eeti>;
|
||||
interrupts-extended = <&gpio3 22 IRQ_TYPE_EDGE_FALLING>;
|
||||
wakeup-gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>;
|
||||
wakeup-source;
|
||||
};
|
||||
};
|
||||
|
||||
&ipu2 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&kpp {
|
||||
status = "disabled"; /* pads partially clash with backlight1 PWM */
|
||||
};
|
||||
|
||||
&ldb {
|
||||
status = "okay";
|
||||
|
||||
lvds0: lvds-channel@0 {
|
||||
fsl,data-mapping = "spwg";
|
||||
fsl,data-width = <18>;
|
||||
status = "okay";
|
||||
|
||||
display-timings {
|
||||
native-mode = <&lvds0_timing1>;
|
||||
|
||||
lvds0_timing0: hsd100pxn1 {
|
||||
clock-frequency = <65000000>;
|
||||
hactive = <1024>;
|
||||
vactive = <768>;
|
||||
hback-porch = <220>;
|
||||
hfront-porch = <40>;
|
||||
vback-porch = <21>;
|
||||
vfront-porch = <7>;
|
||||
hsync-len = <60>;
|
||||
vsync-len = <10>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <1>;
|
||||
};
|
||||
|
||||
lvds0_timing1: VGA {
|
||||
clock-frequency = <25200000>;
|
||||
hactive = <640>;
|
||||
vactive = <480>;
|
||||
hback-porch = <48>;
|
||||
hfront-porch = <16>;
|
||||
vback-porch = <31>;
|
||||
vfront-porch = <12>;
|
||||
hsync-len = <96>;
|
||||
vsync-len = <2>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <0>;
|
||||
};
|
||||
|
||||
lvds0_timing2: nl12880bc20 {
|
||||
clock-frequency = <71000000>;
|
||||
hactive = <1280>;
|
||||
vactive = <800>;
|
||||
hback-porch = <50>;
|
||||
hfront-porch = <50>;
|
||||
vback-porch = <5>;
|
||||
vfront-porch = <5>;
|
||||
hsync-len = <60>;
|
||||
vsync-len = <13>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
lvds1: lvds-channel@1 {
|
||||
fsl,data-mapping = "spwg";
|
||||
fsl,data-width = <18>;
|
||||
status = "okay";
|
||||
|
||||
display-timings {
|
||||
native-mode = <&lvds1_timing2>;
|
||||
|
||||
lvds1_timing0: hsd100pxn1 {
|
||||
clock-frequency = <65000000>;
|
||||
hactive = <1024>;
|
||||
vactive = <768>;
|
||||
hback-porch = <220>;
|
||||
hfront-porch = <40>;
|
||||
vback-porch = <21>;
|
||||
vfront-porch = <7>;
|
||||
hsync-len = <60>;
|
||||
vsync-len = <10>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <1>;
|
||||
};
|
||||
|
||||
lvds1_timing1: VGA {
|
||||
clock-frequency = <25200000>;
|
||||
hactive = <640>;
|
||||
vactive = <480>;
|
||||
hback-porch = <48>;
|
||||
hfront-porch = <16>;
|
||||
vback-porch = <31>;
|
||||
vfront-porch = <12>;
|
||||
hsync-len = <96>;
|
||||
vsync-len = <2>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <0>;
|
||||
};
|
||||
|
||||
lvds1_timing2: nl12880bc20 {
|
||||
clock-frequency = <71000000>;
|
||||
hactive = <1280>;
|
||||
vactive = <800>;
|
||||
hback-porch = <50>;
|
||||
hfront-porch = <50>;
|
||||
vback-porch = <5>;
|
||||
vfront-porch = <5>;
|
||||
hsync-len = <60>;
|
||||
vsync-len = <13>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pwm1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sata {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl_eeti: eetigrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b1 /* Interrupt */
|
||||
>;
|
||||
};
|
||||
};
|
||||
@ -13,7 +13,7 @@
|
||||
#include "imx6qdl-wandboard-revb1.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Wandboard i.MX6 Quad Board";
|
||||
model = "Wandboard i.MX6 Quad Board rev B1";
|
||||
compatible = "wand,imx6q-wandboard", "fsl,imx6q";
|
||||
|
||||
memory {
|
||||
|
||||
@ -22,7 +22,7 @@
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
cpu0: cpu@0 {
|
||||
compatible = "arm,cortex-a9";
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
@ -154,21 +154,22 @@
|
||||
#size-cells = <0>;
|
||||
reg = <2>;
|
||||
|
||||
ipu2_di0_disp0: endpoint@0 {
|
||||
ipu2_di0_disp0: disp0-endpoint {
|
||||
};
|
||||
|
||||
ipu2_di0_hdmi: endpoint@1 {
|
||||
ipu2_di0_hdmi: hdmi-endpoint {
|
||||
remote-endpoint = <&hdmi_mux_2>;
|
||||
};
|
||||
|
||||
ipu2_di0_mipi: endpoint@2 {
|
||||
ipu2_di0_mipi: mipi-endpoint {
|
||||
remote-endpoint = <&mipi_mux_2>;
|
||||
};
|
||||
|
||||
ipu2_di0_lvds0: endpoint@3 {
|
||||
ipu2_di0_lvds0: lvds0-endpoint {
|
||||
remote-endpoint = <&lvds0_mux_2>;
|
||||
};
|
||||
|
||||
ipu2_di0_lvds1: endpoint@4 {
|
||||
ipu2_di0_lvds1: lvds1-endpoint {
|
||||
remote-endpoint = <&lvds1_mux_2>;
|
||||
};
|
||||
};
|
||||
@ -178,18 +179,19 @@
|
||||
#size-cells = <0>;
|
||||
reg = <3>;
|
||||
|
||||
ipu2_di1_hdmi: endpoint@1 {
|
||||
ipu2_di1_hdmi: hdmi-endpoint {
|
||||
remote-endpoint = <&hdmi_mux_3>;
|
||||
};
|
||||
|
||||
ipu2_di1_mipi: endpoint@2 {
|
||||
ipu2_di1_mipi: mipi-endpoint {
|
||||
remote-endpoint = <&mipi_mux_3>;
|
||||
};
|
||||
|
||||
ipu2_di1_lvds0: endpoint@3 {
|
||||
ipu2_di1_lvds0: lvds0-endpoint {
|
||||
remote-endpoint = <&lvds0_mux_3>;
|
||||
};
|
||||
|
||||
ipu2_di1_lvds1: endpoint@4 {
|
||||
ipu2_di1_lvds1: lvds1-endpoint {
|
||||
remote-endpoint = <&lvds1_mux_3>;
|
||||
};
|
||||
};
|
||||
|
||||
984
sys/gnu/dts/arm/imx6qdl-apalis.dtsi
Normal file
984
sys/gnu/dts/arm/imx6qdl-apalis.dtsi
Normal file
@ -0,0 +1,984 @@
|
||||
/*
|
||||
* Copyright 2014-2016 Toradex AG
|
||||
* Copyright 2012 Freescale Semiconductor, Inc.
|
||||
* Copyright 2011 Linaro Ltd.
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/ {
|
||||
model = "Toradex Apalis iMX6Q/D Module";
|
||||
compatible = "toradex,apalis_imx6q", "fsl,imx6q";
|
||||
|
||||
backlight: backlight {
|
||||
compatible = "pwm-backlight";
|
||||
pwms = <&pwm4 0 5000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* DDC_I2C: I2C2_SDA/SCL on MXM3 205/207 */
|
||||
i2cddc: i2c@0 {
|
||||
compatible = "i2c-gpio";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c_ddc>;
|
||||
gpios = <&gpio3 16 GPIO_ACTIVE_HIGH /* sda */
|
||||
&gpio2 30 GPIO_ACTIVE_HIGH /* scl */
|
||||
>;
|
||||
i2c-gpio,delay-us = <2>; /* ~100 kHz */
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
reg_1p8v: regulator-1p8v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "1P8V";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_2p5v: regulator-2p5v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "2P5V";
|
||||
regulator-min-microvolt = <2500000>;
|
||||
regulator-max-microvolt = <2500000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_3p3v: regulator-3p3v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "3P3V";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_usb_otg_vbus: regulator-usb-otg-vbus {
|
||||
compatible = "regulator-fixed";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_regulator_usbotg_pwr>;
|
||||
regulator-name = "usb_otg_vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* on module USB hub */
|
||||
reg_usb_host_vbus_hub: regulator-usb-host-vbus-hub {
|
||||
compatible = "regulator-fixed";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_regulator_usbhub_pwr>;
|
||||
regulator-name = "usb_host_vbus_hub";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
gpio = <&gpio3 28 GPIO_ACTIVE_HIGH>;
|
||||
startup-delay-us = <2000>;
|
||||
enable-active-high;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
reg_usb_host_vbus: regulator-usb-host-vbus {
|
||||
compatible = "regulator-fixed";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_regulator_usbh_pwr>;
|
||||
regulator-name = "usb_host_vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
vin-supply = <®_usb_host_vbus_hub>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sound {
|
||||
compatible = "fsl,imx-audio-sgtl5000";
|
||||
model = "imx6q-apalis-sgtl5000";
|
||||
ssi-controller = <&ssi1>;
|
||||
audio-codec = <&codec>;
|
||||
audio-routing =
|
||||
"LINE_IN", "Line In Jack",
|
||||
"MIC_IN", "Mic Jack",
|
||||
"Mic Jack", "Mic Bias",
|
||||
"Headphone Jack", "HP_OUT";
|
||||
mux-int-port = <1>;
|
||||
mux-ext-port = <4>;
|
||||
};
|
||||
|
||||
sound_spdif: sound-spdif {
|
||||
compatible = "fsl,imx-audio-spdif";
|
||||
model = "imx-spdif";
|
||||
spdif-controller = <&spdif>;
|
||||
spdif-in;
|
||||
spdif-out;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
&audmux {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_audmux>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&can1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_flexcan1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&can2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_flexcan2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* Apalis SPI1 */
|
||||
&ecspi1 {
|
||||
fsl,spi-num-chipselects = <1>;
|
||||
cs-gpios = <&gpio5 25 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ecspi1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* Apalis SPI2 */
|
||||
&ecspi2 {
|
||||
fsl,spi-num-chipselects = <1>;
|
||||
cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ecspi2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&fec {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_enet>;
|
||||
phy-mode = "rgmii";
|
||||
phy-handle = <ðphy>;
|
||||
phy-reset-duration = <10>;
|
||||
phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
|
||||
status = "okay";
|
||||
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ethphy: ethernet-phy@7 {
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <30 IRQ_TYPE_LEVEL_LOW>;
|
||||
reg = <7>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/*
|
||||
* GEN1_I2C: I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier
|
||||
* board)
|
||||
*/
|
||||
&i2c1 {
|
||||
clock-frequency = <100000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/*
|
||||
* PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
|
||||
* touch screen controller
|
||||
*/
|
||||
&i2c2 {
|
||||
clock-frequency = <100000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c2>;
|
||||
status = "okay";
|
||||
|
||||
pmic: pfuze100@08 {
|
||||
compatible = "fsl,pfuze100";
|
||||
reg = <0x08>;
|
||||
|
||||
regulators {
|
||||
sw1a_reg: sw1ab {
|
||||
regulator-min-microvolt = <300000>;
|
||||
regulator-max-microvolt = <1875000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-ramp-delay = <6250>;
|
||||
};
|
||||
|
||||
sw1c_reg: sw1c {
|
||||
regulator-min-microvolt = <300000>;
|
||||
regulator-max-microvolt = <1875000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-ramp-delay = <6250>;
|
||||
};
|
||||
|
||||
sw3a_reg: sw3a {
|
||||
regulator-min-microvolt = <400000>;
|
||||
regulator-max-microvolt = <1975000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
swbst_reg: swbst {
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5150000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
snvs_reg: vsnvs {
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vref_reg: vrefddr {
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vgen1_reg: vgen1 {
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <1550000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vgen2_reg: vgen2 {
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <1550000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vgen3_reg: vgen3 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vgen4_reg: vgen4 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vgen5_reg: vgen5 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vgen6_reg: vgen6 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
codec: sgtl5000@0a {
|
||||
compatible = "fsl,sgtl5000";
|
||||
reg = <0x0a>;
|
||||
clocks = <&clks IMX6QDL_CLK_CKO>;
|
||||
VDDA-supply = <®_2p5v>;
|
||||
VDDIO-supply = <®_3p3v>;
|
||||
};
|
||||
|
||||
/* STMPE811 touch screen controller */
|
||||
stmpe811@41 {
|
||||
compatible = "st,stmpe811";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_touch_int>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x41>;
|
||||
interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
|
||||
interrupt-parent = <&gpio4>;
|
||||
interrupt-controller;
|
||||
id = <0>;
|
||||
blocks = <0x5>;
|
||||
irq-trigger = <0x1>;
|
||||
|
||||
stmpe_touchscreen {
|
||||
compatible = "st,stmpe-ts";
|
||||
reg = <0>;
|
||||
/* 3.25 MHz ADC clock speed */
|
||||
st,adc-freq = <1>;
|
||||
/* 8 sample average control */
|
||||
st,ave-ctrl = <3>;
|
||||
/* 7 length fractional part in z */
|
||||
st,fraction-z = <7>;
|
||||
/*
|
||||
* 50 mA typical 80 mA max touchscreen drivers
|
||||
* current limit value
|
||||
*/
|
||||
st,i-drive = <1>;
|
||||
/* 12-bit ADC */
|
||||
st,mod-12b = <1>;
|
||||
/* internal ADC reference */
|
||||
st,ref-sel = <0>;
|
||||
/* ADC converstion time: 80 clocks */
|
||||
st,sample-time = <4>;
|
||||
/* 1 ms panel driver settling time */
|
||||
st,settling = <3>;
|
||||
/* 5 ms touch detect interrupt delay */
|
||||
st,touch-det-delay = <5>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/*
|
||||
* GEN2_I2C, CAM: I2C3_SDA/SCL on MXM3 201/203 (unused)
|
||||
*/
|
||||
&i2c3 {
|
||||
clock-frequency = <100000>;
|
||||
pinctrl-names = "default", "recovery";
|
||||
pinctrl-0 = <&pinctrl_i2c3>;
|
||||
pinctrl-1 = <&pinctrl_i2c3_recovery>;
|
||||
scl-gpios = <&gpio3 17 GPIO_ACTIVE_HIGH>;
|
||||
sda-gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&pwm1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pwm1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&pwm2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pwm2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&pwm3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pwm3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&pwm4 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pwm4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&spdif {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_spdif>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&ssi1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1_dte &pinctrl_uart1_ctrl>;
|
||||
fsl,dte-mode;
|
||||
fsl,uart-has-rtscts;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart2_dte>;
|
||||
fsl,dte-mode;
|
||||
fsl,uart-has-rtscts;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&uart4 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart4_dte>;
|
||||
fsl,dte-mode;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&uart5 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart5_dte>;
|
||||
fsl,dte-mode;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&usbotg {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usbotg>;
|
||||
disable-over-current;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* MMC1 */
|
||||
&usdhc1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usdhc1>;
|
||||
vqmmc-supply = <®_3p3v>;
|
||||
bus-width = <8>;
|
||||
voltage-ranges = <3300 3300>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* SD1 */
|
||||
&usdhc2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usdhc2>;
|
||||
vqmmc-supply = <®_3p3v>;
|
||||
bus-width = <4>;
|
||||
voltage-ranges = <3300 3300>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* eMMC */
|
||||
&usdhc3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usdhc3>;
|
||||
vqmmc-supply = <®_3p3v>;
|
||||
bus-width = <8>;
|
||||
voltage-ranges = <3300 3300>;
|
||||
non-removable;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&weim {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
/* pins used on module */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_reset_moci>;
|
||||
|
||||
pinctrl_apalis_gpio1: gpio2io04grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x130b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_apalis_gpio2: gpio2io05grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x130b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_apalis_gpio3: gpio2io06grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x130b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_apalis_gpio4: gpio2io07grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x130b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_apalis_gpio5: gpio6io10grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x130b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_apalis_gpio6: gpio6io09grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x130b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_apalis_gpio7: gpio1io02grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x130b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_apalis_gpio8: gpio1io06grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x130b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_audmux: audmuxgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0
|
||||
MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x130b0
|
||||
MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0
|
||||
MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0
|
||||
/* SGTL5000 sys_mclk */
|
||||
MX6QDL_PAD_GPIO_5__CCM_CLKO1 0x130b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_cam_mclk: cammclkgrp {
|
||||
fsl,pins = <
|
||||
/* CAM sys_mclk */
|
||||
MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x00b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_ecspi1: ecspi1grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_CSI0_DAT6__ECSPI1_MISO 0x100b1
|
||||
MX6QDL_PAD_CSI0_DAT5__ECSPI1_MOSI 0x100b1
|
||||
MX6QDL_PAD_CSI0_DAT4__ECSPI1_SCLK 0x100b1
|
||||
/* SPI1 cs */
|
||||
MX6QDL_PAD_CSI0_DAT7__GPIO5_IO25 0x000b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_ecspi2: ecspi2grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1
|
||||
MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1
|
||||
MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1
|
||||
/* SPI2 cs */
|
||||
MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x000b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_enet: enetgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0
|
||||
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0
|
||||
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0
|
||||
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0
|
||||
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0
|
||||
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0
|
||||
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0
|
||||
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0
|
||||
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0
|
||||
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
|
||||
/* Ethernet PHY reset */
|
||||
MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x000b0
|
||||
/* Ethernet PHY interrupt */
|
||||
MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x000b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_flexcan1: flexcan1grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0
|
||||
MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_flexcan2: flexcan2grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0
|
||||
MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_gpio_keys: gpio1io04grp {
|
||||
fsl,pins = <
|
||||
/* Power button */
|
||||
MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_hdmi_cec: hdmicecgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c_ddc: gpioi2cddcgrp {
|
||||
fsl,pins = <
|
||||
/* DDC bitbang */
|
||||
MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0
|
||||
MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c1: i2c1grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
|
||||
MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c2: i2c2grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
|
||||
MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c3: i2c3grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
|
||||
MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c3_recovery: i2c3recoverygrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_D17__GPIO3_IO17 0x4001b8b1
|
||||
MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x4001b8b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_ipu1_csi0: ipu1csi0grp { /* parallel camera */
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0xb0b1
|
||||
MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0xb0b1
|
||||
MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0xb0b1
|
||||
MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0xb0b1
|
||||
MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0xb0b1
|
||||
MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0xb0b1
|
||||
MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0xb0b1
|
||||
MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0xb0b1
|
||||
MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0xb0b1
|
||||
MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0xb0b1
|
||||
MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0xb0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_ipu1_lcdif: ipu1lcdifgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_A16__IPU1_DI1_DISP_CLK 0x61
|
||||
/* DE */
|
||||
MX6QDL_PAD_EIM_DA10__IPU1_DI1_PIN15 0x61
|
||||
/* HSync */
|
||||
MX6QDL_PAD_EIM_DA11__IPU1_DI1_PIN02 0x61
|
||||
/* VSync */
|
||||
MX6QDL_PAD_EIM_DA12__IPU1_DI1_PIN03 0x61
|
||||
MX6QDL_PAD_EIM_DA9__IPU1_DISP1_DATA00 0x61
|
||||
MX6QDL_PAD_EIM_DA8__IPU1_DISP1_DATA01 0x61
|
||||
MX6QDL_PAD_EIM_DA7__IPU1_DISP1_DATA02 0x61
|
||||
MX6QDL_PAD_EIM_DA6__IPU1_DISP1_DATA03 0x61
|
||||
MX6QDL_PAD_EIM_DA5__IPU1_DISP1_DATA04 0x61
|
||||
MX6QDL_PAD_EIM_DA4__IPU1_DISP1_DATA05 0x61
|
||||
MX6QDL_PAD_EIM_DA3__IPU1_DISP1_DATA06 0x61
|
||||
MX6QDL_PAD_EIM_DA2__IPU1_DISP1_DATA07 0x61
|
||||
MX6QDL_PAD_EIM_DA1__IPU1_DISP1_DATA08 0x61
|
||||
MX6QDL_PAD_EIM_DA0__IPU1_DISP1_DATA09 0x61
|
||||
MX6QDL_PAD_EIM_EB1__IPU1_DISP1_DATA10 0x61
|
||||
MX6QDL_PAD_EIM_EB0__IPU1_DISP1_DATA11 0x61
|
||||
MX6QDL_PAD_EIM_A17__IPU1_DISP1_DATA12 0x61
|
||||
MX6QDL_PAD_EIM_A18__IPU1_DISP1_DATA13 0x61
|
||||
MX6QDL_PAD_EIM_A19__IPU1_DISP1_DATA14 0x61
|
||||
MX6QDL_PAD_EIM_A20__IPU1_DISP1_DATA15 0x61
|
||||
MX6QDL_PAD_EIM_A21__IPU1_DISP1_DATA16 0x61
|
||||
MX6QDL_PAD_EIM_A22__IPU1_DISP1_DATA17 0x61
|
||||
MX6QDL_PAD_EIM_A23__IPU1_DISP1_DATA18 0x61
|
||||
MX6QDL_PAD_EIM_A24__IPU1_DISP1_DATA19 0x61
|
||||
MX6QDL_PAD_EIM_D31__IPU1_DISP1_DATA20 0x61
|
||||
MX6QDL_PAD_EIM_D30__IPU1_DISP1_DATA21 0x61
|
||||
MX6QDL_PAD_EIM_D26__IPU1_DISP1_DATA22 0x61
|
||||
MX6QDL_PAD_EIM_D27__IPU1_DISP1_DATA23 0x61
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_ipu2_vdac: ipu2vdacgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK 0xd1
|
||||
MX6QDL_PAD_DI0_PIN15__IPU2_DI0_PIN15 0xd1
|
||||
MX6QDL_PAD_DI0_PIN2__IPU2_DI0_PIN02 0xd1
|
||||
MX6QDL_PAD_DI0_PIN3__IPU2_DI0_PIN03 0xd1
|
||||
MX6QDL_PAD_DISP0_DAT0__IPU2_DISP0_DATA00 0xf9
|
||||
MX6QDL_PAD_DISP0_DAT1__IPU2_DISP0_DATA01 0xf9
|
||||
MX6QDL_PAD_DISP0_DAT2__IPU2_DISP0_DATA02 0xf9
|
||||
MX6QDL_PAD_DISP0_DAT3__IPU2_DISP0_DATA03 0xf9
|
||||
MX6QDL_PAD_DISP0_DAT4__IPU2_DISP0_DATA04 0xf9
|
||||
MX6QDL_PAD_DISP0_DAT5__IPU2_DISP0_DATA05 0xf9
|
||||
MX6QDL_PAD_DISP0_DAT6__IPU2_DISP0_DATA06 0xf9
|
||||
MX6QDL_PAD_DISP0_DAT7__IPU2_DISP0_DATA07 0xf9
|
||||
MX6QDL_PAD_DISP0_DAT8__IPU2_DISP0_DATA08 0xf9
|
||||
MX6QDL_PAD_DISP0_DAT9__IPU2_DISP0_DATA09 0xf9
|
||||
MX6QDL_PAD_DISP0_DAT10__IPU2_DISP0_DATA10 0xf9
|
||||
MX6QDL_PAD_DISP0_DAT11__IPU2_DISP0_DATA11 0xf9
|
||||
MX6QDL_PAD_DISP0_DAT12__IPU2_DISP0_DATA12 0xf9
|
||||
MX6QDL_PAD_DISP0_DAT13__IPU2_DISP0_DATA13 0xf9
|
||||
MX6QDL_PAD_DISP0_DAT14__IPU2_DISP0_DATA14 0xf9
|
||||
MX6QDL_PAD_DISP0_DAT15__IPU2_DISP0_DATA15 0xf9
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_mmc_cd: gpiommccdgrp {
|
||||
fsl,pins = <
|
||||
/* MMC1 CD */
|
||||
MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x000b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pwm1: pwm1grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pwm2: pwm2grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pwm3: pwm3grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pwm4: pwm4grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_regulator_usbh_pwr: gpioregusbhpwrgrp {
|
||||
fsl,pins = <
|
||||
/* USBH_EN */
|
||||
MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x0f058
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_regulator_usbhub_pwr: gpioregusbhubpwrgrp {
|
||||
fsl,pins = <
|
||||
/* USBH_HUB_EN */
|
||||
MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x0f058
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_regulator_usbotg_pwr: gpioregusbotgpwrgrp {
|
||||
fsl,pins = <
|
||||
/* USBO1 power en */
|
||||
MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x0f058
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_reset_moci: gpioresetmocigrp {
|
||||
fsl,pins = <
|
||||
/* RESET_MOCI control */
|
||||
MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x0f058
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_sd_cd: gpiosdcdgrp {
|
||||
fsl,pins = <
|
||||
/* SD1 CD */
|
||||
MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x000b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_spdif: spdifgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_GPIO_16__SPDIF_IN 0x1b0b0
|
||||
MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_touch_int: gpiotouchintgrp {
|
||||
fsl,pins = <
|
||||
/* STMPE811 interrupt */
|
||||
MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart1_dce: uart1dcegrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
|
||||
MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
/* DTE mode */
|
||||
pinctrl_uart1_dte: uart1dtegrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x1b0b1
|
||||
MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x1b0b1
|
||||
MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x1b0b1
|
||||
MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
/* Additional DTR, DSR, DCD */
|
||||
pinctrl_uart1_ctrl: uart1ctrlgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x1b0b0
|
||||
MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x1b0b0
|
||||
MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart2_dce: uart2dcegrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
|
||||
MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
/* DTE mode */
|
||||
pinctrl_uart2_dte: uart2dtegrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA 0x1b0b1
|
||||
MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA 0x1b0b1
|
||||
MX6QDL_PAD_SD4_DAT6__UART2_RTS_B 0x1b0b1
|
||||
MX6QDL_PAD_SD4_DAT5__UART2_CTS_B 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart4_dce: uart4dcegrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
|
||||
MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
/* DTE mode */
|
||||
pinctrl_uart4_dte: uart4dtegrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_KEY_COL0__UART4_RX_DATA 0x1b0b1
|
||||
MX6QDL_PAD_KEY_ROW0__UART4_TX_DATA 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart5_dce: uart5dcegrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
|
||||
MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
/* DTE mode */
|
||||
pinctrl_uart5_dte: uart5dtegrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_KEY_COL1__UART5_RX_DATA 0x1b0b1
|
||||
MX6QDL_PAD_KEY_ROW1__UART5_TX_DATA 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usbotg: usbotggrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1: usdhc1grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071
|
||||
MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071
|
||||
MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071
|
||||
MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071
|
||||
MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071
|
||||
MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071
|
||||
MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x17071
|
||||
MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x17071
|
||||
MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x17071
|
||||
MX6QDL_PAD_NANDF_D3__SD1_DATA7 0x17071
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2: usdhc2grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17071
|
||||
MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10071
|
||||
MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17071
|
||||
MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17071
|
||||
MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17071
|
||||
MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17071
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3: usdhc3grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
|
||||
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
|
||||
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
|
||||
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
|
||||
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
|
||||
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
|
||||
MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
|
||||
MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
|
||||
MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
|
||||
MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
|
||||
/* eMMC reset */
|
||||
MX6QDL_PAD_SD3_RST__SD3_RESET 0x17059
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3_100mhz: usdhc3100mhzgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
|
||||
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9
|
||||
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
|
||||
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
|
||||
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
|
||||
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
|
||||
MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9
|
||||
MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9
|
||||
MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9
|
||||
MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9
|
||||
/* eMMC reset */
|
||||
MX6QDL_PAD_SD3_RST__SD3_RESET 0x170b9
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3_200mhz: usdhc3200mhzgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
|
||||
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
|
||||
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
|
||||
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
|
||||
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
|
||||
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
|
||||
MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9
|
||||
MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9
|
||||
MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9
|
||||
MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9
|
||||
/* eMMC reset */
|
||||
MX6QDL_PAD_SD3_RST__SD3_RESET 0x170f9
|
||||
>;
|
||||
};
|
||||
};
|
||||
@ -320,13 +320,13 @@
|
||||
|
||||
pinctrl_pwm3: pwm3grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
|
||||
MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pwm4: pwm4grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1
|
||||
MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
|
||||
@ -244,7 +244,7 @@
|
||||
codec: sgtl5000@0a {
|
||||
compatible = "fsl,sgtl5000";
|
||||
reg = <0x0a>;
|
||||
clocks = <&clks 201>;
|
||||
clocks = <&clks IMX6QDL_CLK_CKO>;
|
||||
VDDA-supply = <®_1p8v>;
|
||||
VDDIO-supply = <®_3p3v>;
|
||||
};
|
||||
@ -473,7 +473,7 @@
|
||||
|
||||
pinctrl_pwm3: pwm3grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
|
||||
MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
|
||||
@ -237,7 +237,7 @@
|
||||
codec: sgtl5000@0a {
|
||||
compatible = "fsl,sgtl5000";
|
||||
reg = <0x0a>;
|
||||
clocks = <&clks 201>;
|
||||
clocks = <&clks IMX6QDL_CLK_CKO>;
|
||||
VDDA-supply = <®_1p8v>;
|
||||
VDDIO-supply = <®_3p3v>;
|
||||
};
|
||||
@ -462,7 +462,7 @@
|
||||
|
||||
pinctrl_pwm3: pwm3grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
|
||||
MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
|
||||
@ -328,7 +328,7 @@
|
||||
codec: sgtl5000@0a {
|
||||
compatible = "fsl,sgtl5000";
|
||||
reg = <0x0a>;
|
||||
clocks = <&clks 201>;
|
||||
clocks = <&clks IMX6QDL_CLK_CKO>;
|
||||
VDDA-supply = <&sw4_reg>;
|
||||
VDDIO-supply = <®_3p3v>;
|
||||
};
|
||||
@ -397,8 +397,9 @@
|
||||
};
|
||||
|
||||
&pwm4 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pwm4>;
|
||||
pinctrl-names = "default", "state_dio";
|
||||
pinctrl-0 = <&pinctrl_pwm4_backlight>;
|
||||
pinctrl-1 = <&pinctrl_pwm4_dio>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@ -573,12 +574,20 @@
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pwm4: pwm4grp {
|
||||
pinctrl_pwm4_backlight: pwm4grpbacklight {
|
||||
fsl,pins = <
|
||||
/* LVDS_PWM J6.5 */
|
||||
MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pwm4_dio: pwm4grpdio {
|
||||
fsl,pins = <
|
||||
/* DIO3 J16.4 */
|
||||
MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart1: uart1grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
|
||||
|
||||
411
sys/gnu/dts/arm/imx6qdl-icore-rqs.dtsi
Normal file
411
sys/gnu/dts/arm/imx6qdl-icore-rqs.dtsi
Normal file
@ -0,0 +1,411 @@
|
||||
/*
|
||||
* Copyright (C) 2015 Amarula Solutions B.V.
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/clock/imx6qdl-clock.h>
|
||||
|
||||
/ {
|
||||
memory {
|
||||
reg = <0x10000000 0x80000000>;
|
||||
};
|
||||
|
||||
reg_1p8v: regulator-1p8v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "1P8V";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_2p5v: regulator-2p5v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "2P5V";
|
||||
regulator-min-microvolt = <2500000>;
|
||||
regulator-max-microvolt = <2500000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_3p3v: regulator-3p3v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "3P3V";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_sd3_vmmc: regulator-sd3-vmmc {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "P3V3_SD3_SWITCHED";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
gpio = <&gpio1 4 GPIO_ACTIVE_LOW>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
reg_sd4_vmmc: regulator-sd4-vmmc {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "P3V3_SD4_SWITCHED";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_usb_h1_vbus: regulator-usb-h1-vbus {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "usb_h1_vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_usb_otg_vbus: regulator-usb-otg-vbus {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "usb_otg_vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
usb_hub: usb-hub {
|
||||
compatible = "smsc,usb3503a";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usbhub>;
|
||||
reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
|
||||
clocks = <&clks IMX6QDL_CLK_LVDS2_GATE>;
|
||||
clock-names = "refclk";
|
||||
};
|
||||
};
|
||||
|
||||
&clks {
|
||||
assigned-clocks = <&clks IMX6QDL_CLK_LVDS2_SEL>;
|
||||
assigned-clock-parents = <&clks IMX6QDL_CLK_OSC>;
|
||||
};
|
||||
|
||||
&audmux {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_audmux>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fec {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_enet>;
|
||||
phy-handle = <ð_phy>;
|
||||
phy-mode = "rgmii";
|
||||
status = "okay";
|
||||
|
||||
mdio {
|
||||
eth_phy: ethernet-phy {
|
||||
rxc-skew-ps = <1140>;
|
||||
txc-skew-ps = <1140>;
|
||||
txen-skew-ps = <600>;
|
||||
rxdv-skew-ps = <240>;
|
||||
rxd0-skew-ps = <420>;
|
||||
rxd1-skew-ps = <600>;
|
||||
rxd2-skew-ps = <420>;
|
||||
rxd3-skew-ps = <240>;
|
||||
txd0-skew-ps = <60>;
|
||||
txd1-skew-ps = <60>;
|
||||
txd2-skew-ps = <60>;
|
||||
txd3-skew-ps = <240>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
clock-frequency = <100000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
clock-frequency = <100000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pcie>;
|
||||
reset-gpio = <&gpio3 29 GPIO_ACTIVE_LOW>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ssi1 {
|
||||
fsl,mode = "i2s-slave";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart4 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart4>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbh1 {
|
||||
vbus-supply = <®_usb_h1_vbus>;
|
||||
disable-over-current;
|
||||
clocks = <&clks IMX6QDL_CLK_USBOH3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbotg {
|
||||
vbus-supply = <®_usb_otg_vbus>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usbotg>;
|
||||
disable-over-current;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usdhc1>;
|
||||
no-1-8-v;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc3 {
|
||||
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
||||
pinctrl-0 = <&pinctrl_usdhc3>;
|
||||
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
|
||||
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
|
||||
vmcc-supply = <®_sd3_vmmc>;
|
||||
cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
|
||||
bus-witdh=<4>;
|
||||
no-1-8-v;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc4 {
|
||||
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
||||
pinctrl-0 = <&pinctrl_usdhc4>;
|
||||
pinctrl-1 = <&pinctrl_usdhc4_100mhz>;
|
||||
pinctrl-2 = <&pinctrl_usdhc4_200mhz>;
|
||||
vmcc-supply = <®_sd4_vmmc>;
|
||||
bus-witdh=<8>;
|
||||
no-1-8-v;
|
||||
non-removable;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl_audmux: audmux {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0
|
||||
MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x110b0
|
||||
MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0
|
||||
MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_enet: enetgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
|
||||
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
|
||||
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
|
||||
MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c1: i2c1grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
|
||||
MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c2: i2c2grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
|
||||
MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c3: i2c3grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
|
||||
MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
|
||||
MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pcie: pciegrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1f059 /* PCIe Reset */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart4: uart4grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
|
||||
MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usbhub: usbhubgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1f059 /* HUB USB Reset */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usbotg: usbotggrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1: usdhc1grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071
|
||||
MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071
|
||||
MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071
|
||||
MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071
|
||||
MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071
|
||||
MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3: usdhc3grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17070
|
||||
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10070
|
||||
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17070
|
||||
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17070
|
||||
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17070
|
||||
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17070
|
||||
MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x1f059 /* CD */
|
||||
MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1f059 /* PWR */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170B1
|
||||
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100B1
|
||||
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170B1
|
||||
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170B1
|
||||
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170B1
|
||||
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170B1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170F9
|
||||
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100F9
|
||||
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170F9
|
||||
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170F9
|
||||
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170F9
|
||||
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170F9
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc4: usdhc4grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17070
|
||||
MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10070
|
||||
MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17070
|
||||
MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17070
|
||||
MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17070
|
||||
MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17070
|
||||
MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17070
|
||||
MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17070
|
||||
MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17070
|
||||
MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17070
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc4_100mhz: usdhc4grp_100mhz {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD4_CMD__SD4_CMD 0x170B1
|
||||
MX6QDL_PAD_SD4_CLK__SD4_CLK 0x100B1
|
||||
MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x170B1
|
||||
MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x170B1
|
||||
MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x170B1
|
||||
MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x170B1
|
||||
MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x170B1
|
||||
MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x170B1
|
||||
MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x170B1
|
||||
MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x170B1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc4_200mhz: usdhc4grp_200mhz {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD4_CMD__SD4_CMD 0x170F9
|
||||
MX6QDL_PAD_SD4_CLK__SD4_CLK 0x100F9
|
||||
MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x170F9
|
||||
MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x170F9
|
||||
MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x170F9
|
||||
MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x170F9
|
||||
MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x170F9
|
||||
MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x170F9
|
||||
MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x170F9
|
||||
MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x170F9
|
||||
>;
|
||||
};
|
||||
};
|
||||
@ -119,7 +119,7 @@
|
||||
label = "Power Button";
|
||||
gpios = <&gpio2 3 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_POWER>;
|
||||
gpio-key,wakeup;
|
||||
wakeup-source;
|
||||
};
|
||||
|
||||
menu {
|
||||
@ -304,7 +304,7 @@
|
||||
codec: sgtl5000@0a {
|
||||
compatible = "fsl,sgtl5000";
|
||||
reg = <0x0a>;
|
||||
clocks = <&clks 201>;
|
||||
clocks = <&clks IMX6QDL_CLK_CKO>;
|
||||
VDDA-supply = <®_2p5v>;
|
||||
VDDIO-supply = <®_3p3v>;
|
||||
};
|
||||
|
||||
@ -126,7 +126,7 @@
|
||||
codec: sgtl5000@0a {
|
||||
compatible = "fsl,sgtl5000";
|
||||
reg = <0x0a>;
|
||||
clocks = <&clks 201>;
|
||||
clocks = <&clks IMX6QDL_CLK_CKO>;
|
||||
VDDA-supply = <®_3p3v>;
|
||||
VDDIO-supply = <®_3p3v>;
|
||||
};
|
||||
|
||||
@ -105,7 +105,7 @@
|
||||
label = "Power Button";
|
||||
gpios = <&gpio2 3 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_POWER>;
|
||||
gpio-key,wakeup;
|
||||
wakeup-source;
|
||||
};
|
||||
|
||||
menu {
|
||||
@ -290,7 +290,7 @@
|
||||
codec: sgtl5000@0a {
|
||||
compatible = "fsl,sgtl5000";
|
||||
reg = <0x0a>;
|
||||
clocks = <&clks 201>;
|
||||
clocks = <&clks IMX6QDL_CLK_CKO>;
|
||||
VDDA-supply = <®_2p5v>;
|
||||
VDDIO-supply = <®_3p3v>;
|
||||
};
|
||||
|
||||
@ -79,21 +79,21 @@
|
||||
power {
|
||||
label = "Power Button";
|
||||
gpios = <&gpio3 29 GPIO_ACTIVE_LOW>;
|
||||
gpio-key,wakeup;
|
||||
wakeup-source;
|
||||
linux,code = <KEY_POWER>;
|
||||
};
|
||||
|
||||
volume-up {
|
||||
label = "Volume Up";
|
||||
gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
|
||||
gpio-key,wakeup;
|
||||
wakeup-source;
|
||||
linux,code = <KEY_VOLUMEUP>;
|
||||
};
|
||||
|
||||
volume-down {
|
||||
label = "Volume Down";
|
||||
gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
|
||||
gpio-key,wakeup;
|
||||
wakeup-source;
|
||||
linux,code = <KEY_VOLUMEDOWN>;
|
||||
};
|
||||
};
|
||||
@ -115,7 +115,7 @@
|
||||
mux-ext-port = <3>;
|
||||
};
|
||||
|
||||
backlight {
|
||||
backlight_lvds: backlight-lvds {
|
||||
compatible = "pwm-backlight";
|
||||
pwms = <&pwm1 0 5000000>;
|
||||
brightness-levels = <0 4 8 16 32 64 128 255>;
|
||||
@ -133,6 +133,17 @@
|
||||
default-state = "on";
|
||||
};
|
||||
};
|
||||
|
||||
panel {
|
||||
compatible = "hannstar,hsd100pxn1";
|
||||
backlight = <&backlight_lvds>;
|
||||
|
||||
port {
|
||||
panel_in: endpoint {
|
||||
remote-endpoint = <&lvds0_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&audmux {
|
||||
@ -238,6 +249,7 @@
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-ramp-delay = <6250>;
|
||||
};
|
||||
|
||||
sw3a_reg: sw3a {
|
||||
@ -508,18 +520,11 @@
|
||||
fsl,data-width = <18>;
|
||||
status = "okay";
|
||||
|
||||
display-timings {
|
||||
native-mode = <&timing0>;
|
||||
timing0: hsd100pxn1 {
|
||||
clock-frequency = <65000000>;
|
||||
hactive = <1024>;
|
||||
vactive = <768>;
|
||||
hback-porch = <220>;
|
||||
hfront-porch = <40>;
|
||||
vback-porch = <21>;
|
||||
vfront-porch = <7>;
|
||||
hsync-len = <60>;
|
||||
vsync-len = <10>;
|
||||
port@4 {
|
||||
reg = <4>;
|
||||
|
||||
lvds0_out: endpoint {
|
||||
remote-endpoint = <&panel_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -1,12 +1,42 @@
|
||||
/*
|
||||
* Copyright 2014 Lothar Waßmann <LW@KARO-electronics.de>
|
||||
* Copyright 2014-2016 Lothar Waßmann <LW@KARO-electronics.de>
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 at the following locations:
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
@ -37,11 +67,12 @@
|
||||
clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
mclk: clock@0 {
|
||||
compatible = "fixed-clock";
|
||||
reg = <0>;
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <27000000>;
|
||||
clock-frequency = <26000000>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -52,7 +83,7 @@
|
||||
label = "Power Button";
|
||||
gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>;
|
||||
linux,code = <KEY_POWER>;
|
||||
gpio-key,wakeup;
|
||||
wakeup-source;
|
||||
};
|
||||
};
|
||||
|
||||
@ -61,109 +92,95 @@
|
||||
|
||||
user_led: user {
|
||||
label = "Heartbeat";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_user_led>;
|
||||
gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
};
|
||||
|
||||
regulators {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg_3v3_etn: regulator-3v3-etn {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "3V3_ETN";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_etnphy_power>;
|
||||
gpio = <&gpio3 20 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
reg_3v3_etn: regulator@0 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <0>;
|
||||
regulator-name = "3V3_ETN";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_etnphy_power>;
|
||||
gpio = <&gpio3 20 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
reg_2v5: regulator-2v5 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "2V5";
|
||||
regulator-min-microvolt = <2500000>;
|
||||
regulator-max-microvolt = <2500000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_2v5: regulator@1 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <1>;
|
||||
regulator-name = "2V5";
|
||||
regulator-min-microvolt = <2500000>;
|
||||
regulator-max-microvolt = <2500000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
reg_3v3: regulator-3v3 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "3V3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_3v3: regulator@2 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <2>;
|
||||
regulator-name = "3V3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
reg_can_xcvr: regulator-can-xcvr {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "CAN XCVR";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_flexcan_xcvr>;
|
||||
gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-low;
|
||||
};
|
||||
|
||||
reg_can_xcvr: regulator@3 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <3>;
|
||||
regulator-name = "CAN XCVR";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_flexcan_xcvr>;
|
||||
gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-low;
|
||||
};
|
||||
reg_lcd0_pwr: regulator-lcd0-pwr {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "LCD0 POWER";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_lcd0_pwr>;
|
||||
gpio = <&gpio3 29 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
reg_lcd0_pwr: regulator@4 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <4>;
|
||||
regulator-name = "LCD0 POWER";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_lcd0_pwr>;
|
||||
gpio = <&gpio3 29 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
reg_lcd1_pwr: regulator-lcd1-pwr {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "LCD1 POWER";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_lcd1_pwr>;
|
||||
gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
reg_lcd1_pwr: regulator@5 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <5>;
|
||||
regulator-name = "LCD1 POWER";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_lcd1_pwr>;
|
||||
gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
reg_usbh1_vbus: regulator-usbh1-vbus {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "usbh1_vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usbh1_vbus>;
|
||||
gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
reg_usbh1_vbus: regulator@6 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <6>;
|
||||
regulator-name = "usbh1_vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usbh1_vbus>;
|
||||
gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
reg_usbotg_vbus: regulator@7 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <7>;
|
||||
regulator-name = "usbotg_vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usbotg_vbus>;
|
||||
gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
reg_usbotg_vbus: regulator-usbotg-vbus {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "usbotg_vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usbotg_vbus>;
|
||||
gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
sound {
|
||||
@ -209,7 +226,7 @@
|
||||
&gpio2 30 GPIO_ACTIVE_HIGH
|
||||
&gpio3 19 GPIO_ACTIVE_HIGH
|
||||
>;
|
||||
status = "okay";
|
||||
status = "disabled";
|
||||
|
||||
spidev0: spi@0 {
|
||||
compatible = "spidev";
|
||||
@ -227,10 +244,29 @@
|
||||
&fec {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_enet>;
|
||||
clocks = <&clks IMX6QDL_CLK_ENET>,
|
||||
<&clks IMX6QDL_CLK_ENET>,
|
||||
<&clks IMX6QDL_CLK_ENET_REF>,
|
||||
<&clks IMX6QDL_CLK_ENET_REF>;
|
||||
clock-names = "ipg", "ahb", "ptp", "enet_out";
|
||||
phy-mode = "rmii";
|
||||
phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_HIGH>;
|
||||
phy-handle = <&etnphy>;
|
||||
phy-supply = <®_3v3_etn>;
|
||||
status = "okay";
|
||||
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
etnphy: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_enet_mdio>;
|
||||
interrupts-extended = <&gpio7 1 IRQ_TYPE_EDGE_FALLING>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&gpmi {
|
||||
@ -276,7 +312,7 @@
|
||||
interrupts = <15 IRQ_TYPE_EDGE_FALLING>;
|
||||
reset-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>;
|
||||
wake-gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
|
||||
linux,wakeup;
|
||||
wakeup-source;
|
||||
};
|
||||
|
||||
touchscreen: tsc2007@48 {
|
||||
@ -288,7 +324,7 @@
|
||||
interrupts = <26 0>;
|
||||
gpios = <&gpio3 26 GPIO_ACTIVE_LOW>;
|
||||
ti,x-plate-ohms = <660>;
|
||||
linux,wakeup;
|
||||
wakeup-source;
|
||||
};
|
||||
};
|
||||
|
||||
@ -296,310 +332,318 @@
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_hog>;
|
||||
|
||||
imx6qdl-tx6 {
|
||||
pinctrl_hog: hoggrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b0b1 /* LED */
|
||||
MX6QDL_PAD_SD3_DAT2__GPIO7_IO06 0x1b0b1 /* ETN PHY RESET */
|
||||
MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b1 /* ETN PHY INT */
|
||||
MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b1 /* PWR BTN */
|
||||
>;
|
||||
};
|
||||
pinctrl_hog: hoggrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD3_DAT2__GPIO7_IO06 0x1b0b1 /* ETN PHY RESET */
|
||||
MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b1 /* ETN PHY INT */
|
||||
MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b1 /* PWR BTN */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_audmux: audmuxgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_KEY_ROW1__AUD5_RXD 0x130b0 /* SSI1_RXD */
|
||||
MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x110b0 /* SSI1_TXD */
|
||||
MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0 /* SSI1_CLK */
|
||||
MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0 /* SSI1_FS */
|
||||
>;
|
||||
};
|
||||
pinctrl_audmux: audmuxgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_KEY_ROW1__AUD5_RXD 0x130b0 /* SSI1_RXD */
|
||||
MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x110b0 /* SSI1_TXD */
|
||||
MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0 /* SSI1_CLK */
|
||||
MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0 /* SSI1_FS */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_disp0_1: disp0grp-1 {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
|
||||
MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
|
||||
MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
|
||||
MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
|
||||
/* PAD DISP0_DAT0 is used for the Flexcan transceiver control */
|
||||
MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
|
||||
MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
|
||||
MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
|
||||
MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
|
||||
MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
|
||||
MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
|
||||
MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
|
||||
MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
|
||||
MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
|
||||
MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
|
||||
MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
|
||||
MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
|
||||
MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
|
||||
MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
|
||||
MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
|
||||
MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
|
||||
MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
|
||||
MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
|
||||
MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
|
||||
MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
|
||||
MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
|
||||
MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
|
||||
MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
|
||||
>;
|
||||
};
|
||||
pinctrl_disp0_1: disp0grp-1 {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
|
||||
MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
|
||||
MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
|
||||
MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
|
||||
/* PAD DISP0_DAT0 is used for the Flexcan transceiver control */
|
||||
MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
|
||||
MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
|
||||
MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
|
||||
MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
|
||||
MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
|
||||
MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
|
||||
MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
|
||||
MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
|
||||
MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
|
||||
MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
|
||||
MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
|
||||
MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
|
||||
MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
|
||||
MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
|
||||
MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
|
||||
MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
|
||||
MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
|
||||
MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
|
||||
MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
|
||||
MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
|
||||
MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
|
||||
MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
|
||||
MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_disp0_2: disp0grp-2 {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
|
||||
MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
|
||||
MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
|
||||
MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
|
||||
MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
|
||||
MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
|
||||
MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
|
||||
MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
|
||||
MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
|
||||
MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
|
||||
MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
|
||||
MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
|
||||
MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
|
||||
MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
|
||||
MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
|
||||
MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
|
||||
MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
|
||||
MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
|
||||
MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
|
||||
MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
|
||||
MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
|
||||
MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
|
||||
MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
|
||||
MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
|
||||
MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
|
||||
MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
|
||||
MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
|
||||
MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
|
||||
>;
|
||||
};
|
||||
pinctrl_disp0_2: disp0grp-2 {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
|
||||
MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
|
||||
MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
|
||||
MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
|
||||
MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
|
||||
MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
|
||||
MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
|
||||
MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
|
||||
MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
|
||||
MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
|
||||
MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
|
||||
MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
|
||||
MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
|
||||
MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
|
||||
MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
|
||||
MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
|
||||
MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
|
||||
MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
|
||||
MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
|
||||
MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
|
||||
MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
|
||||
MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
|
||||
MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
|
||||
MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
|
||||
MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
|
||||
MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
|
||||
MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
|
||||
MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_ecspi1: ecspi1grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x0b0b0
|
||||
MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x0b0b0
|
||||
MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x0b0b0
|
||||
MX6QDL_PAD_GPIO_19__ECSPI1_RDY 0x0b0b0
|
||||
MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x0b0b0 /* SPI CS0 */
|
||||
MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x0b0b0 /* SPI CS1 */
|
||||
>;
|
||||
};
|
||||
pinctrl_ecspi1: ecspi1grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x0b0b0
|
||||
MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x0b0b0
|
||||
MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x0b0b0
|
||||
MX6QDL_PAD_GPIO_19__ECSPI1_RDY 0x0b0b0
|
||||
MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x0b0b0 /* SPI CS0 */
|
||||
MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x0b0b0 /* SPI CS1 */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_edt_ft5x06: edt-ft5x06grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0 /* Interrupt */
|
||||
MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b0 /* Reset */
|
||||
MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b0 /* Wake */
|
||||
>;
|
||||
};
|
||||
pinctrl_edt_ft5x06: edt-ft5x06grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0 /* Interrupt */
|
||||
MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b0 /* Reset */
|
||||
MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b0 /* Wake */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_enet: enetgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
|
||||
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
|
||||
MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0
|
||||
MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0
|
||||
MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0
|
||||
MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
|
||||
MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0
|
||||
MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0
|
||||
MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
|
||||
>;
|
||||
};
|
||||
pinctrl_enet: enetgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0
|
||||
MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0
|
||||
MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0
|
||||
MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
|
||||
MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0
|
||||
MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0
|
||||
MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_etnphy_power: etnphy-pwrgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b1 /* ETN PHY POWER */
|
||||
>;
|
||||
};
|
||||
pinctrl_enet_mdio: enet-mdiogrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
|
||||
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_flexcan1: flexcan1grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0
|
||||
MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0
|
||||
>;
|
||||
};
|
||||
pinctrl_etnphy_power: etnphy-pwrgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b1 /* ETN PHY POWER */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_flexcan2: flexcan2grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0
|
||||
MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0
|
||||
>;
|
||||
};
|
||||
pinctrl_flexcan1: flexcan1grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0
|
||||
MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_flexcan_xcvr: flexcan-xcvrgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21 0x1b0b0 /* Flexcan XCVR enable */
|
||||
>;
|
||||
};
|
||||
pinctrl_flexcan2: flexcan2grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0
|
||||
MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_gpmi_nand: gpminandgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_NANDF_CLE__NAND_CLE 0x0b0b1
|
||||
MX6QDL_PAD_NANDF_ALE__NAND_ALE 0x0b0b1
|
||||
MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0x0b0b1
|
||||
MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0x0b000
|
||||
MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0x0b0b1
|
||||
MX6QDL_PAD_SD4_CMD__NAND_RE_B 0x0b0b1
|
||||
MX6QDL_PAD_SD4_CLK__NAND_WE_B 0x0b0b1
|
||||
MX6QDL_PAD_NANDF_D0__NAND_DATA00 0x0b0b1
|
||||
MX6QDL_PAD_NANDF_D1__NAND_DATA01 0x0b0b1
|
||||
MX6QDL_PAD_NANDF_D2__NAND_DATA02 0x0b0b1
|
||||
MX6QDL_PAD_NANDF_D3__NAND_DATA03 0x0b0b1
|
||||
MX6QDL_PAD_NANDF_D4__NAND_DATA04 0x0b0b1
|
||||
MX6QDL_PAD_NANDF_D5__NAND_DATA05 0x0b0b1
|
||||
MX6QDL_PAD_NANDF_D6__NAND_DATA06 0x0b0b1
|
||||
MX6QDL_PAD_NANDF_D7__NAND_DATA07 0x0b0b1
|
||||
>;
|
||||
};
|
||||
pinctrl_flexcan_xcvr: flexcan-xcvrgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21 0x1b0b0 /* Flexcan XCVR enable */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c1: i2c1grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
|
||||
MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
|
||||
>;
|
||||
};
|
||||
pinctrl_gpmi_nand: gpminandgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_NANDF_CLE__NAND_CLE 0x0b0b1
|
||||
MX6QDL_PAD_NANDF_ALE__NAND_ALE 0x0b0b1
|
||||
MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0x0b0b1
|
||||
MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0x0b000
|
||||
MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0x0b0b1
|
||||
MX6QDL_PAD_SD4_CMD__NAND_RE_B 0x0b0b1
|
||||
MX6QDL_PAD_SD4_CLK__NAND_WE_B 0x0b0b1
|
||||
MX6QDL_PAD_NANDF_D0__NAND_DATA00 0x0b0b1
|
||||
MX6QDL_PAD_NANDF_D1__NAND_DATA01 0x0b0b1
|
||||
MX6QDL_PAD_NANDF_D2__NAND_DATA02 0x0b0b1
|
||||
MX6QDL_PAD_NANDF_D3__NAND_DATA03 0x0b0b1
|
||||
MX6QDL_PAD_NANDF_D4__NAND_DATA04 0x0b0b1
|
||||
MX6QDL_PAD_NANDF_D5__NAND_DATA05 0x0b0b1
|
||||
MX6QDL_PAD_NANDF_D6__NAND_DATA06 0x0b0b1
|
||||
MX6QDL_PAD_NANDF_D7__NAND_DATA07 0x0b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c3: i2c3grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
|
||||
MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
|
||||
>;
|
||||
};
|
||||
pinctrl_i2c1: i2c1grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
|
||||
MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_kpp: kppgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_GPIO_9__KEY_COL6 0x1b0b1
|
||||
MX6QDL_PAD_GPIO_4__KEY_COL7 0x1b0b1
|
||||
MX6QDL_PAD_KEY_COL2__KEY_COL2 0x1b0b1
|
||||
MX6QDL_PAD_KEY_COL3__KEY_COL3 0x1b0b1
|
||||
MX6QDL_PAD_GPIO_2__KEY_ROW6 0x1b0b1
|
||||
MX6QDL_PAD_GPIO_5__KEY_ROW7 0x1b0b1
|
||||
MX6QDL_PAD_KEY_ROW2__KEY_ROW2 0x1b0b1
|
||||
MX6QDL_PAD_KEY_ROW3__KEY_ROW3 0x1b0b1
|
||||
>;
|
||||
};
|
||||
pinctrl_i2c3: i2c3grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
|
||||
MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_lcd0_pwr: lcd0-pwrgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b1 /* LCD Reset */
|
||||
>;
|
||||
};
|
||||
pinctrl_kpp: kppgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_GPIO_9__KEY_COL6 0x1b0b1
|
||||
MX6QDL_PAD_GPIO_4__KEY_COL7 0x1b0b1
|
||||
MX6QDL_PAD_KEY_COL2__KEY_COL2 0x1b0b1
|
||||
MX6QDL_PAD_KEY_COL3__KEY_COL3 0x1b0b1
|
||||
MX6QDL_PAD_GPIO_2__KEY_ROW6 0x1b0b1
|
||||
MX6QDL_PAD_GPIO_5__KEY_ROW7 0x1b0b1
|
||||
MX6QDL_PAD_KEY_ROW2__KEY_ROW2 0x1b0b1
|
||||
MX6QDL_PAD_KEY_ROW3__KEY_ROW3 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_lcd1_pwr: lcd1-pwrgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x1b0b1 /* LCD Power Enable */
|
||||
>;
|
||||
};
|
||||
pinctrl_lcd0_pwr: lcd0-pwrgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b1 /* LCD Reset */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pwm1: pwm1grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1
|
||||
>;
|
||||
};
|
||||
pinctrl_lcd1_pwr: lcd-pwrgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x1b0b1 /* LCD Power Enable */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pwm2: pwm2grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1
|
||||
>;
|
||||
};
|
||||
pinctrl_pwm1: pwm1grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_tsc2007: tsc2007grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x1b0b0 /* Interrupt */
|
||||
>;
|
||||
};
|
||||
pinctrl_pwm2: pwm2grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart1: uart1grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
|
||||
MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
|
||||
>;
|
||||
};
|
||||
pinctrl_tsc2007: tsc2007grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x1b0b0 /* Interrupt */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart1_rtscts: uart1_rtsctsgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD3_DAT1__UART1_RTS_B 0x1b0b1
|
||||
MX6QDL_PAD_SD3_DAT0__UART1_CTS_B 0x1b0b1
|
||||
>;
|
||||
};
|
||||
pinctrl_uart1: uart1grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
|
||||
MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart2: uart2grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
|
||||
MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
|
||||
>;
|
||||
};
|
||||
pinctrl_uart1_rtscts: uart1_rtsctsgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD3_DAT1__UART1_RTS_B 0x1b0b1
|
||||
MX6QDL_PAD_SD3_DAT0__UART1_CTS_B 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart2_rtscts: uart2_rtsctsgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1
|
||||
MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1
|
||||
>;
|
||||
};
|
||||
pinctrl_uart2: uart2grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
|
||||
MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart3: uart3grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
|
||||
MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
|
||||
>;
|
||||
};
|
||||
pinctrl_uart2_rtscts: uart2_rtsctsgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1
|
||||
MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart3_rtscts: uart3_rtsctsgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD3_DAT3__UART3_CTS_B 0x1b0b1
|
||||
MX6QDL_PAD_SD3_RST__UART3_RTS_B 0x1b0b1
|
||||
>;
|
||||
};
|
||||
pinctrl_uart3: uart3grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
|
||||
MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usbh1_vbus: usbh1-vbusgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x1b0b0 /* USBH1_VBUSEN */
|
||||
>;
|
||||
};
|
||||
pinctrl_uart3_rtscts: uart3_rtsctsgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD3_DAT3__UART3_CTS_B 0x1b0b1
|
||||
MX6QDL_PAD_SD3_RST__UART3_RTS_B 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usbotg: usbotggrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x17059
|
||||
>;
|
||||
};
|
||||
pinctrl_usbh1_vbus: usbh1-vbusgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x1b0b0 /* USBH1_VBUSEN */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usbotg_vbus: usbotg-vbusgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 /* USBOTG_VBUSEN */
|
||||
>;
|
||||
};
|
||||
pinctrl_usbotg: usbotggrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x17059
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1: usdhc1grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD1_CMD__SD1_CMD 0x070b1
|
||||
MX6QDL_PAD_SD1_CLK__SD1_CLK 0x070b1
|
||||
MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x070b1
|
||||
MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x070b1
|
||||
MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x070b1
|
||||
MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x070b1
|
||||
MX6QDL_PAD_SD3_CMD__GPIO7_IO02 0x170b0 /* SD1 CD */
|
||||
>;
|
||||
};
|
||||
pinctrl_usbotg_vbus: usbotg-vbusgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 /* USBOTG_VBUSEN */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2: usdhc2grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD2_CMD__SD2_CMD 0x070b1
|
||||
MX6QDL_PAD_SD2_CLK__SD2_CLK 0x070b1
|
||||
MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x070b1
|
||||
MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x070b1
|
||||
MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x070b1
|
||||
MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x070b1
|
||||
MX6QDL_PAD_SD3_CLK__GPIO7_IO03 0x170b0 /* SD2 CD */
|
||||
>;
|
||||
};
|
||||
pinctrl_usdhc1: usdhc1grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD1_CMD__SD1_CMD 0x070b1
|
||||
MX6QDL_PAD_SD1_CLK__SD1_CLK 0x070b1
|
||||
MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x070b1
|
||||
MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x070b1
|
||||
MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x070b1
|
||||
MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x070b1
|
||||
MX6QDL_PAD_SD3_CMD__GPIO7_IO02 0x170b0 /* SD1 CD */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2: usdhc2grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD2_CMD__SD2_CMD 0x070b1
|
||||
MX6QDL_PAD_SD2_CLK__SD2_CLK 0x070b1
|
||||
MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x070b1
|
||||
MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x070b1
|
||||
MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x070b1
|
||||
MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x070b1
|
||||
MX6QDL_PAD_SD3_CLK__GPIO7_IO03 0x170b0 /* SD2 CD */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_user_led: user-ledgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b0b1 /* LED */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -644,19 +688,22 @@
|
||||
|
||||
&uart1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1>;
|
||||
pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_rtscts>;
|
||||
fsl,uart-has-rtscts;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart2 &pinctrl_uart2_rtscts>;
|
||||
fsl,uart-has-rtscts;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart3 &pinctrl_uart3_rtscts>;
|
||||
fsl,uart-has-rtscts;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
||||
@ -85,7 +85,7 @@
|
||||
codec: sgtl5000@0a {
|
||||
compatible = "fsl,sgtl5000";
|
||||
reg = <0x0a>;
|
||||
clocks = <&clks 201>;
|
||||
clocks = <&clks IMX6QDL_CLK_CKO>;
|
||||
VDDA-supply = <®_2p5v>;
|
||||
VDDIO-supply = <®_3p3v>;
|
||||
};
|
||||
|
||||
@ -261,7 +261,7 @@
|
||||
clocks = <&clks IMX6QDL_CLK_ECSPI1>,
|
||||
<&clks IMX6QDL_CLK_ECSPI1>;
|
||||
clock-names = "ipg", "per";
|
||||
dmas = <&sdma 3 7 1>, <&sdma 4 7 2>;
|
||||
dmas = <&sdma 3 8 1>, <&sdma 4 8 2>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
@ -275,7 +275,7 @@
|
||||
clocks = <&clks IMX6QDL_CLK_ECSPI2>,
|
||||
<&clks IMX6QDL_CLK_ECSPI2>;
|
||||
clock-names = "ipg", "per";
|
||||
dmas = <&sdma 5 7 1>, <&sdma 6 7 2>;
|
||||
dmas = <&sdma 5 8 1>, <&sdma 6 8 2>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
@ -289,7 +289,7 @@
|
||||
clocks = <&clks IMX6QDL_CLK_ECSPI3>,
|
||||
<&clks IMX6QDL_CLK_ECSPI3>;
|
||||
clock-names = "ipg", "per";
|
||||
dmas = <&sdma 7 7 1>, <&sdma 8 7 2>;
|
||||
dmas = <&sdma 7 8 1>, <&sdma 8 8 2>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
@ -303,7 +303,7 @@
|
||||
clocks = <&clks IMX6QDL_CLK_ECSPI4>,
|
||||
<&clks IMX6QDL_CLK_ECSPI4>;
|
||||
clock-names = "ipg", "per";
|
||||
dmas = <&sdma 9 7 1>, <&sdma 10 7 2>;
|
||||
dmas = <&sdma 9 8 1>, <&sdma 10 8 2>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
@ -621,7 +621,7 @@
|
||||
<0 54 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 127 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
regulator-1p1@110 {
|
||||
regulator-1p1 {
|
||||
compatible = "fsl,anatop-regulator";
|
||||
regulator-name = "vdd1p1";
|
||||
regulator-min-microvolt = <800000>;
|
||||
@ -635,7 +635,7 @@
|
||||
anatop-max-voltage = <1375000>;
|
||||
};
|
||||
|
||||
regulator-3p0@120 {
|
||||
regulator-3p0 {
|
||||
compatible = "fsl,anatop-regulator";
|
||||
regulator-name = "vdd3p0";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
@ -649,7 +649,7 @@
|
||||
anatop-max-voltage = <3400000>;
|
||||
};
|
||||
|
||||
regulator-2p5@130 {
|
||||
regulator-2p5 {
|
||||
compatible = "fsl,anatop-regulator";
|
||||
regulator-name = "vdd2p5";
|
||||
regulator-min-microvolt = <2000000>;
|
||||
@ -663,7 +663,7 @@
|
||||
anatop-max-voltage = <2750000>;
|
||||
};
|
||||
|
||||
reg_arm: regulator-vddcore@140 {
|
||||
reg_arm: regulator-vddcore {
|
||||
compatible = "fsl,anatop-regulator";
|
||||
regulator-name = "vddarm";
|
||||
regulator-min-microvolt = <725000>;
|
||||
@ -680,7 +680,7 @@
|
||||
anatop-max-voltage = <1450000>;
|
||||
};
|
||||
|
||||
reg_pu: regulator-vddpu@140 {
|
||||
reg_pu: regulator-vddpu {
|
||||
compatible = "fsl,anatop-regulator";
|
||||
regulator-name = "vddpu";
|
||||
regulator-min-microvolt = <725000>;
|
||||
@ -697,7 +697,7 @@
|
||||
anatop-max-voltage = <1450000>;
|
||||
};
|
||||
|
||||
reg_soc: regulator-vddsoc@140 {
|
||||
reg_soc: regulator-vddsoc {
|
||||
compatible = "fsl,anatop-regulator";
|
||||
regulator-name = "vddsoc";
|
||||
regulator-min-microvolt = <725000>;
|
||||
@ -896,7 +896,6 @@
|
||||
#size-cells = <1>;
|
||||
reg = <0x2100000 0x10000>;
|
||||
ranges = <0 0x2100000 0x10000>;
|
||||
interrupt-parent = <&intc>;
|
||||
clocks = <&clks IMX6QDL_CLK_CAAM_MEM>,
|
||||
<&clks IMX6QDL_CLK_CAAM_ACLK>,
|
||||
<&clks IMX6QDL_CLK_CAAM_IPG>,
|
||||
@ -1231,22 +1230,22 @@
|
||||
#size-cells = <0>;
|
||||
reg = <2>;
|
||||
|
||||
ipu1_di0_disp0: endpoint@0 {
|
||||
ipu1_di0_disp0: disp0-endpoint {
|
||||
};
|
||||
|
||||
ipu1_di0_hdmi: endpoint@1 {
|
||||
ipu1_di0_hdmi: hdmi-endpoint {
|
||||
remote-endpoint = <&hdmi_mux_0>;
|
||||
};
|
||||
|
||||
ipu1_di0_mipi: endpoint@2 {
|
||||
ipu1_di0_mipi: mipi-endpoint {
|
||||
remote-endpoint = <&mipi_mux_0>;
|
||||
};
|
||||
|
||||
ipu1_di0_lvds0: endpoint@3 {
|
||||
ipu1_di0_lvds0: lvds0-endpoint {
|
||||
remote-endpoint = <&lvds0_mux_0>;
|
||||
};
|
||||
|
||||
ipu1_di0_lvds1: endpoint@4 {
|
||||
ipu1_di0_lvds1: lvds1-endpoint {
|
||||
remote-endpoint = <&lvds1_mux_0>;
|
||||
};
|
||||
};
|
||||
@ -1256,22 +1255,22 @@
|
||||
#size-cells = <0>;
|
||||
reg = <3>;
|
||||
|
||||
ipu1_di0_disp1: endpoint@0 {
|
||||
ipu1_di0_disp1: disp1-endpoint {
|
||||
};
|
||||
|
||||
ipu1_di1_hdmi: endpoint@1 {
|
||||
ipu1_di1_hdmi: hdmi-endpoint {
|
||||
remote-endpoint = <&hdmi_mux_1>;
|
||||
};
|
||||
|
||||
ipu1_di1_mipi: endpoint@2 {
|
||||
ipu1_di1_mipi: mipi-endpoint {
|
||||
remote-endpoint = <&mipi_mux_1>;
|
||||
};
|
||||
|
||||
ipu1_di1_lvds0: endpoint@3 {
|
||||
ipu1_di1_lvds0: lvds0-endpoint {
|
||||
remote-endpoint = <&lvds0_mux_1>;
|
||||
};
|
||||
|
||||
ipu1_di1_lvds1: endpoint@4 {
|
||||
ipu1_di1_lvds1: lvds1-endpoint {
|
||||
remote-endpoint = <&lvds1_mux_1>;
|
||||
};
|
||||
};
|
||||
|
||||
59
sys/gnu/dts/arm/imx6qp-nitrogen6_max.dts
Normal file
59
sys/gnu/dts/arm/imx6qp-nitrogen6_max.dts
Normal file
@ -0,0 +1,59 @@
|
||||
/*
|
||||
* Copyright 2016 Boundary Devices, Inc.
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "imx6qp.dtsi"
|
||||
#include "imx6qdl-nitrogen6_max.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Boundary Devices i.MX6 Quad Plus Nitrogen6_MAX Board";
|
||||
compatible = "boundary,imx6qp-nitrogen6_max", "fsl,imx6qp";
|
||||
};
|
||||
|
||||
&pcie {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&sata {
|
||||
status = "okay";
|
||||
};
|
||||
93
sys/gnu/dts/arm/imx6qp-sabreauto.dts
Normal file
93
sys/gnu/dts/arm/imx6qp-sabreauto.dts
Normal file
@ -0,0 +1,93 @@
|
||||
/*
|
||||
* Copyright 2016 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "imx6qp.dtsi"
|
||||
#include "imx6qdl-sabreauto.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Freescale i.MX6 Quad Plus SABRE Automotive Board";
|
||||
compatible = "fsl,imx6qp-sabreauto", "fsl,imx6qp";
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
max7322: gpio@68 {
|
||||
compatible = "maxim,max7322";
|
||||
reg = <0x68>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
imx6qdl-sabreauto {
|
||||
pinctrl_enet: enetgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0
|
||||
MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b018
|
||||
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b018
|
||||
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b018
|
||||
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b018
|
||||
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b018
|
||||
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b018
|
||||
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b018
|
||||
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b018
|
||||
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b018
|
||||
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b018
|
||||
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b018
|
||||
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b018
|
||||
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
|
||||
MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pcie {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&vgen3_reg {
|
||||
regulator-always-on;
|
||||
};
|
||||
93
sys/gnu/dts/arm/imx6qp-sabresd.dts
Normal file
93
sys/gnu/dts/arm/imx6qp-sabresd.dts
Normal file
@ -0,0 +1,93 @@
|
||||
/*
|
||||
* Copyright 2016 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "imx6qp.dtsi"
|
||||
#include "imx6qdl-sabresd.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Freescale i.MX6 Quad Plus SABRE Smart Device Board";
|
||||
compatible = "fsl,imx6qp-sabresd", "fsl,imx6qp";
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
arm-supply = <&sw2_reg>;
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
imx6qdl-sabresd {
|
||||
pinctrl_usdhc2: usdhc2grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
|
||||
MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10071
|
||||
MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
|
||||
MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
|
||||
MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
|
||||
MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
|
||||
MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059
|
||||
MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059
|
||||
MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059
|
||||
MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3: usdhc3grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
|
||||
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10071
|
||||
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
|
||||
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
|
||||
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
|
||||
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
|
||||
MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
|
||||
MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
|
||||
MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
|
||||
MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pcie {
|
||||
status = "disabled";
|
||||
};
|
||||
89
sys/gnu/dts/arm/imx6qp.dtsi
Normal file
89
sys/gnu/dts/arm/imx6qp.dtsi
Normal file
@ -0,0 +1,89 @@
|
||||
/*
|
||||
* Copyright 2016 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#include "imx6q.dtsi"
|
||||
|
||||
/ {
|
||||
soc {
|
||||
ocram2: sram@00940000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0x00940000 0x20000>;
|
||||
clocks = <&clks IMX6QDL_CLK_OCRAM>;
|
||||
};
|
||||
|
||||
ocram3: sram@00960000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0x00960000 0x20000>;
|
||||
clocks = <&clks IMX6QDL_CLK_OCRAM>;
|
||||
};
|
||||
|
||||
ipu1: ipu@02400000 {
|
||||
compatible = "fsl,imx6qp-ipu", "fsl,imx6q-ipu";
|
||||
clocks = <&clks IMX6QDL_CLK_IPU1>,
|
||||
<&clks IMX6QDL_CLK_IPU1_DI0>, <&clks IMX6QDL_CLK_IPU1_DI1>,
|
||||
<&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
|
||||
<&clks IMX6QDL_CLK_LDB_DI0_PODF>, <&clks IMX6QDL_CLK_LDB_DI1_PODF>,
|
||||
<&clks IMX6QDL_CLK_PRG0_APB>;
|
||||
clock-names = "bus",
|
||||
"di0", "di1",
|
||||
"di0_sel", "di1_sel",
|
||||
"ldb_di0", "ldb_di1", "prg";
|
||||
};
|
||||
|
||||
ipu2: ipu@02800000 {
|
||||
compatible = "fsl,imx6qp-ipu", "fsl,imx6q-ipu";
|
||||
clocks = <&clks IMX6QDL_CLK_IPU2>,
|
||||
<&clks IMX6QDL_CLK_IPU2_DI0>, <&clks IMX6QDL_CLK_IPU2_DI1>,
|
||||
<&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>,
|
||||
<&clks IMX6QDL_CLK_LDB_DI0_PODF>, <&clks IMX6QDL_CLK_LDB_DI1_PODF>,
|
||||
<&clks IMX6QDL_CLK_PRG1_APB>;
|
||||
clock-names = "bus",
|
||||
"di0", "di1",
|
||||
"di0_sel", "di1_sel",
|
||||
"ldb_di0", "ldb_di1", "prg";
|
||||
};
|
||||
|
||||
pcie: pcie@0x01000000 {
|
||||
compatible = "fsl,imx6qp-pcie", "snps,dw-pcie";
|
||||
};
|
||||
};
|
||||
};
|
||||
709
sys/gnu/dts/arm/imx6sx-nitrogen6sx.dts
Normal file
709
sys/gnu/dts/arm/imx6sx-nitrogen6sx.dts
Normal file
@ -0,0 +1,709 @@
|
||||
/*
|
||||
* Copyright (C) 2016 Boundary Devices, Inc.
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "imx6sx.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Boundary Devices i.MX6 SoloX Nitrogen6sx Board";
|
||||
compatible = "boundary,imx6sx-nitrogen6sx", "fsl,imx6sx";
|
||||
|
||||
aliases {
|
||||
fb_lcd = &lcdif1;
|
||||
t_lcd = &t_lcd;
|
||||
};
|
||||
|
||||
memory {
|
||||
reg = <0x80000000 0x40000000>;
|
||||
};
|
||||
|
||||
backlight-lvds {
|
||||
compatible = "pwm-backlight";
|
||||
pwms = <&pwm4 0 5000000>;
|
||||
brightness-levels = <0 4 8 16 32 64 128 255>;
|
||||
default-brightness-level = <6>;
|
||||
power-supply = <®_3p3v>;
|
||||
};
|
||||
|
||||
reg_1p8v: regulator-1p8v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "1P8V";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_3p3v: regulator-3p3v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "3P3V";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_can1_3v3: regulator-can1-3v3 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "can1-3v3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
gpio = <&gpio4 27 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
reg_can2_3v3: regulator-can2-3v3 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "can2-3v3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
gpio = <&gpio4 24 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usbotg1_vbus>;
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "usb_otg1_vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
reg_wlan: regulator-wlan {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_reg_wlan>;
|
||||
compatible = "regulator-fixed";
|
||||
clocks = <&clks IMX6SX_CLK_CKO>;
|
||||
clock-names = "slow";
|
||||
regulator-name = "wlan-en";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
startup-delay-us = <70000>;
|
||||
gpio = <&gpio7 6 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
sound {
|
||||
compatible = "fsl,imx-audio-sgtl5000";
|
||||
model = "imx6sx-nitrogen6sx-sgtl5000";
|
||||
cpu-dai = <&ssi1>;
|
||||
audio-codec = <&codec>;
|
||||
audio-routing =
|
||||
"MIC_IN", "Mic Jack",
|
||||
"Mic Jack", "Mic Bias",
|
||||
"Headphone Jack", "HP_OUT";
|
||||
mux-int-port = <1>;
|
||||
mux-ext-port = <5>;
|
||||
};
|
||||
};
|
||||
|
||||
&audmux {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_audmux>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ecspi1 {
|
||||
fsl,spi-num-chipselects = <1>;
|
||||
cs-gpios = <&gpio2 16 GPIO_ACTIVE_LOW>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ecspi1>;
|
||||
status = "okay";
|
||||
|
||||
flash: m25p80@0 {
|
||||
compatible = "microchip,sst25vf016b";
|
||||
spi-max-frequency = <20000000>;
|
||||
reg = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "U-Boot";
|
||||
reg = <0x0 0xc0000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@c0000 {
|
||||
label = "env";
|
||||
reg = <0xc0000 0x2000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@c2000 {
|
||||
label = "Kernel";
|
||||
reg = <0xc2000 0x11e000>;
|
||||
};
|
||||
|
||||
partition@1e0000 {
|
||||
label = "M4";
|
||||
reg = <0x1e0000 0x20000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&fec1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_enet1>;
|
||||
phy-mode = "rgmii";
|
||||
phy-handle = <ðphy1>;
|
||||
phy-supply = <®_3p3v>;
|
||||
fsl,magic-packet;
|
||||
status = "okay";
|
||||
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ethphy1: ethernet-phy@4 {
|
||||
reg = <4>;
|
||||
};
|
||||
|
||||
ethphy2: ethernet-phy@5 {
|
||||
reg = <5>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&fec2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_enet2>;
|
||||
phy-mode = "rgmii";
|
||||
phy-handle = <ðphy2>;
|
||||
phy-supply = <®_3p3v>;
|
||||
fsl,magic-packet;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&flexcan1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_flexcan1>;
|
||||
xceiver-supply = <®_can1_3v3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&flexcan2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_flexcan2>;
|
||||
xceiver-supply = <®_can2_3v3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
clock-frequency = <100000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c1>;
|
||||
status = "okay";
|
||||
|
||||
codec: sgtl5000@0a {
|
||||
compatible = "fsl,sgtl5000";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_sgtl5000>;
|
||||
reg = <0x0a>;
|
||||
clocks = <&clks IMX6SX_CLK_CKO2>;
|
||||
VDDA-supply = <®_1p8v>;
|
||||
VDDIO-supply = <®_1p8v>;
|
||||
VDDD-supply = <®_1p8v>;
|
||||
assigned-clocks = <&clks IMX6SX_CLK_CKO2_SEL>,
|
||||
<&clks IMX6SX_CLK_CKO2>;
|
||||
assigned-clock-parents = <&clks IMX6SX_CLK_OSC>;
|
||||
assigned-clock-rates = <0>, <24000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
clock-frequency = <100000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
clock-frequency = <100000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&lcdif1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_lcdif1>;
|
||||
lcd-supply = <®_3p3v>;
|
||||
display = <&display0>;
|
||||
status = "okay";
|
||||
|
||||
display0: display0 {
|
||||
bits-per-pixel = <16>;
|
||||
bus-width = <24>;
|
||||
|
||||
display-timings {
|
||||
native-mode = <&t_lcd>;
|
||||
t_lcd: t_lcd_default {
|
||||
clock-frequency = <74160000>;
|
||||
hactive = <1280>;
|
||||
vactive = <720>;
|
||||
hback-porch = <220>;
|
||||
hfront-porch = <110>;
|
||||
vback-porch = <20>;
|
||||
vfront-porch = <5>;
|
||||
hsync-len = <40>;
|
||||
vsync-len = <5>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pcie {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pcie>;
|
||||
reset-gpio = <&gpio4 10 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm4 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pwm4>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ssi1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart3>;
|
||||
fsl,uart-has-rtscts;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart5 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart5>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbotg1 {
|
||||
vbus-supply = <®_usb_otg1_vbus>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usbotg1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbotg2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usbotg2>;
|
||||
dr_mode = "host";
|
||||
disable-over-current;
|
||||
reset-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usdhc2>;
|
||||
bus-width = <4>;
|
||||
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
|
||||
keep-power-in-suspend;
|
||||
wakeup-source;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc3 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usdhc3>;
|
||||
bus-width = <4>;
|
||||
non-removable;
|
||||
keep-power-in-suspend;
|
||||
vmmc-supply = <®_wlan>;
|
||||
cap-power-off-card;
|
||||
cap-sdio-irq;
|
||||
status = "okay";
|
||||
|
||||
brcmf: bcrmf@1 {
|
||||
reg = <1>;
|
||||
compatible = "brcm,bcm4329-fmac";
|
||||
interrupt-parent = <&gpio7>;
|
||||
interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
|
||||
wlcore: wlcore@2 {
|
||||
compatible = "ti,wl1271";
|
||||
reg = <2>;
|
||||
interrupt-parent = <&gpio7>;
|
||||
interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
|
||||
ref-clock-frequency = <38400000>;
|
||||
};
|
||||
};
|
||||
|
||||
&usdhc4 {
|
||||
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
||||
pinctrl-0 = <&pinctrl_usdhc4_50mhz>;
|
||||
pinctrl-1 = <&pinctrl_usdhc4_100mhz>;
|
||||
pinctrl-2 = <&pinctrl_usdhc4_200mhz>;
|
||||
bus-width = <8>;
|
||||
non-removable;
|
||||
vmmc-supply = <®_1p8v>;
|
||||
keep-power-in-suspend;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_hog>;
|
||||
|
||||
pinctrl_audmux: audmuxgrp {
|
||||
fsl,pins = <
|
||||
MX6SX_PAD_SD1_DATA0__AUDMUX_AUD5_RXD 0x1b0b0
|
||||
MX6SX_PAD_SD1_DATA1__AUDMUX_AUD5_TXC 0x1b0b0
|
||||
MX6SX_PAD_SD1_DATA2__AUDMUX_AUD5_TXFS 0x1b0b0
|
||||
MX6SX_PAD_SD1_DATA3__AUDMUX_AUD5_TXD 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_ecspi1: ecspi1grp {
|
||||
fsl,pins = <
|
||||
MX6SX_PAD_KEY_COL1__ECSPI1_MISO 0x100b1
|
||||
MX6SX_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1
|
||||
MX6SX_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1
|
||||
MX6SX_PAD_KEY_ROW1__GPIO2_IO_16 0x0b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_enet1: enet1grp {
|
||||
fsl,pins = <
|
||||
MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0x1b0b0
|
||||
MX6SX_PAD_ENET1_MDC__ENET1_MDC 0x1b0b0
|
||||
MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0x30b1
|
||||
MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0x30b1
|
||||
MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0x30b1
|
||||
MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0x30b1
|
||||
MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0x30b1
|
||||
MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0x30b1
|
||||
MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x3081
|
||||
MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x3081
|
||||
MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x3081
|
||||
MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x3081
|
||||
MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x3081
|
||||
MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x3081
|
||||
MX6SX_PAD_ENET2_CRS__GPIO2_IO_7 0xb0b0
|
||||
MX6SX_PAD_ENET1_RX_CLK__GPIO2_IO_4 0xb0b0
|
||||
MX6SX_PAD_ENET1_TX_CLK__GPIO2_IO_5 0xb0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_enet2: enet2grp {
|
||||
fsl,pins = <
|
||||
MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0x30b1
|
||||
MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0x30b1
|
||||
MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 0x30b1
|
||||
MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 0x30b1
|
||||
MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0x30b1
|
||||
MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0x30b1
|
||||
MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x3081
|
||||
MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x3081
|
||||
MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x3081
|
||||
MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x3081
|
||||
MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0x3081
|
||||
MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0x3081
|
||||
MX6SX_PAD_ENET2_COL__GPIO2_IO_6 0xb0b0
|
||||
MX6SX_PAD_ENET2_RX_CLK__GPIO2_IO_8 0xb0b0
|
||||
MX6SX_PAD_ENET2_TX_CLK__GPIO2_IO_9 0xb0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_flexcan1: flexcan1grp {
|
||||
fsl,pins = <
|
||||
MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x1b0b0
|
||||
MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX 0x1b0b0
|
||||
MX6SX_PAD_QSPI1B_DATA3__GPIO4_IO_27 0x1b0b0
|
||||
MX6SX_PAD_QSPI1B_DATA3__GPIO4_IO_27 0x0b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_flexcan2: flexcan2grp {
|
||||
fsl,pins = <
|
||||
MX6SX_PAD_QSPI1A_DQS__CAN2_TX 0x1b0b0
|
||||
MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x1b0b0
|
||||
MX6SX_PAD_QSPI1B_DATA0__GPIO4_IO_24 0x0b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_hog: hoggrp {
|
||||
fsl,pins = <
|
||||
MX6SX_PAD_NAND_CE0_B__GPIO4_IO_1 0x1b0b0
|
||||
MX6SX_PAD_NAND_CLE__GPIO4_IO_3 0x1b0b0
|
||||
MX6SX_PAD_NAND_RE_B__GPIO4_IO_12 0x1b0b0
|
||||
MX6SX_PAD_NAND_WE_B__GPIO4_IO_14 0x1b0b0
|
||||
MX6SX_PAD_NAND_WP_B__GPIO4_IO_15 0x1b0b0
|
||||
MX6SX_PAD_NAND_READY_B__GPIO4_IO_13 0x1b0b0
|
||||
MX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16 0x1b0b0
|
||||
MX6SX_PAD_QSPI1A_DATA1__GPIO4_IO_17 0x1b0b0
|
||||
MX6SX_PAD_QSPI1A_DATA2__GPIO4_IO_18 0x1b0b0
|
||||
MX6SX_PAD_QSPI1A_DATA3__GPIO4_IO_19 0x1b0b0
|
||||
MX6SX_PAD_SD1_CMD__CCM_CLKO1 0x000b0
|
||||
MX6SX_PAD_SD3_DATA5__GPIO7_IO_7 0x1b0b0
|
||||
/* Test points */
|
||||
MX6SX_PAD_NAND_DATA04__GPIO4_IO_8 0x1b0b0
|
||||
MX6SX_PAD_QSPI1B_DATA1__GPIO4_IO_25 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c1: i2c1grp {
|
||||
fsl,pins = <
|
||||
MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x4001b8b1
|
||||
MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x4001b8b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c2: i2c2grp {
|
||||
fsl,pins = <
|
||||
MX6SX_PAD_GPIO1_IO02__I2C2_SCL 0x4001b8b1
|
||||
MX6SX_PAD_GPIO1_IO03__I2C2_SDA 0x4001b8b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c3: i2c3grp {
|
||||
fsl,pins = <
|
||||
MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1
|
||||
MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x4001b8b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_lcdif1: lcdif1grp {
|
||||
fsl,pins = <
|
||||
MX6SX_PAD_LCD1_CLK__LCDIF1_CLK 0x4001b0b0
|
||||
MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x4001b0b0
|
||||
MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x4001b0b0
|
||||
MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x4001b0b0
|
||||
MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x4001b0b0
|
||||
MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x4001b0b0
|
||||
MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x4001b0b0
|
||||
MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x4001b0b0
|
||||
MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x4001b0b0
|
||||
MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x4001b0b0
|
||||
MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x4001b0b0
|
||||
MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x4001b0b0
|
||||
MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x4001b0b0
|
||||
MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x4001b0b0
|
||||
MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x4001b0b0
|
||||
MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x4001b0b0
|
||||
MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x4001b0b0
|
||||
MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x4001b0b0
|
||||
MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x4001b0b0
|
||||
MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x4001b0b0
|
||||
MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x4001b0b0
|
||||
MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x4001b0b0
|
||||
MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x4001b0b0
|
||||
MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x4001b0b0
|
||||
MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x4001b0b0
|
||||
MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x4001b0b0
|
||||
MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x4001b0b0
|
||||
MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x4001b0b0
|
||||
MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x4001b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pcie: pciegrp {
|
||||
fsl,pins = <
|
||||
MX6SX_PAD_NAND_DATA05__GPIO4_IO_9 0xb0b0
|
||||
MX6SX_PAD_NAND_DATA06__GPIO4_IO_10 0xb0b0
|
||||
MX6SX_PAD_NAND_DATA07__GPIO4_IO_11 0xb0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pwm4: pwm4grp {
|
||||
fsl,pins = <
|
||||
MX6SX_PAD_GPIO1_IO13__PWM4_OUT 0x110b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_reg_wlan: reg-wlangrp {
|
||||
fsl,pins = <
|
||||
MX6SX_PAD_SD3_DATA4__GPIO7_IO_6 0x1b0b0
|
||||
MX6SX_PAD_GPIO1_IO11__CCM_CLKO1 0x000b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_sgtl5000: sgtl5000grp {
|
||||
fsl,pins = <
|
||||
MX6SX_PAD_GPIO1_IO12__CCM_CLKO2 0x000b0
|
||||
MX6SX_PAD_ENET1_COL__GPIO2_IO_0 0x1b0b0
|
||||
MX6SX_PAD_ENET1_CRS__GPIO2_IO_1 0x1b0b0
|
||||
MX6SX_PAD_QSPI1A_SS0_B__GPIO4_IO_22 0xb0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart1: uart1grp {
|
||||
fsl,pins = <
|
||||
MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1
|
||||
MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart2: uart2grp {
|
||||
fsl,pins = <
|
||||
MX6SX_PAD_GPIO1_IO06__UART2_TX 0x1b0b1
|
||||
MX6SX_PAD_GPIO1_IO07__UART2_RX 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart3: uart3grp {
|
||||
fsl,pins = <
|
||||
MX6SX_PAD_QSPI1B_SS0_B__UART3_TX 0x1b0b1
|
||||
MX6SX_PAD_QSPI1B_SCLK__UART3_RX 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart5: uart5grp {
|
||||
fsl,pins = <
|
||||
MX6SX_PAD_KEY_COL3__UART5_TX 0x1b0b1
|
||||
MX6SX_PAD_KEY_ROW3__UART5_RX 0x1b0b1
|
||||
MX6SX_PAD_SD3_DATA6__UART3_RTS_B 0x1b0b1
|
||||
MX6SX_PAD_SD3_DATA7__UART3_CTS_B 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usbotg1: usbotg1grp {
|
||||
fsl,pins = <
|
||||
MX6SX_PAD_GPIO1_IO08__USB_OTG1_OC 0x1b0b0
|
||||
MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x170b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usbotg1_vbus: usbotg1-vbusgrp {
|
||||
fsl,pins = <
|
||||
MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usbotg2: usbotg2grp {
|
||||
fsl,pins = <
|
||||
MX6SX_PAD_QSPI1B_DATA2__GPIO4_IO_26 0xb0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2: usdhc2grp {
|
||||
fsl,pins = <
|
||||
MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x17059
|
||||
MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x10059
|
||||
MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x17059
|
||||
MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x17059
|
||||
MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x17059
|
||||
MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x17059
|
||||
MX6SX_PAD_KEY_COL2__GPIO2_IO_12 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3: usdhc3grp {
|
||||
fsl,pins = <
|
||||
MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x10071
|
||||
MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17071
|
||||
MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17071
|
||||
MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17071
|
||||
MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17071
|
||||
MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17071
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc4_50mhz: usdhc4-50mhzgrp {
|
||||
fsl,pins = <
|
||||
MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10071
|
||||
MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17071
|
||||
MX6SX_PAD_SD4_RESET_B__USDHC4_RESET_B 0x17071
|
||||
MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17071
|
||||
MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17071
|
||||
MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17071
|
||||
MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17071
|
||||
MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x17071
|
||||
MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x17071
|
||||
MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x17071
|
||||
MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x17071
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc4_100mhz: usdhc4-100mhzgrp {
|
||||
fsl,pins = <
|
||||
MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100b9
|
||||
MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170b9
|
||||
MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170b9
|
||||
MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170b9
|
||||
MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170b9
|
||||
MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170b9
|
||||
MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170b9
|
||||
MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170b9
|
||||
MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170b9
|
||||
MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170b9
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc4_200mhz: usdhc4-200mhzgrp {
|
||||
fsl,pins = <
|
||||
MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100f9
|
||||
MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170f9
|
||||
MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170f9
|
||||
MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170f9
|
||||
MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170f9
|
||||
MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170f9
|
||||
MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170f9
|
||||
MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170f9
|
||||
MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170f9
|
||||
MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170f9
|
||||
>;
|
||||
};
|
||||
};
|
||||
67
sys/gnu/dts/arm/imx6sx-sdb-sai.dts
Normal file
67
sys/gnu/dts/arm/imx6sx-sdb-sai.dts
Normal file
@ -0,0 +1,67 @@
|
||||
/*
|
||||
* Copyright (C) 2016 NXP Semiconductors
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#include "imx6sx-sdb.dts"
|
||||
|
||||
/ {
|
||||
sound {
|
||||
audio-cpu = <&sai1>;
|
||||
};
|
||||
};
|
||||
|
||||
&audmux {
|
||||
/* pin conflict with sai */
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&sai1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdma {
|
||||
gpr = <&gpr>;
|
||||
/* SDMA event remap for SAI1 */
|
||||
fsl,sdma-event-remap = <0 15 1>, <0 16 1>;
|
||||
};
|
||||
|
||||
&ssi2 {
|
||||
status = "disabled";
|
||||
};
|
||||
@ -18,12 +18,14 @@
|
||||
996000 1250000
|
||||
792000 1175000
|
||||
396000 1175000
|
||||
198000 1175000
|
||||
>;
|
||||
fsl,soc-operating-points = <
|
||||
/* ARM kHz SOC uV */
|
||||
996000 1250000
|
||||
792000 1175000
|
||||
396000 1175000
|
||||
198000 1175000
|
||||
>;
|
||||
};
|
||||
|
||||
|
||||
@ -63,12 +63,14 @@
|
||||
996000 1250000
|
||||
792000 1175000
|
||||
396000 1075000
|
||||
198000 975000
|
||||
>;
|
||||
fsl,soc-operating-points = <
|
||||
/* ARM kHz SOC uV */
|
||||
996000 1175000
|
||||
792000 1175000
|
||||
396000 1175000
|
||||
198000 1175000
|
||||
>;
|
||||
clock-latency = <61036>; /* two CLK32 periods */
|
||||
clocks = <&clks IMX6SX_CLK_ARM>,
|
||||
@ -970,8 +972,7 @@
|
||||
<&clks 0>, <&clks 0>;
|
||||
clock-names = "bus", "mclk1", "mclk2", "mclk3";
|
||||
dma-names = "rx", "tx";
|
||||
dmas = <&sdma 31 23 0>, <&sdma 32 23 0>;
|
||||
dma-source = <&gpr 0 15 0 16>;
|
||||
dmas = <&sdma 31 24 0>, <&sdma 32 24 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -990,8 +991,7 @@
|
||||
<&clks 0>, <&clks 0>;
|
||||
clock-names = "bus", "mclk1", "mclk2", "mclk3";
|
||||
dma-names = "rx", "tx";
|
||||
dmas = <&sdma 33 23 0>, <&sdma 34 23 0>;
|
||||
dma-source = <&gpr 0 17 0 18>;
|
||||
dmas = <&sdma 33 24 0>, <&sdma 34 24 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
||||
516
sys/gnu/dts/arm/imx6ul-pico-hobbit.dts
Normal file
516
sys/gnu/dts/arm/imx6ul-pico-hobbit.dts
Normal file
@ -0,0 +1,516 @@
|
||||
/*
|
||||
* Copyright 2015 Technexion Ltd.
|
||||
*
|
||||
* Author: Wig Cheng <wig.cheng@technexion.com>
|
||||
* Richard Hu <richard.hu@technexion.com>
|
||||
* Tapani Utriainen <tapani@technexion.com>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "imx6ul.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Technexion Pico i.MX6UL Board";
|
||||
compatible = "technexion,imx6ul-pico-hobbit", "fsl,imx6ul";
|
||||
|
||||
memory {
|
||||
reg = <0x80000000 0x10000000>;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = &uart6;
|
||||
};
|
||||
|
||||
backlight {
|
||||
compatible = "pwm-backlight";
|
||||
pwms = <&pwm3 0 5000000>;
|
||||
brightness-levels = <0 4 8 16 32 64 128 255>;
|
||||
default-brightness-level = <6>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
reg_2p5v: regulator-2p5v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "2P5V";
|
||||
regulator-min-microvolt = <2500000>;
|
||||
regulator-max-microvolt = <2500000>;
|
||||
};
|
||||
|
||||
reg_3p3v: regulator-3p3v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "3P3V";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
reg_sd1_vmmc: regulator-sd1-vmmc {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "VSD_3V3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
reg_usb_otg_vbus: regulator-usb-otg-vbus {
|
||||
compatible = "regulator-fixed";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb_otg1>;
|
||||
regulator-name = "usb_otg_vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
gpio = <&gpio1 6 0>;
|
||||
};
|
||||
|
||||
sound {
|
||||
compatible = "fsl,imx-audio-sgtl5000";
|
||||
model = "imx6ul-sgtl5000";
|
||||
audio-cpu = <&sai1>;
|
||||
audio-codec = <&codec>;
|
||||
audio-routing =
|
||||
"LINE_IN", "Line In Jack",
|
||||
"MIC_IN", "Mic Jack",
|
||||
"Mic Jack", "Mic Bias",
|
||||
"Headphone Jack", "HP_OUT";
|
||||
};
|
||||
|
||||
sys_mclk: clock-sys-mclk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <24576000>;
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
hobbitled {
|
||||
label = "hobbitled";
|
||||
gpios = <&gpio1 29 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&can1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_flexcan1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&can2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_flexcan2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&clks {
|
||||
assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
|
||||
assigned-clock-rates = <786432000>;
|
||||
};
|
||||
|
||||
&fec2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_enet2>;
|
||||
phy-mode = "rmii";
|
||||
phy-handle = <ðphy1>;
|
||||
status = "okay";
|
||||
phy-reset-gpios = <&gpio2 15 GPIO_ACTIVE_LOW>;
|
||||
phy-reset-duration = <11>;
|
||||
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ethphy1: ethernet-phy@1 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <1>;
|
||||
max-speed = <100>;
|
||||
interrupt-parent = <&gpio5>;
|
||||
interrupts = <6 IRQ_TYPE_LEVEL_LOW 0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
clock-frequency = <100000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c1>;
|
||||
status = "okay";
|
||||
|
||||
pmic: pfuze3000@08 {
|
||||
compatible = "fsl,pfuze3000";
|
||||
reg = <0x08>;
|
||||
|
||||
regulators {
|
||||
/* VDD_ARM_SOC_IN*/
|
||||
sw1b_reg: sw1b {
|
||||
regulator-min-microvolt = <700000>;
|
||||
regulator-max-microvolt = <1475000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-ramp-delay = <6250>;
|
||||
};
|
||||
|
||||
/* DRAM */
|
||||
sw3a_reg: sw3 {
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <1650000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
/* DRAM */
|
||||
vref_reg: vrefddr {
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
clock_frequency = <100000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c2>;
|
||||
status = "okay";
|
||||
|
||||
codec: sgtl5000@0a {
|
||||
reg = <0x0a>;
|
||||
compatible = "fsl,sgtl5000";
|
||||
clocks = <&sys_mclk>;
|
||||
VDDA-supply = <®_2p5v>;
|
||||
VDDIO-supply = <®_3p3v>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
clock_frequency = <100000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&lcdif {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_lcdif_dat &pinctrl_lcdif_ctrl>;
|
||||
display = <&display0>;
|
||||
status = "okay";
|
||||
|
||||
display0: display0 {
|
||||
bits-per-pixel = <32>;
|
||||
bus-width = <24>;
|
||||
|
||||
display-timings {
|
||||
native-mode = <&timing0>;
|
||||
|
||||
timing0: timing0 {
|
||||
clock-frequency = <33200000>;
|
||||
hactive = <800>;
|
||||
vactive = <480>;
|
||||
hfront-porch = <210>;
|
||||
hback-porch = <46>;
|
||||
hsync-len = <1>;
|
||||
vback-porch = <22>;
|
||||
vfront-porch = <23>;
|
||||
vsync-len = <1>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pwm3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pwm3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm7 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pwm7>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm8 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pwm8>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sai1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_sai1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart3>;
|
||||
fsl,uart-has-rtscts;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart6 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart6>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbotg1 {
|
||||
vbus-supply = <®_usb_otg_vbus>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb_otg1_id>;
|
||||
dr_mode = "otg";
|
||||
disable-over-current;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbotg2 {
|
||||
dr_mode = "host";
|
||||
disable-over-current;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usdhc1>;
|
||||
bus-width = <8>;
|
||||
no-1-8-v;
|
||||
non-removable;
|
||||
keep-power-in-suspend;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc2 { /* Wifi SDIO */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usdhc2>;
|
||||
no-1-8-v;
|
||||
keep-power-in-suspend;
|
||||
wakeup-source;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl_enet2: enet2grp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_ENET1_TX_DATA1__ENET2_MDIO 0x1b0b0
|
||||
MX6UL_PAD_ENET1_TX_EN__ENET2_MDC 0x1b0b0
|
||||
MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
|
||||
MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
|
||||
MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
|
||||
MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
|
||||
MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
|
||||
MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
|
||||
MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
|
||||
MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031
|
||||
MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x800
|
||||
MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x79
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_flexcan1: flexcan1grp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_ENET1_RX_DATA0__FLEXCAN1_TX 0x1b020
|
||||
MX6UL_PAD_ENET1_RX_DATA1__FLEXCAN1_RX 0x1b020
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_flexcan2: flexcan2grp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX 0x1b020
|
||||
MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX 0x1b020
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c1: i2c1grp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_GPIO1_IO02__I2C1_SCL 0x4001b8b0
|
||||
MX6UL_PAD_GPIO1_IO03__I2C1_SDA 0x4001b8b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c2: i2c2grp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
|
||||
MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c3: i2c3grp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_UART1_TX_DATA__I2C3_SCL 0x4001b8b0
|
||||
MX6UL_PAD_UART1_RX_DATA__I2C3_SDA 0x4001b8b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_lcdif_dat: lcdifdatgrp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79
|
||||
MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79
|
||||
MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79
|
||||
MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79
|
||||
MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79
|
||||
MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79
|
||||
MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79
|
||||
MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79
|
||||
MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79
|
||||
MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79
|
||||
MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79
|
||||
MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79
|
||||
MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79
|
||||
MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79
|
||||
MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79
|
||||
MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79
|
||||
MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79
|
||||
MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79
|
||||
MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79
|
||||
MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79
|
||||
MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79
|
||||
MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79
|
||||
MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79
|
||||
MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_lcdif_ctrl: lcdifctrlgrp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79
|
||||
MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79
|
||||
MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79
|
||||
MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79
|
||||
/* LCD reset */
|
||||
MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pwm3: pwm3grp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_NAND_ALE__PWM3_OUT 0x110b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pwm7: pwm7grp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_ENET1_TX_CLK__PWM7_OUT 0x110b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pwm8: pwm8grp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_ENET1_RX_ER__PWM8_OUT 0x110b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_sai1: sai1grp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_CSI_DATA04__SAI1_TX_SYNC 0x1b0b0
|
||||
MX6UL_PAD_CSI_DATA05__SAI1_TX_BCLK 0x1b0b0
|
||||
MX6UL_PAD_CSI_DATA06__SAI1_RX_DATA 0x110b0
|
||||
MX6UL_PAD_CSI_DATA07__SAI1_TX_DATA 0x1f0b8
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart3: uart3grp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b0
|
||||
MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b0
|
||||
MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x1b0b0
|
||||
MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart5: uart5grp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_GPIO1_IO04__UART5_DCE_TX 0x1b0b1
|
||||
MX6UL_PAD_GPIO1_IO05__UART5_DCE_RX 0x1b0b1
|
||||
MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS 0x1b0b1
|
||||
MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart6: uart6grp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_CSI_MCLK__UART6_DCE_TX 0x1b0b1
|
||||
MX6UL_PAD_CSI_PIXCLK__UART6_DCE_RX 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usb_otg1: usbotg1grp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_GPIO1_IO06__GPIO1_IO06 0x10b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usb_otg1_id: usbotg1idgrp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1: usdhc1grp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
|
||||
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10071
|
||||
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
|
||||
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
|
||||
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
|
||||
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
|
||||
MX6UL_PAD_UART1_RTS_B__USDHC1_CD_B 0x03029
|
||||
MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x17059
|
||||
MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x17059
|
||||
MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x17059
|
||||
MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x17059
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2: usdhc2grp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
|
||||
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10059
|
||||
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
|
||||
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
|
||||
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
|
||||
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
|
||||
>;
|
||||
};
|
||||
};
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user