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gnu/dts: Update our copy of arm dts from Linux 4.16

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This commit is contained in:
Emmanuel Vadot 2018-04-20 19:37:08 +00:00
commit c712135a32
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=332839
456 changed files with 17727 additions and 5403 deletions
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2
sys/gnu/dts/arm/am335x-bone-common.dtsi
View File

@ -409,6 +409,6 @@
};
&rtc {
clocks = <&clk_32768_ck>, <&clkdiv32k_ick>;
clocks = <&clk_32768_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
clock-names = "ext-clk", "int-clk";
};

81
sys/gnu/dts/arm/am335x-boneblue.dts
View File

@ -159,6 +159,7 @@
>;
};
/* UT0 */
uart0_pins: pinmux_uart0_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* (E15) uart0_rxd.uart0_rxd */
@ -166,6 +167,37 @@
>;
};
/* UT1 */
uart1_pins: pinmux_uart1_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE0) /* (D16) uart1_rxd.uart1_rxd */
AM33XX_IOPAD(0x984, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* (D15) uart1_txd.uart1_txd */
>;
};
/* GPS */
uart2_pins: pinmux_uart2_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x950, PIN_INPUT_PULLUP | MUX_MODE1) /* (A17) spi0_sclk.uart2_rxd */
AM33XX_IOPAD(0x954, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* (B17) spi0_d0.uart2_txd */
>;
};
/* DSM2 */
uart4_pins: pinmux_uart4_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE6) /* (T17) gpmc_wait0.uart4_rxd */
>;
};
/* UT5 */
uart5_pins: pinmux_uart5_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x8C4, PIN_INPUT_PULLUP | MUX_MODE4) /* (U2) lcd_data9.uart5_rxd */
AM33XX_IOPAD(0x8C0, PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* (U1) lcd_data8.uart5_txd */
>;
};
mmc1_pins: pinmux_mmc1_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* (C15) spi0_cs1.gpio0[6] */
@ -216,10 +248,19 @@
wl18xx_pins: pinmux_wl18xx_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x92c, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* (K18) gmii1_txclk.gpio3[9] - WL_EN */
AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7) /* (H18) rmii1_refclk.gpio0[29] - WL_IRQ */
AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7) /* (K16) gmii1_txd1.gpio0[21] - WL_IRQ */
AM33XX_IOPAD(0x930, PIN_OUTPUT_PULLUP | MUX_MODE7) /* (L18) gmii1_rxclk.gpio3[10] - LS_BUF_EN */
>;
};
/* DCAN */
dcan1_pins: pinmux_dcan1_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x96c, PIN_INPUT | MUX_MODE2) /* (E17) uart0_rtsn.dcan1_rx */
AM33XX_IOPAD(0x968, PIN_OUTPUT | MUX_MODE2) /* (E18) uart0_ctsn.dcan1_tx */
AM33XX_IOPAD(0x940, PIN_OUTPUT | MUX_MODE7) /* (M16) gmii1_rxd0.gpio2[21] */
>;
};
};
&uart0 {
@ -229,6 +270,34 @@
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&uart2_pins>;
status = "okay";
};
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&uart4_pins>;
status = "okay";
};
&uart5 {
pinctrl-names = "default";
pinctrl-0 = <&uart5_pins>;
status = "okay";
};
&usb {
status = "okay";
};
@ -414,7 +483,7 @@
compatible = "ti,wl1835";
reg = <2>;
interrupt-parent = <&gpio0>;
interrupts = <29 IRQ_TYPE_EDGE_RISING>;
interrupts = <21 IRQ_TYPE_EDGE_RISING>;
};
};
@ -446,10 +515,16 @@
&rtc {
system-power-controller;
clocks = <&clk_32768_ck>, <&clkdiv32k_ick>;
clocks = <&clk_32768_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
clock-names = "ext-clk", "int-clk";
};
&dcan1 {
pinctrl-names = "default";
pinctrl-0 = <&dcan1_pins>;
status = "okay";
};
&gpio3 {
ls_buf_en {
gpio-hog;

2
sys/gnu/dts/arm/am335x-evm.dts
View File

@ -790,6 +790,6 @@
};
&rtc {
clocks = <&clk_32768_ck>, <&clkdiv32k_ick>;
clocks = <&clk_32768_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
clock-names = "ext-clk", "int-clk";
};

2
sys/gnu/dts/arm/am335x-evmsk.dts
View File

@ -722,6 +722,6 @@
};
&rtc {
clocks = <&clk_32768_ck>, <&clkdiv32k_ick>;
clocks = <&clk_32768_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
clock-names = "ext-clk", "int-clk";
};

2
sys/gnu/dts/arm/am335x-pepper.dts
View File

@ -139,7 +139,7 @@
&audio_codec {
status = "okay";
gpio-reset = <&gpio1 16 GPIO_ACTIVE_LOW>;
reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
AVDD-supply = <&ldo3_reg>;
IOVDD-supply = <&ldo3_reg>;
DRVDD-supply = <&ldo3_reg>;

205
sys/gnu/dts/arm/am33xx-clocks.dtsi
View File

@ -292,14 +292,6 @@
clock-div = <4>;
};
cefuse_fck: cefuse_fck@a20 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_clkin_ck>;
ti,bit-shift = <1>;
reg = <0x0a20>;
};
clk_24mhz: clk_24mhz {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
@ -316,14 +308,6 @@
clock-div = <732>;
};
clkdiv32k_ick: clkdiv32k_ick@14c {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&clkdiv32k_ck>;
ti,bit-shift = <1>;
reg = <0x014c>;
};
l3_gclk: l3_gclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
@ -350,49 +334,49 @@
timer1_fck: timer1_fck@528 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin_ck>, <&clkdiv32k_ick>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>;
clocks = <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>;
reg = <0x0528>;
};
timer2_fck: timer2_fck@508 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
reg = <0x0508>;
};
timer3_fck: timer3_fck@50c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
reg = <0x050c>;
};
timer4_fck: timer4_fck@510 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
reg = <0x0510>;
};
timer5_fck: timer5_fck@518 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
reg = <0x0518>;
};
timer6_fck: timer6_fck@51c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
reg = <0x051c>;
};
timer7_fck: timer7_fck@504 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
reg = <0x0504>;
};
@ -423,7 +407,7 @@
wdt1_fck: wdt1_fck@538 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&clk_rc32k_ck>, <&clkdiv32k_ick>;
clocks = <&clk_rc32k_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
reg = <0x0538>;
};
@ -493,42 +477,10 @@
gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck@53c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clkdiv32k_ick>;
clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
reg = <0x053c>;
};
gpio0_dbclk: gpio0_dbclk@408 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&gpio0_dbclk_mux_ck>;
ti,bit-shift = <18>;
reg = <0x0408>;
};
gpio1_dbclk: gpio1_dbclk@ac {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&clkdiv32k_ick>;
ti,bit-shift = <18>;
reg = <0x00ac>;
};
gpio2_dbclk: gpio2_dbclk@b0 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&clkdiv32k_ick>;
ti,bit-shift = <18>;
reg = <0x00b0>;
};
gpio3_dbclk: gpio3_dbclk@b4 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&clkdiv32k_ick>;
ti,bit-shift = <18>;
reg = <0x00b4>;
};
lcd_gclk: lcd_gclk@534 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
@ -577,58 +529,6 @@
reg = <0x0700>;
};
dbg_sysclk_ck: dbg_sysclk_ck@414 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_clkin_ck>;
ti,bit-shift = <19>;
reg = <0x0414>;
};
dbg_clka_ck: dbg_clka_ck@414 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&dpll_core_m4_ck>;
ti,bit-shift = <30>;
reg = <0x0414>;
};
stm_pmd_clock_mux_ck: stm_pmd_clock_mux_ck@414 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&dbg_sysclk_ck>, <&dbg_clka_ck>;
ti,bit-shift = <22>;
reg = <0x0414>;
};
trace_pmd_clk_mux_ck: trace_pmd_clk_mux_ck@414 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&dbg_sysclk_ck>, <&dbg_clka_ck>;
ti,bit-shift = <20>;
reg = <0x0414>;
};
stm_clk_div_ck: stm_clk_div_ck@414 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&stm_pmd_clock_mux_ck>;
ti,bit-shift = <27>;
ti,max-div = <64>;
reg = <0x0414>;
ti,index-power-of-two;
};
trace_clk_div_ck: trace_clk_div_ck@414 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&trace_pmd_clk_mux_ck>;
ti,bit-shift = <24>;
ti,max-div = <64>;
reg = <0x0414>;
ti,index-power-of-two;
};
clkout2_ck: clkout2_ck@700 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@ -638,9 +538,88 @@
};
};
&prcm_clockdomains {
clk_24mhz_clkdm: clk_24mhz_clkdm {
compatible = "ti,clockdomain";
clocks = <&clkdiv32k_ick>;
&prcm {
l4_per_cm: l4_per_cm@0 {
compatible = "ti,omap4-cm";
reg = <0x0 0x200>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x0 0x200>;
l4_per_clkctrl: clk@14 {
compatible = "ti,clkctrl";
reg = <0x14 0x13c>;
#clock-cells = <2>;
};
};
l4_wkup_cm: l4_wkup_cm@400 {
compatible = "ti,omap4-cm";
reg = <0x400 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x400 0x100>;
l4_wkup_clkctrl: clk@4 {
compatible = "ti,clkctrl";
reg = <0x4 0xd4>;
#clock-cells = <2>;
};
};
mpu_cm: mpu_cm@600 {
compatible = "ti,omap4-cm";
reg = <0x600 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x600 0x100>;
mpu_clkctrl: clk@4 {
compatible = "ti,clkctrl";
reg = <0x4 0x4>;
#clock-cells = <2>;
};
};
l4_rtc_cm: l4_rtc_cm@800 {
compatible = "ti,omap4-cm";
reg = <0x800 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x800 0x100>;
l4_rtc_clkctrl: clk@0 {
compatible = "ti,clkctrl";
reg = <0x0 0x4>;
#clock-cells = <2>;
};
};
gfx_l3_cm: gfx_l3_cm@900 {
compatible = "ti,omap4-cm";
reg = <0x900 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x900 0x100>;
gfx_l3_clkctrl: clk@4 {
compatible = "ti,clkctrl";
reg = <0x4 0x4>;
#clock-cells = <2>;
};
};
l4_cefuse_cm: l4_cefuse_cm@a00 {
compatible = "ti,omap4-cm";
reg = <0xa00 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xa00 0x100>;
l4_cefuse_clkctrl: clk@20 {
compatible = "ti,clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
};
};

18
sys/gnu/dts/arm/am33xx.dtsi
View File

@ -10,6 +10,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/am33xx.h>
#include <dt-bindings/clock/am3.h>
/ {
compatible = "ti,am33xx";
@ -179,8 +180,11 @@
};
prcm: prcm@200000 {
compatible = "ti,am3-prcm";
compatible = "ti,am3-prcm", "simple-bus";
reg = <0x200000 0x4000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x200000 0x4000>;
prcm_clocks: clocks {
#address-cells = <1>;
@ -496,7 +500,7 @@
status = "disabled";
};
mailbox: mailbox@480C8000 {
mailbox: mailbox@480c8000 {
compatible = "ti,omap4-mailbox";
reg = <0x480C8000 0x200>;
interrupts = <77>;
@ -517,6 +521,8 @@
interrupts = <67>;
ti,hwmods = "timer1";
ti,timer-alwon;
clocks = <&timer1_fck>;
clock-names = "fck";
};
timer2: timer@48040000 {
@ -524,6 +530,8 @@
reg = <0x48040000 0x400>;
interrupts = <68>;
ti,hwmods = "timer2";
clocks = <&timer2_fck>;
clock-names = "fck";
};
timer3: timer@48042000 {
@ -571,7 +579,7 @@
interrupts = <75
76>;
ti,hwmods = "rtc";
clocks = <&clkdiv32k_ick>;
clocks = <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
clock-names = "int-clk";
};
@ -991,7 +999,7 @@
dma-names = "tx", "rx";
};
mcasp1: mcasp@4803C000 {
mcasp1: mcasp@4803c000 {
compatible = "ti,am33xx-mcasp-audio";
ti,hwmods = "mcasp1";
reg = <0x4803C000 0x2000>,
@ -1014,4 +1022,4 @@
};
};
/include/ "am33xx-clocks.dtsi"
#include "am33xx-clocks.dtsi"

8
sys/gnu/dts/arm/am3517.dtsi
View File

@ -26,7 +26,7 @@
interrupt-names = "mc";
};
davinci_emac: ethernet@0x5c000000 {
davinci_emac: ethernet@5c000000 {
compatible = "ti,am3517-emac";
ti,hwmods = "davinci_emac";
status = "disabled";
@ -41,7 +41,7 @@
local-mac-address = [ 00 00 00 00 00 00 ];
};
davinci_mdio: ethernet@0x5c030000 {
davinci_mdio: ethernet@5c030000 {
compatible = "ti,davinci_mdio";
ti,hwmods = "davinci_mdio";
status = "disabled";
@ -99,9 +99,5 @@
status = "disabled";
};
&smartreflex_mpu_iva {
status = "disabled";
};
/include/ "am35xx-clocks.dtsi"
/include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"

20
sys/gnu/dts/arm/am4372.dtsi
View File

@ -10,6 +10,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/am4.h>
/ {
compatible = "ti,am4372", "ti,am43";
@ -163,9 +164,12 @@
};
prcm: prcm@1f0000 {
compatible = "ti,am4-prcm";
compatible = "ti,am4-prcm", "simple-bus";
reg = <0x1f0000 0x11000>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x1f0000 0x11000>;
prcm_clocks: clocks {
#address-cells = <1>;
@ -325,7 +329,7 @@
status = "disabled";
};
mailbox: mailbox@480C8000 {
mailbox: mailbox@480c8000 {
compatible = "ti,omap4-mailbox";
reg = <0x480C8000 0x200>;
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
@ -346,6 +350,8 @@
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
ti,timer-alwon;
ti,hwmods = "timer1";
clocks = <&timer1_fck>;
clock-names = "fck";
};
timer2: timer@48040000 {
@ -353,6 +359,8 @@
reg = <0x48040000 0x400>;
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer2";
clocks = <&timer2_fck>;
clock-names = "fck";
};
timer3: timer@48042000 {
@ -936,7 +944,7 @@
dma-names = "tx", "rx";
};
mcasp1: mcasp@4803C000 {
mcasp1: mcasp@4803c000 {
compatible = "ti,am33xx-mcasp-audio";
ti,hwmods = "mcasp1";
reg = <0x4803C000 0x2000>,
@ -993,7 +1001,7 @@
reg = <0x483a8000 0x8000>;
syscon-phy-power = <&scm_conf 0x620>;
clocks = <&usb_phy0_always_on_clk32k>,
<&usb_otg_ss0_refclk960m>;
<&l4_per_clkctrl AM4_USB_OTG_SS0_CLKCTRL 8>;
clock-names = "wkupclk", "refclk";
#phy-cells = <0>;
status = "disabled";
@ -1012,7 +1020,7 @@
reg = <0x483e8000 0x8000>;
syscon-phy-power = <&scm_conf 0x628>;
clocks = <&usb_phy1_always_on_clk32k>,
<&usb_otg_ss1_refclk960m>;
<&l4_per_clkctrl AM4_USB_OTG_SS1_CLKCTRL 8>;
clock-names = "wkupclk", "refclk";
#phy-cells = <0>;
status = "disabled";
@ -1175,4 +1183,4 @@
};
};
/include/ "am43xx-clocks.dtsi"
#include "am43xx-clocks.dtsi"

4
sys/gnu/dts/arm/am437x-gp-evm.dts
View File

@ -55,7 +55,7 @@
enable-active-high;
};
backlight {
lcd_bl: backlight {
compatible = "pwm-backlight";
pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
brightness-levels = <0 51 53 56 62 75 101 152 255>;
@ -86,6 +86,8 @@
compatible = "osddisplays,osd057T0559-34ts", "panel-dpi";
label = "lcd";
backlight = <&lcd_bl>;
panel-timing {
clock-frequency = <33000000>;
hactive = <800>;

14
sys/gnu/dts/arm/am437x-idk-evm.dts
View File

@ -519,3 +519,17 @@
&cpu {
cpu0-supply = <&tps>;
};
&cpu0_opp_table {
/*
* Supply voltage supervisor on board will not allow opp50 so
* disable it and set opp100 as suspend OPP.
*/
opp50@300000000 {
status = "disabled";
};
opp100@600000000 {
opp-suspend;
};
};

4
sys/gnu/dts/arm/am437x-sk-evm.dts
View File

@ -35,7 +35,7 @@
clock-frequency = <32768>;
};
backlight {
lcd_bl: backlight {
compatible = "pwm-backlight";
pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
brightness-levels = <0 51 53 56 62 75 101 152 255>;
@ -132,6 +132,8 @@
pinctrl-names = "default";
pinctrl-0 = <&lcd_pins>;
backlight = <&lcd_bl>;
enable-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
panel-timing {

10
sys/gnu/dts/arm/am43x-epos-evm.dts
View File

@ -48,6 +48,8 @@
compatible = "osddisplays,osd057T0559-34ts", "panel-dpi";
label = "lcd";
backlight = <&lcd_bl>;
panel-timing {
clock-frequency = <33000000>;
hactive = <800>;
@ -107,7 +109,7 @@
0x03030069>; /* LEFT */
};
backlight {
lcd_bl: backlight {
compatible = "pwm-backlight";
pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
brightness-levels = <0 51 53 56 62 75 101 152 255>;
@ -985,7 +987,11 @@
rx-num-evt = <32>;
};
&synctimer_32kclk {
&mux_synctimer32k_ck {
assigned-clocks = <&mux_synctimer32k_ck>;
assigned-clock-parents = <&clkdiv32k_ick>;
};
&cpu {
cpu0-supply = <&dcdc2>;
};

212
sys/gnu/dts/arm/am43xx-clocks.dtsi
View File

@ -524,54 +524,6 @@
reg = <0x4240>;
};
gpio0_dbclk: gpio0_dbclk@2b68 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&gpio0_dbclk_mux_ck>;
ti,bit-shift = <8>;
reg = <0x2b68>;
};
gpio1_dbclk: gpio1_dbclk@8c78 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&clkdiv32k_ick>;
ti,bit-shift = <8>;
reg = <0x8c78>;
};
gpio2_dbclk: gpio2_dbclk@8c80 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&clkdiv32k_ick>;
ti,bit-shift = <8>;
reg = <0x8c80>;
};
gpio3_dbclk: gpio3_dbclk@8c88 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&clkdiv32k_ick>;
ti,bit-shift = <8>;
reg = <0x8c88>;
};
gpio4_dbclk: gpio4_dbclk@8c90 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&clkdiv32k_ick>;
ti,bit-shift = <8>;
reg = <0x8c90>;
};
gpio5_dbclk: gpio5_dbclk@8c98 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&clkdiv32k_ick>;
ti,bit-shift = <8>;
reg = <0x8c98>;
};
mmc_clk: mmc_clk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
@ -629,14 +581,6 @@
reg = <0x4230>;
};
synctimer_32kclk: synctimer_32kclk@2a30 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&mux_synctimer32k_ck>;
ti,bit-shift = <8>;
reg = <0x2a30>;
};
timer8_fck: timer8_fck@421c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
@ -763,110 +707,76 @@
ti,bit-shift = <8>;
reg = <0x2a48>;
};
};
usb_otg_ss0_refclk960m: usb_otg_ss0_refclk960m@8a60 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&dpll_per_clkdcoldo>;
ti,bit-shift = <8>;
reg = <0x8a60>;
&prcm {
l4_wkup_cm: l4_wkup_cm@2800 {
compatible = "ti,omap4-cm";
reg = <0x2800 0x400>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x2800 0x400>;
l4_wkup_clkctrl: clk@20 {
compatible = "ti,clkctrl";
reg = <0x20 0x34c>;
#clock-cells = <2>;
};
};
usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m@8a68 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&dpll_per_clkdcoldo>;
ti,bit-shift = <8>;
reg = <0x8a68>;
mpu_cm: mpu_cm@8300 {
compatible = "ti,omap4-cm";
reg = <0x8300 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x8300 0x100>;
mpu_clkctrl: clk@20 {
compatible = "ti,clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
};
clkout1_osc_div_ck: clkout1_osc_div_ck {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&sys_clkin_ck>;
ti,bit-shift = <20>;
ti,max-div = <4>;
reg = <0x4100>;
gfx_l3_cm: gfx_l3_cm@8400 {
compatible = "ti,omap4-cm";
reg = <0x8400 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x8400 0x100>;
gfx_l3_clkctrl: clk@20 {
compatible = "ti,clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
};
clkout1_src2_mux_ck: clkout1_src2_mux_ck {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&clk_rc32k_ck>, <&sysclk_div>, <&dpll_ddr_m2_ck>,
<&dpll_per_m2_ck>, <&dpll_disp_m2_ck>,
<&dpll_mpu_m2_ck>;
reg = <0x4100>;
l4_rtc_cm: l4_rtc_cm@8500 {
compatible = "ti,omap4-cm";
reg = <0x8500 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x8500 0x100>;
l4_rtc_clkctrl: clk@20 {
compatible = "ti,clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
};
clkout1_src2_pre_div_ck: clkout1_src2_pre_div_ck {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&clkout1_src2_mux_ck>;
ti,bit-shift = <4>;
ti,max-div = <8>;
reg = <0x4100>;
};
l4_per_cm: l4_per_cm@8800 {
compatible = "ti,omap4-cm";
reg = <0x8800 0xc00>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x8800 0xc00>;
clkout1_src2_post_div_ck: clkout1_src2_post_div_ck {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&clkout1_src2_pre_div_ck>;
ti,bit-shift = <8>;
ti,max-div = <32>;
ti,index-power-of-two;
reg = <0x4100>;
};
clkout1_mux_ck: clkout1_mux_ck {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&clkout1_osc_div_ck>, <&clk_rc32k_ck>,
<&clkout1_src2_post_div_ck>, <&dpll_extdev_m2_ck>;
ti,bit-shift = <16>;
reg = <0x4100>;
};
clkout1_ck: clkout1_ck {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&clkout1_mux_ck>;
ti,bit-shift = <23>;
reg = <0x4100>;
};
clkout2_src_mux_ck: clkout2_src_mux_ck {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&clk_rc32k_ck>, <&sysclk_div>, <&dpll_ddr_m2_ck>,
<&dpll_per_m2_ck>, <&dpll_disp_m2_ck>,
<&dpll_mpu_m2_ck>, <&dpll_extdev_ck>;
reg = <0x4108>;
};
clkout2_pre_div_ck: clkout2_pre_div_ck {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&clkout2_src_mux_ck>;
ti,bit-shift = <4>;
ti,max-div = <8>;
reg = <0x4108>;
};
clkout2_post_div_ck: clkout2_post_div_ck {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&clkout2_pre_div_ck>;
ti,bit-shift = <8>;
ti,max-div = <32>;
ti,index-power-of-two;
reg = <0x4108>;
};
clkout2_ck: clkout2_ck {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&clkout2_post_div_ck>;
ti,bit-shift = <16>;
reg = <0x4108>;
l4_per_clkctrl: clk@20 {
compatible = "ti,clkctrl";
reg = <0x20 0xb04>;
#clock-cells = <2>;
};
};
};

4
sys/gnu/dts/arm/am571x-idk.dts
View File

@ -117,3 +117,7 @@
pinctrl-1 = <&mmc2_pins_hs>;
pinctrl-2 = <&mmc2_pins_ddr_rev20 &mmc2_iodelay_ddr_conf>;
};
&cpu0 {
vdd-supply = <&smps12_reg>;
};

100
sys/gnu/dts/arm/am572x-idk-common.dtsi Normal file
View File

@ -0,0 +1,100 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include "am57xx-idk-common.dtsi"
/ {
memory@0 {
device_type = "memory";
reg = <0x0 0x80000000 0x0 0x80000000>;
};
status-leds {
compatible = "gpio-leds";
cpu0-led {
label = "status0:red:cpu0";
gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>;
default-state = "off";
linux,default-trigger = "cpu0";
};
usr0-led {
label = "status0:green:usr";
gpios = <&gpio3 11 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
heartbeat-led {
label = "status0:blue:heartbeat";
gpios = <&gpio3 12 GPIO_ACTIVE_HIGH>;
default-state = "off";
linux,default-trigger = "heartbeat";
};
cpu1-led {
label = "status1:red:cpu1";
gpios = <&gpio3 10 GPIO_ACTIVE_HIGH>;
default-state = "off";
linux,default-trigger = "cpu1";
};
usr1-led {
label = "status1:green:usr";
gpios = <&gpio7 23 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
mmc0-led {
label = "status1:blue:mmc0";
gpios = <&gpio7 22 GPIO_ACTIVE_HIGH>;
default-state = "off";
linux,default-trigger = "mmc0";
};
};
};
&omap_dwc3_2 {
extcon = <&extcon_usb2>;
};
&extcon_usb2 {
id-gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>;
vbus-gpio = <&gpio3 26 GPIO_ACTIVE_HIGH>;
};
&sn65hvs882 {
load-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
};
&pcie1_rc {
status = "okay";
gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
};
&pcie1_ep {
gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
};
&mailbox5 {
status = "okay";
mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
status = "okay";
};
mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
status = "okay";
};
};
&mailbox6 {
status = "okay";
mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
status = "okay";
};
mbox_dsp2_ipc3x: mbox_dsp2_ipc3x {
status = "okay";
};
};

93
sys/gnu/dts/arm/am572x-idk.dts
View File

@ -9,8 +9,7 @@
/dts-v1/;
#include "dra74x.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include "am572x-idk-common.dtsi"
#include "am57xx-idk-common.dtsi"
#include "dra74x-mmc-iodelay.dtsi"
@ -18,54 +17,6 @@
model = "TI AM5728 IDK";
compatible = "ti,am5728-idk", "ti,am5728", "ti,dra742", "ti,dra74",
"ti,dra7";
memory@0 {
device_type = "memory";
reg = <0x0 0x80000000 0x0 0x80000000>;
};
status-leds {
compatible = "gpio-leds";
cpu0-led {
label = "status0:red:cpu0";
gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>;
default-state = "off";
linux,default-trigger = "cpu0";
};
usr0-led {
label = "status0:green:usr";
gpios = <&gpio3 11 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
heartbeat-led {
label = "status0:blue:heartbeat";
gpios = <&gpio3 12 GPIO_ACTIVE_HIGH>;
default-state = "off";
linux,default-trigger = "heartbeat";
};
cpu1-led {
label = "status1:red:cpu1";
gpios = <&gpio3 10 GPIO_ACTIVE_HIGH>;
default-state = "off";
linux,default-trigger = "cpu1";
};
usr1-led {
label = "status1:green:usr";
gpios = <&gpio7 23 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
mmc0-led {
label = "status1:blue:mmc0";
gpios = <&gpio7 22 GPIO_ACTIVE_HIGH>;
default-state = "off";
linux,default-trigger = "mmc0";
};
};
};
&mmc1 {
@ -86,44 +37,6 @@
pinctrl-2 = <&mmc2_pins_ddr_rev20>;
};
&omap_dwc3_2 {
extcon = <&extcon_usb2>;
};
&extcon_usb2 {
id-gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>;
vbus-gpio = <&gpio3 26 GPIO_ACTIVE_HIGH>;
};
&sn65hvs882 {
load-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
};
&pcie1_rc {
status = "okay";
gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
};
&pcie1_ep {
gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
};
&mailbox5 {
status = "okay";
mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
status = "okay";
};
mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
status = "okay";
};
};
&mailbox6 {
status = "okay";
mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
status = "okay";
};
mbox_dsp2_ipc3x: mbox_dsp2_ipc3x {
status = "okay";
};
&cpu0 {
vdd-supply = <&smps12_reg>;
};

22
sys/gnu/dts/arm/am574x-idk.dts Normal file
View File

@ -0,0 +1,22 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
*/
/dts-v1/;
#include "dra76x.dtsi"
#include "am572x-idk-common.dtsi"
/ {
model = "TI AM5748 IDK";
compatible = "ti,am5728-idk", "ti,dra762", "ti,dra7";
};
&qspi {
spi-max-frequency = <96000000>;
m25p80@0 {
spi-max-frequency = <96000000>;
};
};

4
sys/gnu/dts/arm/am57xx-beagle-x15-common.dtsi
View File

@ -388,7 +388,7 @@
};
&cpu0 {
cpu0-supply = <&smps12_reg>;
vdd-supply = <&smps12_reg>;
voltage-tolerance = <1>;
};
@ -554,7 +554,7 @@
&mcasp3 {
#sound-dai-cells = <0>;
assigned-clocks = <&mcasp3_ahclkx_mux>;
assigned-clocks = <&l4per_clkctrl DRA7_MCASP3_CLKCTRL 24>;
assigned-clock-parents = <&sys_clkin2>;
status = "okay";

12
sys/gnu/dts/arm/animeo_ip.dts
View File

@ -43,6 +43,18 @@
ahb {
apb {
tcb0: timer@fffa0000 {
timer@0 {
compatible = "atmel,tcb-timer";
reg = <0>, <1>;
};
timer@2 {
compatible = "atmel,tcb-timer";
reg = <2>;
};
};
usart0: serial@fffb0000 {
pinctrl-0 = <&pinctrl_usart0 &pinctrl_usart0_rts>;
linux,rs485-enabled-at-boot-time;

5
sys/gnu/dts/arm/arm-realview-eb-mp.dtsi
View File

@ -150,11 +150,6 @@
interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
};
&charlcd {
interrupt-parent = <&intc>;
interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
};
&serial0 {
interrupt-parent = <&intc>;
interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;

5
sys/gnu/dts/arm/armada-38x.dtsi
View File

@ -279,6 +279,11 @@
marvell,function = "dev";
};
nand_rb: nand-rb {
marvell,pins = "mpp41";
marvell,function = "nand";
};
uart0_pins: uart-pins-0 {
marvell,pins = "mpp0", "mpp1";
marvell,function = "ua0";

4
sys/gnu/dts/arm/aspeed-ast2500-evb.dts
View File

@ -1,4 +1,4 @@
// SPDX-License-Identifier: GPL-2.0
// SPDX-License-Identifier: GPL-2.0+
/dts-v1/;
#include "aspeed-g5.dtsi"
@ -16,7 +16,7 @@
bootargs = "console=ttyS4,115200 earlyprintk";
};
memory {
memory@80000000 {
reg = <0x80000000 0x20000000>;
};
};

5
sys/gnu/dts/arm/aspeed-bmc-opp-palmetto.dts
View File

@ -1,4 +1,4 @@
// SPDX-License-Identifier: GPL-2.0
// SPDX-License-Identifier: GPL-2.0+
/dts-v1/;
#include "aspeed-g4.dtsi"
@ -12,7 +12,7 @@
bootargs = "console=ttyS4,115200 earlyprintk";
};
memory {
memory@40000000 {
reg = <0x40000000 0x20000000>;
};
@ -34,6 +34,7 @@
status = "okay";
m25p,fast-read;
label = "bmc";
#include "openbmc-flash-layout.dtsi"
};
};

135
sys/gnu/dts/arm/aspeed-bmc-opp-romulus.dts
View File

@ -1,23 +1,19 @@
// SPDX-License-Identifier: GPL-2.0
// SPDX-License-Identifier: GPL-2.0+
/dts-v1/;
#include "aspeed-g5.dtsi"
#include <dt-bindings/gpio/aspeed-gpio.h>
/ {
model = "Romulus BMC";
compatible = "ibm,romulus-bmc", "aspeed,ast2500";
aliases {
serial4 = &uart5;
};
chosen {
stdout-path = &uart5;
bootargs = "console=ttyS4,115200 earlyprintk";
};
memory {
reg = <0x80000000 0x40000000>;
memory@80000000 {
reg = <0x80000000 0x20000000>;
};
reserved-memory {
@ -29,6 +25,49 @@
no-map;
reg = <0xbf000000 0x01000000>; /* 16M */
};
flash_memory: region@98000000 {
no-map;
reg = <0x98000000 0x04000000>; /* 64M */
};
};
leds {
compatible = "gpio-leds";
fault {
gpios = <&gpio ASPEED_GPIO(N, 2) GPIO_ACTIVE_LOW>;
};
identify {
gpios = <&gpio ASPEED_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
};
power {
gpios = <&gpio ASPEED_GPIO(R, 5) GPIO_ACTIVE_LOW>;
};
};
fsi: gpio-fsi {
compatible = "fsi-master-gpio", "fsi-master";
#address-cells = <2>;
#size-cells = <0>;
clock-gpios = <&gpio ASPEED_GPIO(AA, 0) GPIO_ACTIVE_HIGH>;
data-gpios = <&gpio ASPEED_GPIO(AA, 2) GPIO_ACTIVE_HIGH>;
mux-gpios = <&gpio ASPEED_GPIO(A, 6) GPIO_ACTIVE_HIGH>;
enable-gpios = <&gpio ASPEED_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
trans-gpios = <&gpio ASPEED_GPIO(R, 2) GPIO_ACTIVE_HIGH>;
};
gpio-keys {
compatible = "gpio-keys";
checkstop {
label = "checkstop";
gpios = <&gpio ASPEED_GPIO(J, 2) GPIO_ACTIVE_LOW>;
linux,code = <ASPEED_GPIO(J, 2)>;
};
};
};
@ -38,6 +77,7 @@
status = "okay";
m25p,fast-read;
label = "bmc";
#include "openbmc-flash-layout.dtsi"
};
};
@ -53,6 +93,12 @@
};
};
&lpc_ctrl {
status = "okay";
memory-region = <&flash_memory>;
flash = <&spi1>;
};
&uart1 {
/* Rear RS-232 connector */
status = "okay";
@ -81,6 +127,10 @@
pinctrl-0 = <&pinctrl_rmii1_default>;
};
&i2c1 {
status = "okay";
};
&i2c2 {
status = "okay";
};
@ -133,8 +183,77 @@
&i2c12 {
status = "okay";
max31785@52 {
compatible = "maxim,max31785";
reg = <0x52>;
};
};
&gpio {
nic_func_mode0 {
gpio-hog;
gpios = <ASPEED_GPIO(D, 3) GPIO_ACTIVE_HIGH>;
output-low;
line-name = "nic_func_mode0";
};
nic_func_mode1 {
gpio-hog;
gpios = <ASPEED_GPIO(D, 4) GPIO_ACTIVE_HIGH>;
output-low;
line-name = "nic_func_mode1";
};
};
&vuart {
status = "okay";
};
&gfx {
status = "okay";
};
&pinctrl {
aspeed,external-nodes = <&gfx &lhc>;
};
&pwm_tacho {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default>;
fan@0 {
reg = <0x00>;
aspeed,fan-tach-ch = /bits/ 8 <0x08>;
};
fan@1 {
reg = <0x00>;
aspeed,fan-tach-ch = /bits/ 8 <0x09>;
};
fan@2 {
reg = <0x01>;
aspeed,fan-tach-ch = /bits/ 8 <0x0a>;
};
fan@3 {
reg = <0x01>;
aspeed,fan-tach-ch = /bits/ 8 <0x0b>;
};
fan@4 {
reg = <0x00>;
aspeed,fan-tach-ch = /bits/ 8 <0x0c>;
};
fan@5 {
reg = <0x00>;
aspeed,fan-tach-ch = /bits/ 8 <0x0d>;
};
fan@6 {
reg = <0x01>;
aspeed,fan-tach-ch = /bits/ 8 <0x0e>;
};
};

548
sys/gnu/dts/arm/aspeed-bmc-opp-witherspoon.dts Normal file
View File

@ -0,0 +1,548 @@
// SPDX-License-Identifier: GPL-2.0+
/dts-v1/;
#include "aspeed-g5.dtsi"
#include <dt-bindings/gpio/aspeed-gpio.h>
#include <dt-bindings/leds/leds-pca955x.h>
/ {
model = "Witherspoon BMC";
compatible = "ibm,witherspoon-bmc", "aspeed,ast2500";
chosen {
stdout-path = &uart5;
bootargs = "console=ttyS4,115200 earlyprintk";
};
memory@80000000 {
reg = <0x80000000 0x20000000>;
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
flash_memory: region@98000000 {
no-map;
reg = <0x98000000 0x04000000>; /* 64M */
};
};
gpio-keys-polled {
compatible = "gpio-keys-polled";
#address-cells = <1>;
#size-cells = <0>;
poll-interval = <1000>;
fan0-presence {
label = "fan0-presence";
gpios = <&pca0 4 GPIO_ACTIVE_LOW>;
linux,code = <4>;
};
fan1-presence {
label = "fan1-presence";
gpios = <&pca0 5 GPIO_ACTIVE_LOW>;
linux,code = <5>;
};
fan2-presence {
label = "fan2-presence";
gpios = <&pca0 6 GPIO_ACTIVE_LOW>;
linux,code = <6>;
};
fan3-presence {
label = "fan3-presence";
gpios = <&pca0 7 GPIO_ACTIVE_LOW>;
linux,code = <7>;
};
};
leds {
compatible = "gpio-leds";
fan0 {
retain-state-shutdown;
default-state = "keep";
gpios = <&pca0 0 GPIO_ACTIVE_LOW>;
};
fan1 {
retain-state-shutdown;
default-state = "keep";
gpios = <&pca0 1 GPIO_ACTIVE_LOW>;
};
fan2 {
retain-state-shutdown;
default-state = "keep";
gpios = <&pca0 2 GPIO_ACTIVE_LOW>;
};
fan3 {
retain-state-shutdown;
default-state = "keep";
gpios = <&pca0 3 GPIO_ACTIVE_LOW>;
};
front-fault {
retain-state-shutdown;
default-state = "keep";
gpios = <&pca0 13 GPIO_ACTIVE_LOW>;
};
front-power {
retain-state-shutdown;
default-state = "keep";
gpios = <&pca0 14 GPIO_ACTIVE_LOW>;
};
front-id {
retain-state-shutdown;
default-state = "keep";
gpios = <&pca0 15 GPIO_ACTIVE_LOW>;
};
rear-fault {
gpios = <&gpio ASPEED_GPIO(N, 2) GPIO_ACTIVE_LOW>;
};
rear-id {
gpios = <&gpio ASPEED_GPIO(N, 4) GPIO_ACTIVE_LOW>;
};
rear-power {
gpios = <&gpio ASPEED_GPIO(N, 3) GPIO_ACTIVE_LOW>;
};
power-button {
gpios = <&gpio ASPEED_GPIO(R, 5) GPIO_ACTIVE_LOW>;
};
};
fsi: gpio-fsi {
compatible = "fsi-master-gpio", "fsi-master";
#address-cells = <2>;
#size-cells = <0>;
clock-gpios = <&gpio ASPEED_GPIO(AA, 0) GPIO_ACTIVE_HIGH>;
data-gpios = <&gpio ASPEED_GPIO(E, 0) GPIO_ACTIVE_HIGH>;
mux-gpios = <&gpio ASPEED_GPIO(A, 6) GPIO_ACTIVE_HIGH>;
enable-gpios = <&gpio ASPEED_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
trans-gpios = <&gpio ASPEED_GPIO(R, 2) GPIO_ACTIVE_HIGH>;
};
iio-hwmon-dps310 {
compatible = "iio-hwmon";
io-channels = <&dps 0>;
};
iio-hwmon-bmp280 {
compatible = "iio-hwmon";
io-channels = <&bmp 1>;
};
};
&fmc {
status = "okay";
flash@0 {
status = "okay";
label = "bmc";
m25p,fast-read;
#include "openbmc-flash-layout.dtsi"
};
flash@1 {
status = "okay";
label = "alt";
m25p,fast-read;
};
};
&spi1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1_default>;
flash@0 {
status = "okay";
label = "pnor";
m25p,fast-read;
};
};
&uart1 {
/* Rear RS-232 connector */
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_txd1_default
&pinctrl_rxd1_default
&pinctrl_nrts1_default
&pinctrl_ndtr1_default
&pinctrl_ndsr1_default
&pinctrl_ncts1_default
&pinctrl_ndcd1_default
&pinctrl_nri1_default>;
};
&uart2 {
/* APSS */
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_txd2_default &pinctrl_rxd2_default>;
};
&uart5 {
status = "okay";
};
&lpc_ctrl {
status = "okay";
memory-region = <&flash_memory>;
flash = <&spi1>;
};
&mac0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rmii1_default>;
use-ncsi;
};
&i2c2 {
status = "okay";
/* MUX ->
* Samtec 1
* Samtec 2
*/
};
&i2c3 {
status = "okay";
bmp: bmp280@77 {
compatible = "bosch,bmp280";
reg = <0x77>;
#io-channel-cells = <1>;
};
max31785@52 {
compatible = "maxim,max31785a";
reg = <0x52>;
#address-cells = <1>;
#size-cells = <0>;
};
dps: dps310@76 {
compatible = "infineon,dps310";
reg = <0x76>;
#io-channel-cells = <0>;
};
pca0: pca9552@60 {
compatible = "nxp,pca9552";
reg = <0x60>;
#address-cells = <1>;
#size-cells = <0>;
gpio-controller;
#gpio-cells = <2>;
gpio@0 {
reg = <0>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@1 {
reg = <1>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@2 {
reg = <2>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@3 {
reg = <3>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@4 {
reg = <4>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@5 {
reg = <5>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@6 {
reg = <6>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@7 {
reg = <7>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@8 {
reg = <8>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@9 {
reg = <9>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@10 {
reg = <10>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@11 {
reg = <11>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@12 {
reg = <12>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@13 {
reg = <13>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@14 {
reg = <14>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@15 {
reg = <15>;
type = <PCA955X_TYPE_GPIO>;
};
};
power-supply@68 {
compatible = "ibm,cffps1";
reg = <0x68>;
};
power-supply@69 {
compatible = "ibm,cffps1";
reg = <0x69>;
};
};
&i2c4 {
status = "okay";
tmp423a@4c {
compatible = "ti,tmp423";
reg = <0x4c>;
};
ir35221@70 {
compatible = "infineon,ir35221";
reg = <0x70>;
};
ir35221@71 {
compatible = "infineon,ir35221";
reg = <0x71>;
};
};
&i2c5 {
status = "okay";
tmp423a@4c {
compatible = "ti,tmp423";
reg = <0x4c>;
};
ir35221@70 {
compatible = "infineon,ir35221";
reg = <0x70>;
};
ir35221@71 {
compatible = "infineon,ir35221";
reg = <0x71>;
};
};
&i2c9 {
status = "okay";
tmp275@4a {
compatible = "ti,tmp275";
reg = <0x4a>;
};
};
&i2c10 {
/* MUX
* -> PCIe Slot 3
* -> PCIe Slot 4
*/
status = "okay";
};
&i2c11 {
status = "okay";
pca9552: pca9552@60 {
compatible = "nxp,pca9552";
reg = <0x60>;
#address-cells = <1>;
#size-cells = <0>;
gpio-controller;
#gpio-cells = <2>;
gpio-line-names = "PS_SMBUS_RESET_N", "APSS_RESET_N",
"GPU0_TH_OVERT_N_BUFF", "GPU1_TH_OVERT_N_BUFF",
"GPU2_TH_OVERT_N_BUFF", "GPU3_TH_OVERT_N_BUFF",
"GPU4_TH_OVERT_N_BUFF", "GPU5_TH_OVERT_N_BUFF",
"GPU0_PWR_GOOD_BUFF", "GPU1_PWR_GOOD_BUFF",
"GPU2_PWR_GOOD_BUFF", "GPU3_PWR_GOOD_BUFF",
"GPU4_PWR_GOOD_BUFF", "GPU5_PWR_GOOD_BUFF",
"12V_BREAKER_FLT_N", "THROTTLE_UNLATCHED_N";
gpio@0 {
reg = <0>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@1 {
reg = <1>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@2 {
reg = <2>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@3 {
reg = <3>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@4 {
reg = <4>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@5 {
reg = <5>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@6 {
reg = <6>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@7 {
reg = <7>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@8 {
reg = <8>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@9 {
reg = <9>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@10 {
reg = <10>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@11 {
reg = <11>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@12 {
reg = <12>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@13 {
reg = <13>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@14 {
reg = <14>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@15 {
reg = <15>;
type = <PCA955X_TYPE_GPIO>;
};
};
rtc@32 {
compatible = "epson,rx8900";
reg = <0x32>;
};
eeprom@51 {
compatible = "atmel,24c64";
reg = <0x51>;
};
ucd90160@64 {
compatible = "ti,ucd90160";
reg = <0x64>;
};
};
&i2c12 {
status = "okay";
};
&i2c13 {
status = "okay";
};
&vuart {
status = "okay";
};
&gfx {
status = "okay";
};
&pinctrl {
aspeed,external-nodes = <&gfx &lhc>;
};
&wdt1 {
aspeed,reset-type = "none";
aspeed,external-signal;
aspeed,ext-push-pull;
aspeed,ext-active-high;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdtrst1_default>;
};

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sys/gnu/dts/arm/aspeed-bmc-opp-zaius.dts Normal file
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// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
#include "aspeed-g5.dtsi"
#include <dt-bindings/gpio/aspeed-gpio.h>
/ {
model = "Zaius BMC";
compatible = "ingrasys,zaius-bmc", "aspeed,ast2500";
chosen {
stdout-path = &uart5;
bootargs = "console=ttyS4,115200 earlyprintk";
};
memory@80000000 {
reg = <0x80000000 0x40000000>;
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
flash_memory: region@98000000 {
no-map;
reg = <0x98000000 0x04000000>; /* 64M */
};
};
onewire0 {
compatible = "w1-gpio";
gpios = <&gpio ASPEED_GPIO(H, 0) GPIO_ACTIVE_HIGH>;
};
onewire1 {
compatible = "w1-gpio";
gpios = <&gpio ASPEED_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
};
onewire2 {
compatible = "w1-gpio";
gpios = <&gpio ASPEED_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
};
onewire3 {
compatible = "w1-gpio";
gpios = <&gpio ASPEED_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
};
gpio-keys {
compatible = "gpio-keys";
checkstop {
label = "checkstop";
gpios = <&gpio ASPEED_GPIO(F, 7) GPIO_ACTIVE_LOW>;
linux,code = <ASPEED_GPIO(F, 7)>;
};
};
leds {
compatible = "gpio-leds";
sys_boot_status {
label = "System boot status";
gpios = <&gpio ASPEED_GPIO(D, 5) GPIO_ACTIVE_LOW>;
};
attention {
label = "Attention";
gpios = <&gpio ASPEED_GPIO(D, 6) GPIO_ACTIVE_LOW>;
};
plt_fault {
label = "Platform fault";
gpios = <&gpio ASPEED_GPIO(D, 7) GPIO_ACTIVE_LOW>;
};
hdd_fault {
label = "Onboard drive fault";
gpios = <&gpio ASPEED_GPIO(AA, 2) GPIO_ACTIVE_LOW>;
};
};
fsi: gpio-fsi {
compatible = "fsi-master-gpio", "fsi-master";
#address-cells = <2>;
#size-cells = <0>;
trans-gpios = <&gpio ASPEED_GPIO(O, 6) GPIO_ACTIVE_HIGH>;
enable-gpios = <&gpio ASPEED_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
clock-gpios = <&gpio ASPEED_GPIO(G, 0) GPIO_ACTIVE_HIGH>;
data-gpios = <&gpio ASPEED_GPIO(G, 1) GPIO_ACTIVE_HIGH>;
mux-gpios = <&gpio ASPEED_GPIO(P, 6) GPIO_ACTIVE_HIGH>;
};
iio-hwmon {
compatible = "iio-hwmon";
io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>,
<&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>,
<&adc 8>, <&adc 9>, <&adc 10>, <&adc 11>,
<&adc 13>, <&adc 14>, <&adc 15>;
};
iio-hwmon-battery {
compatible = "iio-hwmon";
io-channels = <&adc 12>;
};
};
&fmc {
status = "okay";
flash@0 {
status = "okay";
label = "bmc";
m25p,fast-read;
#include "openbmc-flash-layout.dtsi"
};
};
&spi1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1_default>;
flash@0 {
status = "okay";
label = "pnor";
m25p,fast-read;
};
};
&spi2 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi2ck_default
&pinctrl_spi2cs0_default
&pinctrl_spi2cs1_default
&pinctrl_spi2miso_default
&pinctrl_spi2mosi_default>;
flash@0 {
status = "okay";
};
};
&uart1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_txd1_default
&pinctrl_rxd1_default>;
};
&lpc_ctrl {
status = "okay";
memory-region = <&flash_memory>;
flash = <&spi1>;
};
&lpc_snoop {
status = "okay";
snoop-ports = <0x80>;
};
&uart5 {
status = "okay";
};
&mac0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rmii1_default>;
use-ncsi;
};
&mac1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>;
};
&i2c0 {
status = "okay";
eeprom@50 {
compatible = "atmel,24c64";
reg = <0x50>;
pagesize = <32>;
};
rtc@68 {
compatible = "nxp,pcf8523";
reg = <0x68>;
};
ucd90160@64 {
compatible = "ti,ucd90160";
reg = <0x64>;
};
/* Power sequencer UCD90160 PMBUS @64h
* FRU AT24C64D @50h
* RTC PCF8523 @68h
* Clock buffer 9DBL04 @6dh
*/
};
&i2c1 {
status = "okay";
i2c-switch@71 {
compatible = "nxp,pca9546";
reg = <0x71>;
#address-cells = <1>;
#size-cells = <0>;
};
/* MUX1 PCA9546A @71h
* PCIe 0
* PCIe 1
* PCIe 2
* TPM header
*/
};
&i2c2 {
status = "disabled";
/* OCP Mezz Connector A (OOB SMBUS) */
};
&i2c3 {
status = "disabled";
/* OCP Mezz Connector A (PCIe slot SMBUS) */
};
&i2c4 {
status = "okay";
i2c-switch@71 {
compatible = "nxp,pca9546";
reg = <0x71>;
#address-cells = <1>;
#size-cells = <0>;
};
/* MUX1 PCA9546A @71h
* PCIe 3
* PCIe 4
*/
};
&i2c5 {
status = "disabled";
/* CPU0 PRM 0.7V */
/* CPU0 PRM 1.2V CH03 */
/* CPU0 PRM 0.8V */
/* CPU0 PRM 1.2V CH47 */
};
&i2c6 {
status = "disabled";
/* CPU1 PRM 0.7V */
/* CPU1 PRM 1.2V CH03 */
/* CPU1 PRM 0.8V */
/* CPU1 PRM 1.2V CH47 */
};
&i2c7 {
status = "okay";
pca9541a@70 {
compatible = "nxp,pca9541";
reg = <0x70>;
i2c-arb {
#address-cells = <1>;
#size-cells = <0>;
hotswap@54 {
compatible = "ti,lm5066i";
reg = <0x54>;
};
};
};
/* Master selector PCA9541A @70h (other master: CPU0)
* LM5066I PMBUS @10h
*/
/* 12V Quarter Brick DC/DC Converter Q54SJ12050 @61h */
power-brick@61 {
compatible = "delta,dps800";
reg = <0x61>;
};
/* CPU0 VR ISL68137 0.7V, 0.96V PMBUS @64h */
/* CPU0 VR ISL68137 1.2V CH03 PMBUS @40h */
/* CPU0 VR ISL68137 0.8V PMBUS @60h */
/* CPU0 VR 1.0V IR38064 I2C @11h, PMBUS @41h */
/* CPU0 VR ISL68137 1.2V CH47 PMBUS @41h */
};
&i2c8 {
status = "okay";
/* CPU1 VR ISL68137 0.7V, 0.96V PMBUS @65h */
/* CPU1 VR ISL68137 1.2V CH03 PMBUS @44h */
/* CPU1 VR ISL68137 0.8V PMBUS @61h */
/* CPU1 VR 1.0V IR38064 I2C @12h, PMBUS @42h */
/* CPU0 VR ISL68137 1.2V CH47 PMBUS @45h */
};
&i2c9 {
status = "disabled";
/* Fan board */
};
&i2c10 {
status = "disabled";
};
&i2c11 {
status = "disabled";
/* GPU sideband */
};
&i2c12 {
status = "disabled";
};
&i2c13 {
status = "disabled";
/* MUX PI3USB102
* CPU0 debug
* CPU1 debug
*/
};
&pinctrl {
aspeed,external-nodes = <&gfx &lhc>;
pinctrl_gpioh_unbiased: gpioi_unbiased {
pins = "A8", "C7", "B7", "A7", "D7", "B6", "A6", "E7";
bias-disable;
};
};
&gpio {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpioh_unbiased>;
line_iso_u146_en {
gpio-hog;
gpios = <ASPEED_GPIO(O, 4) GPIO_ACTIVE_HIGH>;
output-high;
line-name = "iso_u164_en";
};
ncsi_mux_en_n {
gpio-hog;
gpios = <ASPEED_GPIO(P, 0) GPIO_ACTIVE_HIGH>;
output-low;
line-name = "ncsi_mux_en_n";
};
line_bmc_i2c2_sw_rst_n {
gpio-hog;
gpios = <ASPEED_GPIO(P, 1) GPIO_ACTIVE_HIGH>;
output-high;
line-name = "bmc_i2c2_sw_rst_n";
};
line_bmc_i2c5_sw_rst_n {
gpio-hog;
gpios = <ASPEED_GPIO(P, 3) GPIO_ACTIVE_HIGH>;
output-high;
line-name = "bmc_i2c5_sw_rst_n";
};
};
&vuart {
status = "okay";
};
&gfx {
status = "okay";
};
&pwm_tacho {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default
&pinctrl_pwm2_default &pinctrl_pwm3_default>;
fan@0 {
reg = <0x00>;
aspeed,fan-tach-ch = /bits/ 8 <0x00>;
};
fan@1 {
reg = <0x01>;
aspeed,fan-tach-ch = /bits/ 8 <0x01>;
};
fan@2 {
reg = <0x02>;
aspeed,fan-tach-ch = /bits/ 8 <0x02>;
};
fan@3 {
reg = <0x03>;
aspeed,fan-tach-ch = /bits/ 8 <0x03>;
};
};

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// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
#include "aspeed-g4.dtsi"
#include <dt-bindings/gpio/aspeed-gpio.h>
/ {
model = "Quanta Q71L BMC";
compatible = "quanta,q71l-bmc", "aspeed,ast2400";
chosen {
stdout-path = &uart5;
bootargs = "console=ttyS4,115200 earlyprintk";
};
memory@40000000 {
reg = <0x40000000 0x8000000>;
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
vga_memory: framebuffer@47800000 {
no-map;
reg = <0x47800000 0x00800000>; /* 8MB */
};
};
leds {
compatible = "gpio-leds";
heartbeat {
gpios = <&gpio ASPEED_GPIO(B, 0) GPIO_ACTIVE_LOW>;
};
power {
gpios = <&gpio ASPEED_GPIO(B, 2) GPIO_ACTIVE_LOW>;
};
identify {
gpios = <&gpio ASPEED_GPIO(B, 3) GPIO_ACTIVE_LOW>;
};
};
iio-hwmon {
compatible = "iio-hwmon";
io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>,
<&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>,
<&adc 8>, <&adc 9>, <&adc 10>;
};
iio-hwmon-battery {
compatible = "iio-hwmon";
io-channels = <&adc 11>;
};
i2c1mux: i2cmux {
compatible = "i2c-mux-gpio";
#address-cells = <1>;
#size-cells = <0>;
/* mux-gpios = <&sgpio 10 GPIO_ACTIVE_HIGH> */
i2c-parent = <&i2c1>;
};
};
&fmc {
status = "okay";
flash@0 {
status = "okay";
label = "bmc";
m25p,fast-read;
#include "openbmc-flash-layout.dtsi"
};
};
&spi {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1_default>;
flash@0 {
status = "okay";
m25p,fast-read;
label = "pnor";
};
};
&pinctrl {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_vgahs_default &pinctrl_vgavs_default
&pinctrl_ddcclk_default &pinctrl_ddcdat_default>;
};
&lpc_snoop {
status = "okay";
snoop-ports = <0x80>;
};
&mac0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rmii1_default>;
use-ncsi;
};
&mac1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>;
};
&uart5 {
status = "okay";
};
&i2c0 {
status = "okay";
};
&i2c1 {
status = "okay";
/* temp2 inlet */
tmp75@4c {
compatible = "ti,tmp75";
reg = <0x4c>;
};
/* temp3 */
tmp75@4e {
compatible = "ti,tmp75";
reg = <0x4e>;
};
/* temp1 */
tmp75@4f {
compatible = "ti,tmp75";
reg = <0x4f>;
};
/* Baseboard FRU */
eeprom@54 {
compatible = "atmel,24c64";
reg = <0x54>;
};
/* FP FRU */
eeprom@57 {
compatible = "atmel,24c64";
reg = <0x57>;
};
};
&i2c2 {
status = "okay";
/* 0: PCIe Slot 2,
* Slot 3,
* Slot 6,
* Slot 7
*/
i2c-switch@74 {
compatible = "nxp,pca9546";
reg = <0x74>;
#address-cells = <1>;
#size-cells = <0>;
i2c-mux-idle-disconnect; /* may use mux@77 next. */
i2c_pcie2: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
};
i2c_pcie3: i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
};
i2c_pcie6: i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
};
i2c_pcie7: i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
};
};
/* 0: PCIe Slot 1,
* Slot 4,
* Slot 5,
* Slot 8,
* Slot 9,
* Slot 10,
* SSD 1,
* SSD 2
*/
i2c-switch@77 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x77>;
i2c-mux-idle-disconnect; /* may use mux@74 next. */
i2c_pcie1: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
};
i2c_pcie4: i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
};
i2c_pcie5: i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
};
i2c_pcie8: i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
};
i2c_pcie9: i2c@4 {
#address-cells = <1>;
#size-cells = <0>;
reg = <4>;
};
i2c_pcie10: i2c@5 {
#address-cells = <1>;
#size-cells = <0>;
reg = <5>;
};
i2c_ssd1: i2c@6 {
#address-cells = <1>;
#size-cells = <0>;
reg = <6>;
};
i2c_ssd2: i2c@7 {
#address-cells = <1>;
#size-cells = <0>;
reg = <7>;
};
};
};
&i2c3 {
status = "okay";
/* BIOS FRU */
eeprom@56 {
compatible = "atmel,24c64";
reg = <0x56>;
};
};
&i2c4 {
status = "okay";
};
&i2c5 {
status = "okay";
};
&i2c6 {
status = "okay";
};
&i2c7 {
status = "okay";
/* 0: PSU4
* PSU1
* PSU3
* PSU2
*/
i2c-switch@70 {
compatible = "nxp,pca9546";
reg = <0x70>;
#address-cells = <1>;
#size-cells = <0>;
i2c_psu4: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
};
i2c_psu1: i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
};
i2c_psu3: i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
};
i2c_psu2: i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
};
};
/* PDB FRU */
eeprom@52 {
compatible = "atmel,24c64";
reg = <0x52>;
};
};
&i2c8 {
status = "okay";
/* BMC FRU */
eeprom@50 {
compatible = "atmel,24c64";
reg = <0x50>;
};
};
&vuart {
status = "okay";
};
&wdt2 {
status = "okay";
};
&pwm_tacho {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm0_default
&pinctrl_pwm1_default
&pinctrl_pwm2_default
&pinctrl_pwm3_default>;
fan@0 {
reg = <0x00>;
aspeed,fan-tach-ch = /bits/ 8 <0x00>;
};
fan@1 {
reg = <0x01>;
aspeed,fan-tach-ch = /bits/ 8 <0x01>;
};
fan@2 {
reg = <0x02>;
aspeed,fan-tach-ch = /bits/ 8 <0x02>;
};
fan@3 {
reg = <0x03>;
aspeed,fan-tach-ch = /bits/ 8 <0x03>;
};
fan@4 {
reg = <0x00>;
aspeed,fan-tach-ch = /bits/ 8 <0x04>;
};
fan@5 {
reg = <0x01>;
aspeed,fan-tach-ch = /bits/ 8 <0x05>;
};
fan@6 {
reg = <0x02>;
aspeed,fan-tach-ch = /bits/ 8 <0x06>;
};
fan@7 {
reg = <0x03>;
aspeed,fan-tach-ch = /bits/ 8 <0x07>;
};
};
&i2c1mux {
i2c@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
/* Memory Riser 1 FRU */
eeprom@50 {
compatible = "atmel,24c02";
reg = <0x50>;
};
/* Memory Riser 2 FRU */
eeprom@51 {
compatible = "atmel,24c02";
reg = <0x51>;
};
/* Memory Riser 3 FRU */
eeprom@52 {
compatible = "atmel,24c02";
reg = <0x52>;
};
/* Memory Riser 4 FRU */
eeprom@53 {
compatible = "atmel,24c02";
reg = <0x53>;
};
};
i2c@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
/* Memory Riser 5 FRU */
eeprom@50 {
compatible = "atmel,24c02";
reg = <0x50>;
};
/* Memory Riser 6 FRU */
eeprom@51 {
compatible = "atmel,24c02";
reg = <0x51>;
};
/* Memory Riser 7 FRU */
eeprom@52 {
compatible = "atmel,24c02";
reg = <0x52>;
};
/* Memory Riser 8 FRU */
eeprom@53 {
compatible = "atmel,24c02";
reg = <0x53>;
};
};
};

168
sys/gnu/dts/arm/aspeed-g4.dtsi
View File

@ -1,5 +1,5 @@
// SPDX-License-Identifier: GPL-2.0
#include "skeleton.dtsi"
// SPDX-License-Identifier: GPL-2.0+
#include <dt-bindings/clock/aspeed-clock.h>
/ {
model = "Aspeed BMC";
@ -42,6 +42,11 @@
};
};
memory@40000000 {
device_type = "memory";
reg = <0x40000000 0>;
};
ahb {
compatible = "simple-bus";
#address-cells = <1>;
@ -54,6 +59,7 @@
#address-cells = <1>;
#size-cells = <0>;
compatible = "aspeed,ast2400-fmc";
clocks = <&syscon ASPEED_CLK_AHB>;
status = "disabled";
interrupts = <19>;
flash@0 {
@ -69,6 +75,7 @@
#address-cells = <1>;
#size-cells = <0>;
compatible = "aspeed,ast2400-spi";
clocks = <&syscon ASPEED_CLK_AHB>;
status = "disabled";
flash@0 {
reg = < 0 >;
@ -89,6 +96,7 @@
compatible = "aspeed,ast2400-mac", "faraday,ftgmac100";
reg = <0x1e660000 0x180>;
interrupts = <2>;
clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>;
status = "disabled";
};
@ -96,6 +104,7 @@
compatible = "aspeed,ast2400-mac", "faraday,ftgmac100";
reg = <0x1e680000 0x180>;
interrupts = <3>;
clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>;
status = "disabled";
};
@ -106,47 +115,12 @@
ranges;
syscon: syscon@1e6e2000 {
compatible = "aspeed,g4-scu", "syscon", "simple-mfd";
compatible = "aspeed,ast2400-scu", "syscon", "simple-mfd";
reg = <0x1e6e2000 0x1a8>;
#address-cells = <1>;
#size-cells = <0>;
clk_clkin: clk_clkin {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <48000000>;
};
clk_hpll: clk_hpll@70 {
#clock-cells = <0>;
compatible = "aspeed,g4-hpll-clock", "fixed-clock";
reg = <0x70>;
clocks = <&clk_clkin>;
clock-frequency = <384000000>;
};
clk_ahb: clk_ahb@70 {
#clock-cells = <0>;
compatible = "aspeed,g4-ahb-clock", "fixed-clock";
reg = <0x70>;
clocks = <&clk_hpll>;
clock-frequency = <192000000>;
};
clk_apb: clk_apb@8 {
#clock-cells = <0>;
compatible = "aspeed,g4-apb-clock", "fixed-clock";
reg = <0x08>;
clocks = <&clk_hpll>;
clock-frequency = <48000000>;
};
clk_uart: clk_uart@2c{
#clock-cells = <0>;
compatible = "aspeed,g4-uart-clock", "fixed-clock";
reg = <0x2c>;
clock-frequency = <24000000>;
};
#clock-cells = <1>;
#reset-cells = <1>;
pinctrl: pinctrl {
compatible = "aspeed,g4-pinctrl";
@ -156,7 +130,8 @@
adc: adc@1e6e9000 {
compatible = "aspeed,ast2400-adc";
reg = <0x1e6e9000 0xb0>;
clocks = <&clk_apb>;
clocks = <&syscon ASPEED_CLK_APB>;
resets = <&syscon ASPEED_RESET_ADC>;
#io-channel-cells = <1>;
status = "disabled";
};
@ -173,6 +148,7 @@
reg = <0x1e780000 0x1000>;
interrupts = <20>;
gpio-ranges = <&pinctrl 0 0 220>;
clocks = <&syscon ASPEED_CLK_APB>;
interrupt-controller;
};
@ -181,7 +157,7 @@
compatible = "aspeed,ast2400-timer";
reg = <0x1e782000 0x90>;
interrupts = <16 17 18 35 36 37 38 39>;
clocks = <&clk_apb>;
clocks = <&syscon ASPEED_CLK_APB>;
clock-names = "PCLK";
};
@ -190,7 +166,7 @@
reg = <0x1e783000 0x20>;
reg-shift = <2>;
interrupts = <9>;
clocks = <&clk_uart>;
clocks = <&syscon ASPEED_CLK_GATE_UART1CLK>;
no-loopback-test;
status = "disabled";
};
@ -200,7 +176,7 @@
reg = <0x1e784000 0x20>;
reg-shift = <2>;
interrupts = <10>;
clocks = <&clk_uart>;
clocks = <&syscon ASPEED_CLK_GATE_UART5CLK>;
no-loopback-test;
status = "disabled";
};
@ -208,11 +184,23 @@
wdt1: watchdog@1e785000 {
compatible = "aspeed,ast2400-wdt";
reg = <0x1e785000 0x1c>;
clocks = <&syscon ASPEED_CLK_APB>;
};
wdt2: watchdog@1e785020 {
compatible = "aspeed,ast2400-wdt";
reg = <0x1e785020 0x1c>;
clocks = <&syscon ASPEED_CLK_APB>;
};
pwm_tacho: pwm-tacho-controller@1e786000 {
compatible = "aspeed,ast2400-pwm-tacho";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x1e786000 0x1000>;
clocks = <&syscon ASPEED_CLK_APB>;
resets = <&syscon ASPEED_RESET_PWM>;
status = "disabled";
};
vuart: serial@1e787000 {
@ -220,17 +208,59 @@
reg = <0x1e787000 0x40>;
reg-shift = <2>;
interrupts = <8>;
clocks = <&clk_uart>;
clocks = <&syscon ASPEED_CLK_APB>;
no-loopback-test;
status = "disabled";
};
lpc: lpc@1e789000 {
compatible = "aspeed,ast2400-lpc", "simple-mfd";
reg = <0x1e789000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x1e789000 0x1000>;
lpc_bmc: lpc-bmc@0 {
compatible = "aspeed,ast2400-lpc-bmc";
reg = <0x0 0x80>;
};
lpc_host: lpc-host@80 {
compatible = "aspeed,ast2400-lpc-host", "simple-mfd", "syscon";
reg = <0x80 0x1e0>;
reg-io-width = <4>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x80 0x1e0>;
lpc_ctrl: lpc-ctrl@0 {
compatible = "aspeed,ast2400-lpc-ctrl";
reg = <0x0 0x80>;
status = "disabled";
};
lpc_snoop: lpc-snoop@0 {
compatible = "aspeed,ast2400-lpc-snoop";
reg = <0x0 0x80>;
interrupts = <8>;
status = "disabled";
};
lhc: lhc@20 {
compatible = "aspeed,ast2400-lhc";
reg = <0x20 0x24 0x48 0x8>;
};
};
};
uart2: serial@1e78d000 {
compatible = "ns16550a";
reg = <0x1e78d000 0x20>;
reg-shift = <2>;
interrupts = <32>;
clocks = <&clk_uart>;
clocks = <&syscon ASPEED_CLK_GATE_UART2CLK>;
no-loopback-test;
status = "disabled";
};
@ -240,7 +270,7 @@
reg = <0x1e78e000 0x20>;
reg-shift = <2>;
interrupts = <33>;
clocks = <&clk_uart>;
clocks = <&syscon ASPEED_CLK_GATE_UART3CLK>;
no-loopback-test;
status = "disabled";
};
@ -250,7 +280,7 @@
reg = <0x1e78f000 0x20>;
reg-shift = <2>;
interrupts = <34>;
clocks = <&clk_uart>;
clocks = <&syscon ASPEED_CLK_GATE_UART4CLK>;
no-loopback-test;
status = "disabled";
};
@ -281,7 +311,8 @@
reg = <0x40 0x40>;
compatible = "aspeed,ast2400-i2c-bus";
clocks = <&clk_apb>;
clocks = <&syscon ASPEED_CLK_APB>;
resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <0>;
interrupt-parent = <&i2c_ic>;
@ -296,7 +327,8 @@
reg = <0x80 0x40>;
compatible = "aspeed,ast2400-i2c-bus";
clocks = <&clk_apb>;
clocks = <&syscon ASPEED_CLK_APB>;
resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <1>;
interrupt-parent = <&i2c_ic>;
@ -311,7 +343,8 @@
reg = <0xc0 0x40>;
compatible = "aspeed,ast2400-i2c-bus";
clocks = <&clk_apb>;
clocks = <&syscon ASPEED_CLK_APB>;
resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <2>;
interrupt-parent = <&i2c_ic>;
@ -327,7 +360,8 @@
reg = <0x100 0x40>;
compatible = "aspeed,ast2400-i2c-bus";
clocks = <&clk_apb>;
clocks = <&syscon ASPEED_CLK_APB>;
resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <3>;
interrupt-parent = <&i2c_ic>;
@ -343,7 +377,8 @@
reg = <0x140 0x40>;
compatible = "aspeed,ast2400-i2c-bus";
clocks = <&clk_apb>;
clocks = <&syscon ASPEED_CLK_APB>;
resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <4>;
interrupt-parent = <&i2c_ic>;
@ -359,7 +394,8 @@
reg = <0x180 0x40>;
compatible = "aspeed,ast2400-i2c-bus";
clocks = <&clk_apb>;
clocks = <&syscon ASPEED_CLK_APB>;
resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <5>;
interrupt-parent = <&i2c_ic>;
@ -375,7 +411,8 @@
reg = <0x1c0 0x40>;
compatible = "aspeed,ast2400-i2c-bus";
clocks = <&clk_apb>;
clocks = <&syscon ASPEED_CLK_APB>;
resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <6>;
interrupt-parent = <&i2c_ic>;
@ -391,7 +428,8 @@
reg = <0x300 0x40>;
compatible = "aspeed,ast2400-i2c-bus";
clocks = <&clk_apb>;
clocks = <&syscon ASPEED_CLK_APB>;
resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <7>;
interrupt-parent = <&i2c_ic>;
@ -407,7 +445,8 @@
reg = <0x340 0x40>;
compatible = "aspeed,ast2400-i2c-bus";
clocks = <&clk_apb>;
clocks = <&syscon ASPEED_CLK_APB>;
resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <8>;
interrupt-parent = <&i2c_ic>;
@ -423,7 +462,8 @@
reg = <0x380 0x40>;
compatible = "aspeed,ast2400-i2c-bus";
clocks = <&clk_apb>;
clocks = <&syscon ASPEED_CLK_APB>;
resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <9>;
interrupt-parent = <&i2c_ic>;
@ -439,7 +479,8 @@
reg = <0x3c0 0x40>;
compatible = "aspeed,ast2400-i2c-bus";
clocks = <&clk_apb>;
clocks = <&syscon ASPEED_CLK_APB>;
resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <10>;
interrupt-parent = <&i2c_ic>;
@ -455,7 +496,8 @@
reg = <0x400 0x40>;
compatible = "aspeed,ast2400-i2c-bus";
clocks = <&clk_apb>;
clocks = <&syscon ASPEED_CLK_APB>;
resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <11>;
interrupt-parent = <&i2c_ic>;
@ -471,7 +513,8 @@
reg = <0x440 0x40>;
compatible = "aspeed,ast2400-i2c-bus";
clocks = <&clk_apb>;
clocks = <&syscon ASPEED_CLK_APB>;
resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <12>;
interrupt-parent = <&i2c_ic>;
@ -487,7 +530,8 @@
reg = <0x480 0x40>;
compatible = "aspeed,ast2400-i2c-bus";
clocks = <&clk_apb>;
clocks = <&syscon ASPEED_CLK_APB>;
resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <13>;
interrupt-parent = <&i2c_ic>;

161
sys/gnu/dts/arm/aspeed-g5.dtsi
View File

@ -1,5 +1,5 @@
// SPDX-License-Identifier: GPL-2.0
#include "skeleton.dtsi"
// SPDX-License-Identifier: GPL-2.0+
#include <dt-bindings/clock/aspeed-clock.h>
/ {
model = "Aspeed BMC";
@ -42,6 +42,11 @@
};
};
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0>;
};
ahb {
compatible = "simple-bus";
#address-cells = <1>;
@ -54,6 +59,7 @@
#address-cells = <1>;
#size-cells = <0>;
compatible = "aspeed,ast2500-fmc";
clocks = <&syscon ASPEED_CLK_AHB>;
status = "disabled";
interrupts = <19>;
flash@0 {
@ -79,6 +85,7 @@
#address-cells = <1>;
#size-cells = <0>;
compatible = "aspeed,ast2500-spi";
clocks = <&syscon ASPEED_CLK_AHB>;
status = "disabled";
flash@0 {
reg = < 0 >;
@ -98,6 +105,7 @@
#address-cells = <1>;
#size-cells = <0>;
compatible = "aspeed,ast2500-spi";
clocks = <&syscon ASPEED_CLK_AHB>;
status = "disabled";
flash@0 {
reg = < 0 >;
@ -123,6 +131,7 @@
compatible = "aspeed,ast2500-mac", "faraday,ftgmac100";
reg = <0x1e660000 0x180>;
interrupts = <2>;
clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>;
status = "disabled";
};
@ -130,6 +139,7 @@
compatible = "aspeed,ast2500-mac", "faraday,ftgmac100";
reg = <0x1e680000 0x180>;
interrupts = <3>;
clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>;
status = "disabled";
};
@ -140,55 +150,18 @@
ranges;
syscon: syscon@1e6e2000 {
compatible = "aspeed,g5-scu", "syscon", "simple-mfd";
compatible = "aspeed,ast2500-scu", "syscon", "simple-mfd";
reg = <0x1e6e2000 0x1a8>;
#address-cells = <1>;
#size-cells = <0>;
clk_clkin: clk_clkin@70 {
#clock-cells = <0>;
compatible = "aspeed,g5-clkin-clock", "fixed-clock";
reg = <0x70>;
clock-frequency = <24000000>;
};
clk_hpll: clk_hpll@24 {
#clock-cells = <0>;
compatible = "aspeed,g5-hpll-clock", "fixed-clock";
reg = <0x24>;
clocks = <&clk_clkin>;
clock-frequency = <792000000>;
};
clk_ahb: clk_ahb@70 {
#clock-cells = <0>;
compatible = "aspeed,g5-ahb-clock", "fixed-clock";
reg = <0x70>;
clocks = <&clk_hpll>;
clock-frequency = <198000000>;
};
clk_apb: clk_apb@8 {
#clock-cells = <0>;
compatible = "aspeed,g5-apb-clock", "fixed-clock";
reg = <0x08>;
clocks = <&clk_hpll>;
clock-frequency = <24750000>;
};
clk_uart: clk_uart@2c {
#clock-cells = <0>;
compatible = "aspeed,uart-clock", "fixed-clock";
reg = <0x2c>;
clock-frequency = <24000000>;
};
#clock-cells = <1>;
#reset-cells = <1>;
pinctrl: pinctrl {
compatible = "aspeed,g5-pinctrl";
aspeed,external-nodes = <&gfx &lhc>;
};
};
gfx: display@1e6e6000 {
@ -200,7 +173,8 @@
adc: adc@1e6e9000 {
compatible = "aspeed,ast2500-adc";
reg = <0x1e6e9000 0xb0>;
clocks = <&clk_apb>;
clocks = <&syscon ASPEED_CLK_APB>;
resets = <&syscon ASPEED_RESET_ADC>;
#io-channel-cells = <1>;
status = "disabled";
};
@ -217,6 +191,7 @@
reg = <0x1e780000 0x1000>;
interrupts = <20>;
gpio-ranges = <&pinctrl 0 0 220>;
clocks = <&syscon ASPEED_CLK_APB>;
interrupt-controller;
};
@ -225,7 +200,7 @@
compatible = "aspeed,ast2400-timer";
reg = <0x1e782000 0x90>;
interrupts = <16 17 18 35 36 37 38 39>;
clocks = <&clk_apb>;
clocks = <&syscon ASPEED_CLK_APB>;
clock-names = "PCLK";
};
@ -234,7 +209,7 @@
reg = <0x1e783000 0x20>;
reg-shift = <2>;
interrupts = <9>;
clocks = <&clk_uart>;
clocks = <&syscon ASPEED_CLK_GATE_UART1CLK>;
no-loopback-test;
status = "disabled";
};
@ -244,7 +219,7 @@
reg = <0x1e784000 0x20>;
reg-shift = <2>;
interrupts = <10>;
clocks = <&clk_uart>;
clocks = <&syscon ASPEED_CLK_GATE_UART5CLK>;
no-loopback-test;
status = "disabled";
};
@ -252,16 +227,39 @@
wdt1: watchdog@1e785000 {
compatible = "aspeed,ast2500-wdt";
reg = <0x1e785000 0x20>;
clocks = <&syscon ASPEED_CLK_APB>;
};
wdt2: watchdog@1e785020 {
compatible = "aspeed,ast2500-wdt";
reg = <0x1e785020 0x20>;
clocks = <&syscon ASPEED_CLK_APB>;
};
wdt3: watchdog@1e785040 {
compatible = "aspeed,ast2500-wdt";
reg = <0x1e785040 0x20>;
clocks = <&syscon ASPEED_CLK_APB>;
status = "disabled";
};
pwm_tacho: pwm-tacho-controller@1e786000 {
compatible = "aspeed,ast2500-pwm-tacho";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x1e786000 0x1000>;
clocks = <&syscon ASPEED_CLK_APB>;
resets = <&syscon ASPEED_RESET_PWM>;
status = "disabled";
};
vuart: serial@1e787000 {
compatible = "aspeed,ast2500-vuart";
reg = <0x1e787000 0x40>;
reg-shift = <2>;
interrupts = <8>;
clocks = <&syscon ASPEED_CLK_APB>;
no-loopback-test;
status = "disabled";
};
@ -288,6 +286,19 @@
reg-io-width = <4>;
lpc_ctrl: lpc-ctrl@0 {
compatible = "aspeed,ast2500-lpc-ctrl";
reg = <0x0 0x80>;
status = "disabled";
};
lpc_snoop: lpc-snoop@0 {
compatible = "aspeed,ast2500-lpc-snoop";
reg = <0x0 0x80>;
interrupts = <8>;
status = "disabled";
};
lhc: lhc@20 {
compatible = "aspeed,ast2500-lhc";
reg = <0x20 0x24 0x48 0x8>;
@ -295,22 +306,12 @@
};
};
vuart: serial@1e787000 {
compatible = "aspeed,ast2500-vuart";
reg = <0x1e787000 0x40>;
reg-shift = <2>;
interrupts = <10>;
clocks = <&clk_uart>;
no-loopback-test;
status = "disabled";
};
uart2: serial@1e78d000 {
compatible = "ns16550a";
reg = <0x1e78d000 0x20>;
reg-shift = <2>;
interrupts = <32>;
clocks = <&clk_uart>;
clocks = <&syscon ASPEED_CLK_GATE_UART2CLK>;
no-loopback-test;
status = "disabled";
};
@ -320,7 +321,7 @@
reg = <0x1e78e000 0x20>;
reg-shift = <2>;
interrupts = <33>;
clocks = <&clk_uart>;
clocks = <&syscon ASPEED_CLK_GATE_UART3CLK>;
no-loopback-test;
status = "disabled";
};
@ -330,7 +331,7 @@
reg = <0x1e78f000 0x20>;
reg-shift = <2>;
interrupts = <34>;
clocks = <&clk_uart>;
clocks = <&syscon ASPEED_CLK_GATE_UART4CLK>;
no-loopback-test;
status = "disabled";
};
@ -361,7 +362,8 @@
reg = <0x40 0x40>;
compatible = "aspeed,ast2500-i2c-bus";
clocks = <&clk_apb>;
clocks = <&syscon ASPEED_CLK_APB>;
resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <0>;
interrupt-parent = <&i2c_ic>;
@ -376,7 +378,8 @@
reg = <0x80 0x40>;
compatible = "aspeed,ast2500-i2c-bus";
clocks = <&clk_apb>;
clocks = <&syscon ASPEED_CLK_APB>;
resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <1>;
interrupt-parent = <&i2c_ic>;
@ -391,7 +394,8 @@
reg = <0xc0 0x40>;
compatible = "aspeed,ast2500-i2c-bus";
clocks = <&clk_apb>;
clocks = <&syscon ASPEED_CLK_APB>;
resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <2>;
interrupt-parent = <&i2c_ic>;
@ -407,7 +411,8 @@
reg = <0x100 0x40>;
compatible = "aspeed,ast2500-i2c-bus";
clocks = <&clk_apb>;
clocks = <&syscon ASPEED_CLK_APB>;
resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <3>;
interrupt-parent = <&i2c_ic>;
@ -423,7 +428,8 @@
reg = <0x140 0x40>;
compatible = "aspeed,ast2500-i2c-bus";
clocks = <&clk_apb>;
clocks = <&syscon ASPEED_CLK_APB>;
resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <4>;
interrupt-parent = <&i2c_ic>;
@ -439,7 +445,8 @@
reg = <0x180 0x40>;
compatible = "aspeed,ast2500-i2c-bus";
clocks = <&clk_apb>;
clocks = <&syscon ASPEED_CLK_APB>;
resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <5>;
interrupt-parent = <&i2c_ic>;
@ -455,7 +462,8 @@
reg = <0x1c0 0x40>;
compatible = "aspeed,ast2500-i2c-bus";
clocks = <&clk_apb>;
clocks = <&syscon ASPEED_CLK_APB>;
resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <6>;
interrupt-parent = <&i2c_ic>;
@ -471,7 +479,8 @@
reg = <0x300 0x40>;
compatible = "aspeed,ast2500-i2c-bus";
clocks = <&clk_apb>;
clocks = <&syscon ASPEED_CLK_APB>;
resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <7>;
interrupt-parent = <&i2c_ic>;
@ -487,7 +496,8 @@
reg = <0x340 0x40>;
compatible = "aspeed,ast2500-i2c-bus";
clocks = <&clk_apb>;
clocks = <&syscon ASPEED_CLK_APB>;
resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <8>;
interrupt-parent = <&i2c_ic>;
@ -503,7 +513,8 @@
reg = <0x380 0x40>;
compatible = "aspeed,ast2500-i2c-bus";
clocks = <&clk_apb>;
clocks = <&syscon ASPEED_CLK_APB>;
resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <9>;
interrupt-parent = <&i2c_ic>;
@ -519,7 +530,8 @@
reg = <0x3c0 0x40>;
compatible = "aspeed,ast2500-i2c-bus";
clocks = <&clk_apb>;
clocks = <&syscon ASPEED_CLK_APB>;
resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <10>;
interrupt-parent = <&i2c_ic>;
@ -535,7 +547,8 @@
reg = <0x400 0x40>;
compatible = "aspeed,ast2500-i2c-bus";
clocks = <&clk_apb>;
clocks = <&syscon ASPEED_CLK_APB>;
resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <11>;
interrupt-parent = <&i2c_ic>;
@ -551,7 +564,8 @@
reg = <0x440 0x40>;
compatible = "aspeed,ast2500-i2c-bus";
clocks = <&clk_apb>;
clocks = <&syscon ASPEED_CLK_APB>;
resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <12>;
interrupt-parent = <&i2c_ic>;
@ -567,7 +581,8 @@
reg = <0x480 0x40>;
compatible = "aspeed,ast2500-i2c-bus";
clocks = <&clk_apb>;
clocks = <&syscon ASPEED_CLK_APB>;
resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <13>;
interrupt-parent = <&i2c_ic>;

12
sys/gnu/dts/arm/at91-ariag25.dts
View File

@ -58,6 +58,18 @@
};
};
tcb0: timer@f8008000 {
timer@0 {
compatible = "atmel,tcb-timer";
reg = <0>;
};
timer@1 {
compatible = "atmel,tcb-timer";
reg = <1>;
};
};
i2c0: i2c@f8010000 {
status = "okay";
};

12
sys/gnu/dts/arm/at91-ariettag25.dts
View File

@ -46,6 +46,18 @@
};
};
tcb0: timer@f8008000 {
timer@0 {
compatible = "atmel,tcb-timer";
reg = <0>;
};
timer@1 {
compatible = "atmel,tcb-timer";
reg = <1>;
};
};
usb2: gadget@f803c000 {
status = "okay";
};

12
sys/gnu/dts/arm/at91-cosino.dtsi
View File

@ -37,6 +37,18 @@
ahb {
apb {
tcb0: timer@f8008000 {
timer@0 {
compatible = "atmel,tcb-timer";
reg = <0>;
};
timer@1 {
compatible = "atmel,tcb-timer";
reg = <1>;
};
};
mmc0: mmc@f0008000 {
pinctrl-0 = <
&pinctrl_board_mmc0

12
sys/gnu/dts/arm/at91-foxg20.dts
View File

@ -34,6 +34,18 @@
ahb {
apb {
tcb0: timer@fffa0000 {
timer@0 {
compatible = "atmel,tcb-timer";
reg = <0>, <1>;
};
timer@2 {
compatible = "atmel,tcb-timer";
reg = <2>;
};
};
usb1: gadget@fffa4000 {
atmel,vbus-gpio = <&pioC 6 GPIO_ACTIVE_HIGH>;
status = "okay";

12
sys/gnu/dts/arm/at91-kizbox.dts
View File

@ -31,6 +31,18 @@
ahb {
apb {
tcb0: timer@fffa0000 {
timer@0 {
compatible = "atmel,tcb-timer";
reg = <0>, <1>;
};
timer@2 {
compatible = "atmel,tcb-timer";
reg = <2>;
};
};
macb0: ethernet@fffc4000 {
phy-mode = "mii";
pinctrl-0 = <&pinctrl_macb_rmii

12
sys/gnu/dts/arm/at91-kizbox2.dts
View File

@ -94,6 +94,18 @@
};
};
tcb0: timer@f0010000 {
timer@0 {
compatible = "atmel,tcb-timer";
reg = <0>;
};
timer@1 {
compatible = "atmel,tcb-timer";
reg = <1>;
};
};
usart0: serial@f001c000 {
status = "okay";
};

12
sys/gnu/dts/arm/at91-kizboxmini.dts
View File

@ -34,6 +34,18 @@
ahb {
apb {
tcb0: timer@f8008000 {
timer@0 {
compatible = "atmel,tcb-timer";
reg = <0>;
};
timer@1 {
compatible = "atmel,tcb-timer";
reg = <1>;
};
};
usart0: serial@f801c000 {
status = "okay";
};

12
sys/gnu/dts/arm/at91-linea.dtsi
View File

@ -27,6 +27,18 @@
clock-frequency = <12000000>;
};
&tcb0 {
timer@0 {
compatible = "atmel,tcb-timer";
reg = <0>;
};
timer@1 {
compatible = "atmel,tcb-timer";
reg = <1>;
};
};
&i2c0 {
status = "okay";

244
sys/gnu/dts/arm/at91-natte.dtsi Normal file
View File

@ -0,0 +1,244 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* at91-natte.dts - Device Tree include file for the Natte board
*
* Copyright (C) 2017 Axentia Technologies AB
*
* Author: Peter Rosin <peda@axentia.se>
*/
/ {
mux: mux-controller {
compatible = "gpio-mux";
#mux-control-cells = <0>;
mux-gpios = <&ioexp 0 GPIO_ACTIVE_HIGH>,
<&ioexp 1 GPIO_ACTIVE_HIGH>,
<&ioexp 2 GPIO_ACTIVE_HIGH>;
};
batntc-mux {
compatible = "io-channel-mux";
io-channels = <&adc 5>;
io-channel-names = "parent";
mux-controls = <&mux>;
channels =
"batntc0", "batntc1", "batntc2", "batntc3",
"batntc4", "batntc5", "batntc6", "batntc7";
};
batv-mux {
compatible = "io-channel-mux";
io-channels = <&adc 6>;
io-channel-names = "parent";
mux-controls = <&mux>;
channels =
"batv0", "batv1", "batv2", "batv3",
"batv4", "batv5", "batv6", "batv7";
};
iout-mux {
compatible = "io-channel-mux";
io-channels = <&adc 7>;
io-channel-names = "parent";
mux-controls = <&mux>;
channels =
"iout0", "iout1", "iout2", "iout3",
"iout4", "iout5", "iout6", "iout7";
};
i2c-mux {
compatible = "i2c-mux";
mux-locked;
i2c-parent = <&i2c0>;
mux-controls = <&mux>;
#address-cells = <1>;
#size-cells = <0>;
i2c@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
charger@9 {
compatible = "ti,bq24735";
reg = <0x9>;
ti,charge-current = <2000>;
ti,charge-voltage = <16800>;
poll-interval = <20000>;
};
};
i2c@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
charger@9 {
compatible = "ti,bq24735";
reg = <0x9>;
ti,charge-current = <2000>;
ti,charge-voltage = <16800>;
poll-interval = <20000>;
};
};
i2c@2 {
reg = <2>;
#address-cells = <1>;
#size-cells = <0>;
charger@9 {
compatible = "ti,bq24735";
reg = <0x9>;
ti,charge-current = <2000>;
ti,charge-voltage = <16800>;
poll-interval = <20000>;
};
};
i2c@3 {
reg = <3>;
#address-cells = <1>;
#size-cells = <0>;
charger@9 {
compatible = "ti,bq24735";
reg = <0x9>;
ti,charge-current = <2000>;
ti,charge-voltage = <16800>;
poll-interval = <20000>;
};
};
i2c@4 {
reg = <4>;
#address-cells = <1>;
#size-cells = <0>;
charger@9 {
compatible = "ti,bq24735";
reg = <0x9>;
ti,charge-current = <2000>;
ti,charge-voltage = <16800>;
poll-interval = <20000>;
};
};
i2c@5 {
reg = <5>;
#address-cells = <1>;
#size-cells = <0>;
charger@9 {
compatible = "ti,bq24735";
reg = <0x9>;
ti,charge-current = <2000>;
ti,charge-voltage = <16800>;
poll-interval = <20000>;
};
};
i2c@6 {
reg = <6>;
#address-cells = <1>;
#size-cells = <0>;
charger@9 {
compatible = "ti,bq24735";
reg = <0x9>;
ti,charge-current = <2000>;
ti,charge-voltage = <16800>;
poll-interval = <20000>;
};
};
i2c@7 {
reg = <7>;
#address-cells = <1>;
#size-cells = <0>;
charger@9 {
compatible = "ti,bq24735";
reg = <0x9>;
ti,charge-current = <2000>;
ti,charge-voltage = <16800>;
poll-interval = <20000>;
};
};
};
};
&i2c0 {
status = "okay";
ioexp: ioexp@20 {
#gpio-cells = <2>;
compatible = "semtech,sx1502q";
reg = <0x20>;
gpio-controller;
ngpios = <8>;
pinctrl-names = "default";
pinctrl-0 = <&gpio3_cfg_pins>;
gpio3_cfg_pins: gpio3_cfg {
pins = "gpio3";
bias-pull-up;
};
};
adc: adc@48 {
compatible = "ti,ads1015";
reg = <0x48>;
#io-channel-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
channel@4 {
reg = <4>;
ti,gain = <2>;
ti,datarate = <4>;
};
channel@5 {
reg = <5>;
ti,gain = <2>;
ti,datarate = <4>;
};
channel@6 {
reg = <6>;
ti,gain = <1>;
ti,datarate = <4>;
};
channel@7 {
reg = <7>;
ti,gain = <3>;
ti,datarate = <4>;
};
};
};

258
sys/gnu/dts/arm/at91-nattis-2-natte-2.dts Normal file
View File

@ -0,0 +1,258 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* at91-nattis-2-natte-2.dts - Device Tree file for the Linea/Nattis board
*
* Copyright (C) 2017 Axentia Technologies AB
*
* Author: Peter Rosin <peda@axentia.se>
*/
/dts-v1/;
#include "at91-linea.dtsi"
#include "sama5d3_lcd.dtsi"
#include "at91-natte.dtsi"
/ {
model = "Axentia Linea-Nattis v2 Natte v2";
compatible = "axentia,nattis-2", "axentia,natte-2", "axentia,linea",
"atmel,sama5d31", "atmel,sama5d3", "atmel,sama5";
ahb {
apb {
pinctrl@fffff200 {
nattis {
pinctrl_usba_vbus: usba_vbus {
atmel,pins =
<AT91_PIOD 28
AT91_PERIPH_GPIO
AT91_PINCTRL_DEGLITCH>;
};
pinctrl_mmc0_cd: mmc0_cd {
atmel,pins =
<AT91_PIOD 5
AT91_PERIPH_GPIO
AT91_PINCTRL_PULL_UP_DEGLITCH>;
};
pinctrl_lcd_prlud0: lcd_prlud0 {
atmel,pins =
<AT91_PIOA 21
AT91_PERIPH_GPIO
AT91_PINCTRL_OUTPUT_VAL(0)>;
};
pinctrl_lcd_hipow0: lcd_hipow0 {
atmel,pins =
<AT91_PIOA 23
AT91_PERIPH_GPIO
AT91_PINCTRL_OUTPUT_VAL(0)>;
};
};
};
watchdog@fffffe40 {
status = "okay";
};
};
};
gpio-keys {
compatible = "gpio-keys";
wakeup {
label = "Wakeup";
linux,code = <10>;
gpio-key,wakeup;
gpios = <&pioB 27 GPIO_ACTIVE_LOW>;
};
};
panel_reg: panel-regulator {
compatible = "regulator-fixed";
regulator-name = "panel-VCC";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
bl_reg: backlight-regulator {
compatible = "regulator-fixed";
regulator-name = "panel-VDD";
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
};
panel_bl: backlight {
compatible = "pwm-backlight";
pwms = <&hlcdc_pwm 0 100000 0>;
brightness-levels = < 0 1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16 17 18 19
20 21 22 23 24 25 26 27 28 29
30 31 32 33 34 35 36 37 38 39
40 41 42 43 44 45 46 47 48 49
50 51 52 53 54 55 56 57 58 59
60 61 62 63 64 65 66 67 68 69
70 71 72 73 74 75 76 77 78 79
80 81 82 83 84 85 86 87 88 89
90 91 92 93 94 95 96 97 98 99
100>;
default-brightness-level = <40>;
power-supply = <&bl_reg>;
enable-gpios = <&pioA 20 GPIO_ACTIVE_HIGH>;
};
panel: panel {
compatible = "sharp,lq150x1lg11";
backlight = <&panel_bl>;
power-supply = <&panel_reg>;
port {
panel_input: endpoint {
remote-endpoint = <&hlcdc_panel_output>;
};
};
};
sound {
compatible = "simple-audio-card";
simple-audio-card,name = "nattis-tfa9879";
simple-audio-card,format = "i2s";
simple-audio-card,bitclock-master = <&cpu_dai>;
simple-audio-card,frame-master = <&cpu_dai>;
simple-audio-card,widgets = "Line", "Line Out Jack";
simple-audio-card,routing = "Line Out Jack", "LINEOUT";
cpu_dai: simple-audio-card,cpu {
sound-dai = <&ssc0>;
};
simple-audio-card,codec {
sound-dai = <&amp>;
};
};
};
&i2c0 {
status = "okay";
clock-frequency = <100000>;
temp@18 {
compatible = "nxp,se97b", "jedec,jc-42.4-temp";
reg = <0x18>;
smbus-timeout-disable;
};
eeprom@50 {
compatible = "nxp,24c02";
reg = <0x50>;
pagesize = <16>;
};
amp: amplifier@6c {
compatible = "nxp,tfa9879";
reg = <0x6c>;
#sound-dai-cells = <0>;
};
};
&ssc0 {
status = "okay";
atmel,clk-from-rk-pin;
#sound-dai-cells = <0>;
};
&hlcdc {
status = "okay";
hlcdc-display-controller {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcd_base
&pinctrl_lcd_rgb565
&pinctrl_lcd_prlud0
&pinctrl_lcd_hipow0>;
port@0 {
hlcdc_panel_output: endpoint {
remote-endpoint = <&panel_input>;
};
};
};
};
&mmc0 {
status = "okay";
pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0
&pinctrl_mmc0_dat1_3
&pinctrl_mmc0_cd>;
slot@0 {
reg = <0>;
bus-width = <4>;
cd-gpios = <&pioD 5 GPIO_ACTIVE_HIGH>;
};
};
&usart0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart0>;
atmel,use-dma-rx;
};
&nand {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
at91bootstrap@0 {
label = "at91bootstrap";
reg = <0x0 0x40000>;
};
bootloader@40000 {
label = "bootloader";
reg = <0x40000 0x80000>;
};
bootloaderenv@c0000 {
label = "bootloader env";
reg = <0xc0000 0xc0000>;
};
dtb@180000 {
label = "device tree";
reg = <0x180000 0x80000>;
};
kernel@200000 {
label = "kernel";
reg = <0x200000 0x600000>;
};
rootfs@800000 {
label = "rootfs";
reg = <0x800000 0x0f800000>;
};
};
};
&dbgu {
status = "okay";
atmel,use-dma-rx;
};
&usb0 {
status = "okay";
atmel,vbus-gpio = <&pioD 28 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usba_vbus>;
};

12
sys/gnu/dts/arm/at91-qil_a9260.dts
View File

@ -31,6 +31,18 @@
ahb {
apb {
tcb0: timer@fffa0000 {
timer@0 {
compatible = "atmel,tcb-timer";
reg = <0>, <1>;
};
timer@2 {
compatible = "atmel,tcb-timer";
reg = <2>;
};
};
usb1: gadget@fffa4000 {
atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>;
status = "okay";

12
sys/gnu/dts/arm/at91-sam9_l9260.dts
View File

@ -32,6 +32,18 @@
ahb {
apb {
tcb0: timer@fffa0000 {
timer@0 {
compatible = "atmel,tcb-timer";
reg = <0>, <1>;
};
timer@2 {
compatible = "atmel,tcb-timer";
reg = <2>;
};
};
mmc0: mmc@fffa8000 {
pinctrl-0 = <
&pinctrl_board_mmc0

12
sys/gnu/dts/arm/at91-sama5d27_som1_ek.dts
View File

@ -119,6 +119,18 @@
status = "okay";
};
tcb0: timer@f800c000 {
timer0: timer@0 {
compatible = "atmel,tcb-timer";
reg = <0>;
};
timer1: timer@1 {
compatible = "atmel,tcb-timer";
reg = <1>;
};
};
uart1: serial@f8020000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_default>;

413
sys/gnu/dts/arm/at91-sama5d2_ptc_ek.dts Normal file
View File

@ -0,0 +1,413 @@
// SPDX-License-Identifier: (GPL-2.0+ OR X11)
/*
* at91-sama5d2_ptc_ek.dts - Device Tree file for SAMA5D2 PTC EK board
*
* Copyright (C) 2017 Microchip/Atmel,
* 2017 Wenyou Yang <wenyou.yang@microchip.com>
* 2017 Ludovic Desroches <ludovic.desroches@microchip.com>
*/
/dts-v1/;
#include "sama5d2.dtsi"
#include "sama5d2-pinfunc.h"
#include <dt-bindings/mfd/atmel-flexcom.h>
#include <dt-bindings/gpio/gpio.h>
/ {
model = "Atmel SAMA5D2 PTC EK";
compatible = "atmel,sama5d2-ptc_ek", "atmel,sama5d2", "atmel,sama5";
aliases {
serial0 = &uart0;
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
};
chosen {
stdout-path = "serial0:115200n8";
};
clocks {
slow_xtal {
clock-frequency = <32768>;
};
main_xtal {
clock-frequency = <24000000>;
};
};
ahb {
usb0: gadget@300000 {
atmel,vbus-gpio = <&pioA PIN_PA27 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usba_vbus>;
status = "okay";
};
usb1: ohci@400000 {
num-ports = <3>;
atmel,vbus-gpio = <0
&pioA PIN_PB12 GPIO_ACTIVE_HIGH
0
>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb_default>;
status = "okay";
};
usb2: ehci@500000 {
status = "okay";
};
ebi: ebi@10000000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nand_default>;
status = "okay"; /* conflicts with sdmmc1 and qspi0 */
nand_controller: nand-controller {
status = "okay";
nand@3 {
reg = <0x3 0x0 0x2>;
atmel,rb = <0>;
nand-bus-width = <8>;
nand-ecc-mode = "hw";
nand-on-flash-bbt;
label = "atmel_nand";
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
at91bootstrap@0 {
label = "bootstrap";
reg = <0x0 0x40000>;
};
bootloader@40000 {
label = "bootloader";
reg = <0x40000 0xc0000>;
};
bootloaderenv@0x100000 {
label = "bootloader env";
reg = <0x100000 0x40000>;
};
bootloaderenvred@0x140000 {
label = "bootloader env redundant";
reg = <0x140000 0x40000>;
};
dtb@180000 {
label = "device tree";
reg = <0x180000 0x80000>;
};
kernel@200000 {
label = "kernel";
reg = <0x200000 0x600000>;
};
rootfs@800000 {
label = "rootfs";
reg = <0x800000 0x1f800000>;
};
};
};
};
};
sdmmc0: sdio-host@a0000000 {
bus-width = <8>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdmmc0_default>;
non-removable;
mmc-ddr-1_8v;
status = "okay";
};
apb {
spi0: spi@f8000000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi0_default>;
status = "okay";
};
macb0: ethernet@f8008000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_macb0_default &pinctrl_macb0_phy_irq>;
phy-mode = "rmii";
status = "okay";
ethernet-phy@1 {
reg = <0x1>;
interrupt-parent = <&pioA>;
interrupts = <56 IRQ_TYPE_LEVEL_LOW>;
};
};
tcb0: timer@f800c000 {
timer0: timer@0 {
compatible = "atmel,tcb-timer";
reg = <0>;
};
timer1: timer@1 {
compatible = "atmel,tcb-timer";
reg = <1>;
};
};
uart0: serial@f801c000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0_default>;
atmel,use-dma-rx;
atmel,use-dma-tx;
status = "okay";
};
uart2: serial@f8024000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2_default>;
atmel,use-dma-rx;
atmel,use-dma-tx;
status = "okay";
};
i2c0: i2c@f8028000 {
dmas = <0>, <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c0_default>;
status = "okay";
};
flx0: flexcom@f8034000 {
atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;
status = "okay";
i2c2: i2c@600 {
compatible = "atmel,sama5d2-i2c";
reg = <0x600 0x200>;
interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>;
dmas = <0>, <0>;
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
clocks = <&flx0_clk>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flx0_default>;
atmel,fifo-size = <16>;
status = "okay";
};
};
shdwc@f8048010 {
atmel,shdwc-debouncer = <976>;
input@0 {
reg = <0>;
atmel,wakeup-type = "low";
};
};
watchdog@f8048040 {
status = "okay";
};
spi1: spi@fc000000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1_default>;
status = "okay";
};
i2c1: i2c@fc028000 {
dmas = <0>, <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1_default>;
status = "okay";
at24@50 {
compatible = "24c02";
reg = <0x50>;
pagesize = <8>;
};
};
pinctrl@fc038000 {
pinctrl_flx0_default: flx0_default {
pinmux = <PIN_PB28__FLEXCOM0_IO0>,
<PIN_PB29__FLEXCOM0_IO1>;
bias-disable;
};
pinctrl_i2c0_default: i2c0_default {
pinmux = <PIN_PD21__TWD0>,
<PIN_PD22__TWCK0>;
bias-disable;
};
pinctrl_i2c1_default: i2c1_default {
pinmux = <PIN_PC6__TWD1>,
<PIN_PC7__TWCK1>;
bias-disable;
};
pinctrl_key_gpio_default: key_gpio_default {
pinmux = <PIN_PA10__GPIO>;
bias-pull-up;
};
pinctrl_led_gpio_default: led_gpio_default {
pinmux = <PIN_PB6__GPIO>,
<PIN_PB8__GPIO>,
<PIN_PB10__GPIO>;
bias-pull-up;
};
pinctrl_macb0_default: macb0_default {
pinmux = <PIN_PB14__GTXCK>,
<PIN_PB15__GTXEN>,
<PIN_PB16__GRXDV>,
<PIN_PB17__GRXER>,
<PIN_PB18__GRX0>,
<PIN_PB19__GRX1>,
<PIN_PB20__GTX0>,
<PIN_PB21__GTX1>,
<PIN_PB22__GMDC>,
<PIN_PB23__GMDIO>;
bias-disable;
};
pinctrl_macb0_phy_irq: macb0_phy_irq {
pinmux = <PIN_PB24__GPIO>;
bias-disable;
};
pinctrl_nand_default: nand_default {
re_we_data {
pinmux = <PIN_PA22__D0>,
<PIN_PA23__D1>,
<PIN_PA24__D2>,
<PIN_PA25__D3>,
<PIN_PA26__D4>,
<PIN_PA27__D5>,
<PIN_PA28__D6>,
<PIN_PA29__D7>,
<PIN_PA30__NWE_NANDWE>,
<PIN_PB2__NRD_NANDOE>;
bias-pull-up;
};
ale_cle_rdy_cs {
pinmux = <PIN_PB0__A21_NANDALE>,
<PIN_PB1__A22_NANDCLE>,
<PIN_PC8__NANDRDY>,
<PIN_PA31__NCS3>;
bias-pull-up;
};
};
pinctrl_sdmmc0_default: sdmmc0_default {
cmd_data {
pinmux = <PIN_PA1__SDMMC0_CMD>,
<PIN_PA2__SDMMC0_DAT0>,
<PIN_PA3__SDMMC0_DAT1>,
<PIN_PA4__SDMMC0_DAT2>,
<PIN_PA5__SDMMC0_DAT3>,
<PIN_PA6__SDMMC0_DAT4>,
<PIN_PA7__SDMMC0_DAT5>,
<PIN_PA8__SDMMC0_DAT6>,
<PIN_PA9__SDMMC0_DAT7>;
bias-pull-up;
};
ck_cd_vddsel {
pinmux = <PIN_PA0__SDMMC0_CK>,
<PIN_PA11__SDMMC0_VDDSEL>,
<PIN_PA13__SDMMC0_CD>;
bias-disable;
};
};
pinctrl_spi0_default: spi0_default {
pinmux = <PIN_PA14__SPI0_SPCK>,
<PIN_PA15__SPI0_MOSI>,
<PIN_PA16__SPI0_MISO>,
<PIN_PA17__SPI0_NPCS0>;
bias-disable;
};
pinctrl_spi1_default: spi1_default {
pinmux = <PIN_PC1__SPI1_SPCK>,
<PIN_PC2__SPI1_MOSI>,
<PIN_PC3__SPI1_MISO>,
<PIN_PC4__SPI1_NPCS0>;
bias-disable;
};
pinctrl_uart0_default: uart0_default {
pinmux = <PIN_PB26__URXD0>,
<PIN_PB27__UTXD0>;
bias-disable;
};
pinctrl_uart2_default: uart2_default {
pinmux = <PIN_PD23__URXD2>,
<PIN_PD24__UTXD2>;
bias-disable;
};
pinctrl_usb_default: usb_default {
pinmux = <PIN_PB12__GPIO>;
bias-disable;
};
pinctrl_usba_vbus: usba_vbus {
pinmux = <PIN_PB11__GPIO>;
bias-disable;
};
};
};
};
gpio_keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_key_gpio_default>;
bp1 {
label = "PB_USER";
gpios = <&pioA PIN_PA10 GPIO_ACTIVE_LOW>;
linux,code = <0x104>;
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_led_gpio_default>;
status = "okay";
red {
label = "red";
gpios = <&pioA PIN_PB10 GPIO_ACTIVE_HIGH>;
};
green {
label = "green";
gpios = <&pioA PIN_PB8 GPIO_ACTIVE_HIGH>;
};
blue {
label = "blue";
gpios = <&pioA PIN_PB6 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
};
};

12
sys/gnu/dts/arm/at91-sama5d2_xplained.dts
View File

@ -133,6 +133,18 @@
};
};
tcb0: timer@f800c000 {
timer0: timer@0 {
compatible = "atmel,tcb-timer";
reg = <0>;
};
timer1: timer@1 {
compatible = "atmel,tcb-timer";
reg = <1>;
};
};
pdmic@f8018000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pdmic_default>;

12
sys/gnu/dts/arm/at91-sama5d3_xplained.dts
View File

@ -65,6 +65,18 @@
status = "okay";
};
tcb0: timer@f0010000 {
timer0: timer@0 {
compatible = "atmel,tcb-timer";
reg = <0>;
};
timer1: timer@1 {
compatible = "atmel,tcb-timer";
reg = <1>;
};
};
i2c0: i2c@f0014000 {
pinctrl-0 = <&pinctrl_i2c0_pu>;
status = "okay";

12
sys/gnu/dts/arm/at91-sama5d4_ma5d4.dtsi
View File

@ -89,6 +89,18 @@
};
};
tcb2: timer@fc024000 {
timer@0 {
compatible = "atmel,tcb-timer";
reg = <0>;
};
timer@1 {
compatible = "atmel,tcb-timer";
reg = <1>;
};
};
adc0: adc@fc034000 {
pinctrl-names = "default";
pinctrl-0 = <

12
sys/gnu/dts/arm/at91-sama5d4_xplained.dts
View File

@ -130,6 +130,18 @@
status = "okay";
};
tcb2: timer@fc024000 {
timer0: timer@0 {
compatible = "atmel,tcb-timer";
reg = <0>;
};
timer1: timer@1 {
compatible = "atmel,tcb-timer";
reg = <1>;
};
};
adc0: adc@fc034000 {
pinctrl-names = "default";
pinctrl-0 = <

12
sys/gnu/dts/arm/at91-sama5d4ek.dts
View File

@ -174,6 +174,18 @@
status = "okay";
};
tcb2: timer@fc024000 {
timer@0 {
compatible = "atmel,tcb-timer";
reg = <0>;
};
timer@1 {
compatible = "atmel,tcb-timer";
reg = <1>;
};
};
watchdog@fc068640 {
status = "okay";
};

12
sys/gnu/dts/arm/at91-vinco.dts
View File

@ -151,6 +151,18 @@
status = "okay";
};
tcb2: timer@fc024000 {
timer@0 {
compatible = "atmel,tcb-timer";
reg = <0>;
};
timer@1 {
compatible = "atmel,tcb-timer";
reg = <1>;
};
};
macb1: ethernet@fc028000 {
phy-mode = "rmii";
status = "okay";

8
sys/gnu/dts/arm/at91rm9200.dtsi
View File

@ -375,7 +375,9 @@
};
tcb0: timer@fffa0000 {
compatible = "atmel,at91rm9200-tcb";
compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xfffa0000 0x100>;
interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0
18 IRQ_TYPE_LEVEL_HIGH 0
@ -385,7 +387,9 @@
};
tcb1: timer@fffa4000 {
compatible = "atmel,at91rm9200-tcb";
compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xfffa4000 0x100>;
interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0
21 IRQ_TYPE_LEVEL_HIGH 0

12
sys/gnu/dts/arm/at91rm9200ek.dts
View File

@ -32,6 +32,18 @@
ahb {
apb {
tcb0: timer@fffa0000 {
timer@0 {
compatible = "atmel,tcb-timer";
reg = <0>, <1>;
};
timer@2 {
compatible = "atmel,tcb-timer";
reg = <2>;
};
};
usb1: gadget@fffb0000 {
atmel,vbus-gpio = <&pioD 4 GPIO_ACTIVE_HIGH>;
atmel,pullup-gpio = <&pioD 5 GPIO_ACTIVE_HIGH>;

8
sys/gnu/dts/arm/at91sam9260.dtsi
View File

@ -386,7 +386,9 @@
};
tcb0: timer@fffa0000 {
compatible = "atmel,at91rm9200-tcb";
compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xfffa0000 0x100>;
interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0
18 IRQ_TYPE_LEVEL_HIGH 0
@ -396,7 +398,9 @@
};
tcb1: timer@fffdc000 {
compatible = "atmel,at91rm9200-tcb";
compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xfffdc000 0x100>;
interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0
27 IRQ_TYPE_LEVEL_HIGH 0

12
sys/gnu/dts/arm/at91sam9260ek.dts
View File

@ -69,6 +69,18 @@
ahb {
apb {
tcb0: timer@fffa0000 {
timer@0 {
compatible = "atmel,tcb-timer";
reg = <0>, <1>;
};
timer@2 {
compatible = "atmel,tcb-timer";
reg = <2>;
};
};
usb1: gadget@fffa4000 {
atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>;
status = "okay";

6
sys/gnu/dts/arm/at91sam9261.dtsi
View File

@ -80,7 +80,7 @@
status = "disabled";
};
fb0: fb@0x00600000 {
fb0: fb@600000 {
compatible = "atmel,at91sam9261-lcdc";
reg = <0x00600000 0x1000>;
interrupts = <21 IRQ_TYPE_LEVEL_HIGH 3>;
@ -125,7 +125,9 @@
ranges;
tcb0: timer@fffa0000 {
compatible = "atmel,at91rm9200-tcb";
compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xfffa0000 0x100>;
interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>,
<18 IRQ_TYPE_LEVEL_HIGH 0>,

22
sys/gnu/dts/arm/at91sam9261ek.dts
View File

@ -15,6 +15,14 @@
chosen {
bootargs = "rootfstype=ubifs ubi.mtd=5 root=ubi0:rootfs rw";
stdout-path = "serial0:115200n8";
clocksource {
timer = <&timer0>;
};
clockevent {
timer = <&timer1>;
};
};
memory {
@ -36,7 +44,7 @@
status = "okay";
};
fb0: fb@0x00600000 {
fb0: fb@600000 {
display = <&display0>;
atmel,power-control-gpio = <&pioA 12 GPIO_ACTIVE_LOW>;
status = "okay";
@ -125,6 +133,18 @@
};
apb {
tcb0: timer@fffa0000 {
timer0: timer@0 {
compatible = "atmel,tcb-timer";
reg = <0>, <1>;
};
timer1: timer@2 {
compatible = "atmel,tcb-timer";
reg = <2>;
};
};
usb1: gadget@fffa4000 {
atmel,vbus-gpio = <&pioB 29 GPIO_ACTIVE_HIGH>;
status = "okay";

6
sys/gnu/dts/arm/at91sam9263.dtsi
View File

@ -389,7 +389,9 @@
};
tcb0: timer@fff7c000 {
compatible = "atmel,at91rm9200-tcb";
compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xfff7c000 0x100>;
interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&tcb_clk>, <&slow_xtal>;
@ -999,7 +1001,7 @@
};
};
fb0: fb@0x00700000 {
fb0: fb@700000 {
compatible = "atmel,at91sam9263-lcdc";
reg = <0x00700000 0x1000>;
interrupts = <26 IRQ_TYPE_LEVEL_HIGH 3>;

14
sys/gnu/dts/arm/at91sam9263ek.dts
View File

@ -37,6 +37,18 @@
status = "okay";
};
tcb0: timer@fff7c000 {
timer@0 {
compatible = "atmel,tcb-timer";
reg = <0>, <1>;
};
timer@2 {
compatible = "atmel,tcb-timer";
reg = <2>;
};
};
usart0: serial@fff8c000 {
pinctrl-0 = <
&pinctrl_usart0
@ -95,7 +107,7 @@
};
};
fb0: fb@0x00700000 {
fb0: fb@700000 {
display = <&display0>;
status = "okay";

12
sys/gnu/dts/arm/at91sam9g20ek_common.dtsi
View File

@ -51,6 +51,18 @@
status = "okay";
};
tcb0: timer@fffa0000 {
timer@0 {
compatible = "atmel,tcb-timer";
reg = <0>, <1>;
};
timer@2 {
compatible = "atmel,tcb-timer";
reg = <2>;
};
};
usart0: serial@fffb0000 {
pinctrl-0 =
<&pinctrl_usart0

2
sys/gnu/dts/arm/at91sam9g25ek.dts
View File

@ -25,7 +25,7 @@
};
i2c0: i2c@f8010000 {
ov2640: camera@0x30 {
ov2640: camera@30 {
compatible = "ovti,ov2640";
reg = <0x30>;
pinctrl-names = "default";

10
sys/gnu/dts/arm/at91sam9g45.dtsi
View File

@ -415,7 +415,9 @@
};
tcb0: timer@fff7c000 {
compatible = "atmel,at91rm9200-tcb";
compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xfff7c000 0x100>;
interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&tcb0_clk>, <&tcb0_clk>, <&tcb0_clk>, <&clk32k>;
@ -423,7 +425,9 @@
};
tcb1: timer@fffd4000 {
compatible = "atmel,at91rm9200-tcb";
compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xfffd4000 0x100>;
interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&tcb0_clk>, <&tcb0_clk>, <&tcb0_clk>, <&clk32k>;
@ -1302,7 +1306,7 @@
};
};
fb0: fb@0x00500000 {
fb0: fb@500000 {
compatible = "atmel,at91sam9g45-lcdc";
reg = <0x00500000 0x1000>;
interrupts = <23 IRQ_TYPE_LEVEL_HIGH 3>;

14
sys/gnu/dts/arm/at91sam9m10g45ek.dts
View File

@ -39,6 +39,18 @@
status = "okay";
};
tcb0: timer@fff7c000 {
timer@0 {
compatible = "atmel,tcb-timer";
reg = <0>, <1>;
};
timer@2 {
compatible = "atmel,tcb-timer";
reg = <2>;
};
};
usart1: serial@fff90000 {
pinctrl-0 =
<&pinctrl_usart1
@ -220,7 +232,7 @@
};
};
fb0: fb@0x00500000 {
fb0: fb@500000 {
display = <&display0>;
status = "okay";

8
sys/gnu/dts/arm/at91sam9n12.dtsi
View File

@ -446,7 +446,9 @@
};
tcb0: timer@f8008000 {
compatible = "atmel,at91sam9x5-tcb";
compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xf8008000 0x100>;
interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&tcb_clk>, <&clk32k>;
@ -454,7 +456,9 @@
};
tcb1: timer@f800c000 {
compatible = "atmel,at91sam9x5-tcb";
compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xf800c000 0x100>;
interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&tcb_clk>, <&clk32k>;

12
sys/gnu/dts/arm/at91sam9n12ek.dts
View File

@ -42,6 +42,18 @@
status = "okay";
};
tcb0: timer@f8008000 {
timer@0 {
compatible = "atmel,tcb-timer";
reg = <0>;
};
timer@1 {
compatible = "atmel,tcb-timer";
reg = <1>;
};
};
i2c0: i2c@f8010000 {
status = "okay";

4
sys/gnu/dts/arm/at91sam9rl.dtsi
View File

@ -124,7 +124,9 @@
ranges;
tcb0: timer@fffa0000 {
compatible = "atmel,at91rm9200-tcb";
compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xfffa0000 0x100>;
interrupts = <16 IRQ_TYPE_LEVEL_HIGH 0>,
<17 IRQ_TYPE_LEVEL_HIGH 0>,

12
sys/gnu/dts/arm/at91sam9rlek.dts
View File

@ -124,6 +124,18 @@
};
apb {
tcb0: timer@fffa0000 {
timer@0 {
compatible = "atmel,tcb-timer";
reg = <0>, <1>;
};
timer@2 {
compatible = "atmel,tcb-timer";
reg = <2>;
};
};
mmc0: mmc@fffa4000 {
pinctrl-0 = <
&pinctrl_board_mmc0

8
sys/gnu/dts/arm/at91sam9x5.dtsi
View File

@ -433,7 +433,9 @@
};
tcb0: timer@f8008000 {
compatible = "atmel,at91sam9x5-tcb";
compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xf8008000 0x100>;
interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&tcb0_clk>, <&clk32k>;
@ -441,7 +443,9 @@
};
tcb1: timer@f800c000 {
compatible = "atmel,at91sam9x5-tcb";
compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xf800c000 0x100>;
interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&tcb0_clk>, <&clk32k>;

12
sys/gnu/dts/arm/at91sam9x5cm.dtsi
View File

@ -24,6 +24,18 @@
ahb {
apb {
tcb0: timer@f8008000 {
timer@0 {
compatible = "atmel,tcb-timer";
reg = <0>;
};
timer@1 {
compatible = "atmel,tcb-timer";
reg = <1>;
};
};
pinctrl@fffff400 {
1wire_cm {
pinctrl_1wire_cm: 1wire_cm-0 {

20
sys/gnu/dts/arm/axp81x.dtsi
View File

@ -48,6 +48,22 @@
interrupt-controller;
#interrupt-cells = <1>;
axp_gpio: axp-gpio {
compatible = "x-powers,axp813-gpio";
gpio-controller;
#gpio-cells = <2>;
gpio0_ldo: gpio0-ldo {
pins = "GPIO0";
function = "ldo";
};
gpio1_ldo: gpio1-ldo {
pins = "GPIO1";
function = "ldo";
};
};
regulators {
/* Default work frequency for buck regulators */
x-powers,dcdc-freq = <3000>;
@ -113,11 +129,15 @@
};
reg_ldo_io0: ldo-io0 {
pinctrl-names = "default";
pinctrl-0 = <&gpio0_ldo>;
/* Disable by default to avoid conflicts with GPIO */
status = "disabled";
};
reg_ldo_io1: ldo-io1 {
pinctrl-names = "default";
pinctrl-0 = <&gpio1_ldo>;
/* Disable by default to avoid conflicts with GPIO */
status = "disabled";
};

2
sys/gnu/dts/arm/bcm11351.dtsi
View File

@ -55,7 +55,7 @@
<0x3ff00100 0x100>;
};
smc@0x3404c000 {
smc@3404c000 {
compatible = "brcm,bcm11351-smc", "brcm,kona-smc";
reg = <0x3404c000 0x400>; /* 1 KiB in SRAM */
};

2
sys/gnu/dts/arm/bcm21664.dtsi
View File

@ -55,7 +55,7 @@
<0x3ff00100 0x100>;
};
smc@0x3404e000 {
smc@3404e000 {
compatible = "brcm,bcm21664-smc", "brcm,kona-smc";
reg = <0x3404e000 0x400>; /* 1 KiB in SRAM */
};

4
sys/gnu/dts/arm/bcm2835-rpi-a-plus.dts
View File

@ -10,12 +10,12 @@
leds {
act {
gpios = <&gpio 47 0>;
gpios = <&gpio 47 GPIO_ACTIVE_HIGH>;
};
pwr {
label = "PWR";
gpios = <&gpio 35 0>;
gpios = <&gpio 35 GPIO_ACTIVE_HIGH>;
default-state = "keep";
linux,default-trigger = "default-on";
};

2
sys/gnu/dts/arm/bcm2835-rpi-a.dts
View File

@ -10,7 +10,7 @@
leds {
act {
gpios = <&gpio 16 1>;
gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
};
};
};

4
sys/gnu/dts/arm/bcm2835-rpi-b-plus.dts
View File

@ -11,12 +11,12 @@
leds {
act {
gpios = <&gpio 47 0>;
gpios = <&gpio 47 GPIO_ACTIVE_HIGH>;
};
pwr {
label = "PWR";
gpios = <&gpio 35 0>;
gpios = <&gpio 35 GPIO_ACTIVE_HIGH>;
default-state = "keep";
linux,default-trigger = "default-on";
};

2
sys/gnu/dts/arm/bcm2835-rpi-b-rev2.dts
View File

@ -11,7 +11,7 @@
leds {
act {
gpios = <&gpio 16 1>;
gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
};
};
};

2
sys/gnu/dts/arm/bcm2835-rpi-b.dts
View File

@ -11,7 +11,7 @@
leds {
act {
gpios = <&gpio 16 1>;
gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
};
};
};

6
sys/gnu/dts/arm/bcm2835.dtsi
View File

@ -18,10 +18,10 @@
soc {
ranges = <0x7e000000 0x20000000 0x02000000>;
dma-ranges = <0x40000000 0x00000000 0x20000000>;
};
arm-pmu {
compatible = "arm,arm1176-pmu";
};
arm-pmu {
compatible = "arm,arm1176-pmu";
};
};

4
sys/gnu/dts/arm/bcm2836-rpi-2-b.dts
View File

@ -15,12 +15,12 @@
leds {
act {
gpios = <&gpio 47 0>;
gpios = <&gpio 47 GPIO_ACTIVE_HIGH>;
};
pwr {
label = "PWR";
gpios = <&gpio 35 0>;
gpios = <&gpio 35 GPIO_ACTIVE_HIGH>;
default-state = "keep";
linux,default-trigger = "default-on";
};

24
sys/gnu/dts/arm/bcm2836.dtsi
View File

@ -9,28 +9,28 @@
<0x40000000 0x40000000 0x00001000>;
dma-ranges = <0xc0000000 0x00000000 0x3f000000>;
local_intc: local_intc {
local_intc: local_intc@40000000 {
compatible = "brcm,bcm2836-l1-intc";
reg = <0x40000000 0x100>;
interrupt-controller;
#interrupt-cells = <1>;
#interrupt-cells = <2>;
interrupt-parent = <&local_intc>;
};
};
arm-pmu {
compatible = "arm,cortex-a7-pmu";
interrupt-parent = <&local_intc>;
interrupts = <9>;
};
arm-pmu {
compatible = "arm,cortex-a7-pmu";
interrupt-parent = <&local_intc>;
interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
};
timer {
compatible = "arm,armv7-timer";
interrupt-parent = <&local_intc>;
interrupts = <0>, // PHYS_SECURE_PPI
<1>, // PHYS_NONSECURE_PPI
<3>, // VIRT_PPI
<2>; // HYP_PPI
interrupts = <0 IRQ_TYPE_LEVEL_HIGH>, // PHYS_SECURE_PPI
<1 IRQ_TYPE_LEVEL_HIGH>, // PHYS_NONSECURE_PPI
<3 IRQ_TYPE_LEVEL_HIGH>, // VIRT_PPI
<2 IRQ_TYPE_LEVEL_HIGH>; // HYP_PPI
always-on;
};
@ -76,7 +76,7 @@
compatible = "brcm,bcm2836-armctrl-ic";
reg = <0x7e00b200 0x200>;
interrupt-parent = <&local_intc>;
interrupts = <8>;
interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
};
&cpu_thermal {

2
sys/gnu/dts/arm/bcm2837-rpi-3-b.dts
View File

@ -20,7 +20,7 @@
leds {
act {
gpios = <&gpio 47 0>;
gpios = <&gpio 47 GPIO_ACTIVE_HIGH>;
};
};
};

14
sys/gnu/dts/arm/bcm2837.dtsi
View File

@ -8,11 +8,11 @@
<0x40000000 0x40000000 0x00001000>;
dma-ranges = <0xc0000000 0x00000000 0x3f000000>;
local_intc: local_intc {
local_intc: local_intc@40000000 {
compatible = "brcm,bcm2836-l1-intc";
reg = <0x40000000 0x100>;
interrupt-controller;
#interrupt-cells = <1>;
#interrupt-cells = <2>;
interrupt-parent = <&local_intc>;
};
};
@ -20,10 +20,10 @@
timer {
compatible = "arm,armv7-timer";
interrupt-parent = <&local_intc>;
interrupts = <0>, // PHYS_SECURE_PPI
<1>, // PHYS_NONSECURE_PPI
<3>, // VIRT_PPI
<2>; // HYP_PPI
interrupts = <0 IRQ_TYPE_LEVEL_HIGH>, // PHYS_SECURE_PPI
<1 IRQ_TYPE_LEVEL_HIGH>, // PHYS_NONSECURE_PPI
<3 IRQ_TYPE_LEVEL_HIGH>, // VIRT_PPI
<2 IRQ_TYPE_LEVEL_HIGH>; // HYP_PPI
always-on;
};
@ -73,7 +73,7 @@
compatible = "brcm,bcm2836-armctrl-ic";
reg = <0x7e00b200 0x200>;
interrupt-parent = <&local_intc>;
interrupts = <8>;
interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
};
&cpu_thermal {

3
sys/gnu/dts/arm/bcm283x.dtsi
View File

@ -2,6 +2,7 @@
#include <dt-bindings/clock/bcm2835.h>
#include <dt-bindings/clock/bcm2835-aux.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
/* firmware-provided startup stubs live here, where the secondary CPUs are
* spinning.
@ -464,7 +465,7 @@
status = "disabled";
};
aux: aux@0x7e215000 {
aux: aux@7e215000 {
compatible = "brcm,bcm2835-aux";
#clock-cells = <1>;
reg = <0x7e215000 0x8>;

2
sys/gnu/dts/arm/bcm958625hr.dts
View File

@ -49,7 +49,7 @@
memory {
device_type = "memory";
reg = <0x60000000 0x80000000>;
reg = <0x60000000 0x20000000>;
};
gpio-restart {

30
sys/gnu/dts/arm/dm814x-clocks.dtsi
View File

@ -337,3 +337,33 @@
clock-frequency = <20000000>;
};
};
&prcm {
default_cm: default_cm@500 {
compatible = "ti,omap4-cm";
reg = <0x500 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x500 0x100>;
default_clkctrl: clk@0 {
compatible = "ti,clkctrl";
reg = <0x0 0x5c>;
#clock-cells = <2>;
};
};
alwon_cm: alwon_cm@1400 {
compatible = "ti,omap4-cm";
reg = <0x1400 0x300>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x1400 0x300>;
alwon_clkctrl: clk@0 {
compatible = "ti,clkctrl";
reg = <0x0 0x228>;
#clock-cells = <2>;
};
};
};

4
sys/gnu/dts/arm/dm814x.dtsi
View File

@ -250,6 +250,8 @@
interrupts = <67>;
ti,hwmods = "timer1";
ti,timer-alwon;
clocks = <&timer1_fck>;
clock-names = "fck";
};
uart1: uart@20000 {
@ -287,6 +289,8 @@
reg = <0x40000 0x2000>;
interrupts = <68>;
ti,hwmods = "timer2";
clocks = <&timer2_fck>;
clock-names = "fck";
};
timer3: timer@42000 {

30
sys/gnu/dts/arm/dm816x-clocks.dtsi
View File

@ -248,3 +248,33 @@
reg = <0x03a8>;
};
};
&prcm {
default_cm: default_cm@500 {
compatible = "ti,omap4-cm";
reg = <0x500 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x500 0x100>;
default_clkctrl: clk@0 {
compatible = "ti,clkctrl";
reg = <0x0 0x5c>;
#clock-cells = <2>;
};
};
alwon_cm: alwon_cm@1400 {
compatible = "ti,omap4-cm";
reg = <0x1400 0x300>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x1400 0x300>;
alwon_clkctrl: clk@0 {
compatible = "ti,clkctrl";
reg = <0x0 0x208>;
#clock-cells = <2>;
};
};
};

9
sys/gnu/dts/arm/dm816x.dtsi
View File

@ -67,8 +67,11 @@
ranges;
prcm: prcm@48180000 {
compatible = "ti,dm816-prcm";
compatible = "ti,dm816-prcm", "simple-bus";
reg = <0x48180000 0x4000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x48180000 0x4000>;
prcm_clocks: clocks {
#address-cells = <1>;
@ -331,6 +334,8 @@
interrupts = <67>;
ti,hwmods = "timer1";
ti,timer-alwon;
clocks = <&timer1_fck>;
clock-names = "fck";
};
timer2: timer@48040000 {
@ -338,6 +343,8 @@
reg = <0x48040000 0x2000>;
interrupts = <68>;
ti,hwmods = "timer2";
clocks = <&timer2_fck>;
clock-names = "fck";
};
timer3: timer@48042000 {

8
sys/gnu/dts/arm/dra62x-j5eco-evm.dts
View File

@ -74,19 +74,19 @@
label = "X-Loader";
reg = <0 0x80000>;
};
partition@0x80000 {
partition@80000 {
label = "U-Boot";
reg = <0x80000 0x1c0000>;
};
partition@0x1c0000 {
partition@1c0000 {
label = "Environment";
reg = <0x240000 0x40000>;
};
partition@0x280000 {
partition@280000 {
label = "Kernel";
reg = <0x280000 0x500000>;
};
partition@0x780000 {
partition@780000 {
label = "Filesystem";
reg = <0x780000 0xf880000>;
};

4
sys/gnu/dts/arm/dra7-evm-common.dtsi
View File

@ -204,7 +204,7 @@
&atl {
assigned-clocks = <&abe_dpll_sys_clk_mux>,
<&atl_gfclk_mux>,
<&atl_clkctrl DRA7_ATL_CLKCTRL 26>,
<&dpll_abe_ck>,
<&dpll_abe_m2x2_ck>,
<&atl_clkin2_ck>;
@ -222,7 +222,7 @@
&mcasp3 {
#sound-dai-cells = <0>;
assigned-clocks = <&mcasp3_ahclkx_mux>;
assigned-clocks = <&l4per_clkctrl DRA7_MCASP3_CLKCTRL 24>;
assigned-clock-parents = <&atl_clkin2_ck>;
status = "okay";

2
sys/gnu/dts/arm/dra7-evm.dts
View File

@ -361,7 +361,7 @@
};
&cpu0 {
cpu0-supply = <&smps123_reg>;
vdd-supply = <&smps123_reg>;
};
&omap_dwc3_2 {

169
sys/gnu/dts/arm/dra7.dtsi
View File

@ -7,8 +7,11 @@
* Based on "omap4.dtsi"
*/
#include <dt-bindings/bus/ti-sysc.h>
#include <dt-bindings/clock/dra7.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/dra.h>
#include <dt-bindings/clock/dra7.h>
#define MAX_SOURCES 400
@ -92,6 +95,8 @@
cooling-min-level = <0>;
cooling-max-level = <2>;
#cooling-cells = <2>; /* min followed by max */
vbb-supply = <&abb_mpu>;
};
};
@ -101,16 +106,26 @@
opp_nom-1000000000 {
opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = <1060000 850000 1150000>;
opp-microvolt = <1060000 850000 1150000>,
<1060000 850000 1150000>;
opp-supported-hw = <0xFF 0x01>;
opp-suspend;
};
opp_od-1176000000 {
opp-hz = /bits/ 64 <1176000000>;
opp-microvolt = <1160000 885000 1160000>;
opp-microvolt = <1160000 885000 1160000>,
<1160000 885000 1160000>;
opp-supported-hw = <0xFF 0x02>;
};
opp_high@1500000000 {
opp-hz = /bits/ 64 <1500000000>;
opp-microvolt = <1210000 950000 1250000>,
<1210000 950000 1250000>;
opp-supported-hw = <0xFF 0x04>;
};
};
/*
@ -224,8 +239,12 @@
};
cm_core_aon: cm_core_aon@5000 {
compatible = "ti,dra7-cm-core-aon";
compatible = "ti,dra7-cm-core-aon",
"simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x5000 0x2000>;
ranges = <0 0x5000 0x2000>;
cm_core_aon_clocks: clocks {
#address-cells = <1>;
@ -237,8 +256,11 @@
};
cm_core: cm_core@8000 {
compatible = "ti,dra7-cm-core";
compatible = "ti,dra7-cm-core", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x8000 0x3000>;
ranges = <0 0x8000 0x3000>;
cm_core_clocks: clocks {
#address-cells = <1>;
@ -263,9 +285,12 @@
};
prm: prm@6000 {
compatible = "ti,dra7-prm";
compatible = "ti,dra7-prm", "simple-bus";
reg = <0x6000 0x3000>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x6000 0x3000>;
prm_clocks: clocks {
#address-cells = <1>;
@ -293,7 +318,6 @@
* node and enable pcie1_ep mode.
*/
pcie1_rc: pcie@51000000 {
compatible = "ti,dra7-pcie";
reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>;
reg-names = "rc_dbics", "ti_conf", "config";
interrupts = <0 232 0x4>, <0 233 0x4>;
@ -323,7 +347,6 @@
};
pcie1_ep: pcie_ep@51000000 {
compatible = "ti,dra7-pcie-ep";
reg = <0x51000000 0x28>, <0x51002000 0x14c>, <0x51001000 0x28>, <0x1000 0x10000000>;
reg-names = "ep_dbics", "ti_conf", "ep_dbics2", "addr_space";
interrupts = <0 232 0x4>;
@ -345,8 +368,7 @@
ranges = <0x51800000 0x51800000 0x3000
0x0 0x30000000 0x10000000>;
status = "disabled";
pcie@51800000 {
compatible = "ti,dra7-pcie";
pcie2_rc: pcie@51800000 {
reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>;
reg-names = "rc_dbics", "ti_conf", "config";
interrupts = <0 355 0x4>, <0 356 0x4>;
@ -876,6 +898,8 @@
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer1";
ti,timer-alwon;
clock-names = "fck";
clocks = <&wkupaon_clkctrl DRA7_TIMER1_CLKCTRL 24>;
};
timer2: timer@48032000 {
@ -1358,7 +1382,7 @@
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "qspi";
clocks = <&qspi_gfclk_div>;
clocks = <&l4per_clkctrl DRA7_QSPI_CLKCTRL 25>;
clock-names = "fck";
num-cs = <4>;
interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
@ -1373,14 +1397,15 @@
ranges;
reg = <0x4a090000 0x20>;
ti,hwmods = "ocp2scp3";
sata_phy: phy@4A096000 {
sata_phy: phy@4a096000 {
compatible = "ti,phy-pipe3-sata";
reg = <0x4A096000 0x80>, /* phy_rx */
<0x4A096400 0x64>, /* phy_tx */
<0x4A096800 0x40>; /* pll_ctrl */
reg-names = "phy_rx", "phy_tx", "pll_ctrl";
syscon-phy-power = <&scm_conf 0x374>;
clocks = <&sys_clkin1>, <&sata_ref_clk>;
clocks = <&sys_clkin1>,
<&l3init_clkctrl DRA7_SATA_CLKCTRL 8>;
clock-names = "sysclk", "refclk";
syscon-pllreset = <&scm_conf 0x3fc>;
#phy-cells = <0>;
@ -1395,9 +1420,9 @@
syscon-pcs = <&scm_conf_pcie 0x10>;
clocks = <&dpll_pcie_ref_ck>,
<&dpll_pcie_ref_m2ldo_ck>,
<&optfclk_pciephy1_32khz>,
<&optfclk_pciephy1_clk>,
<&optfclk_pciephy1_div_clk>,
<&l3init_clkctrl DRA7_PCIE1_CLKCTRL 8>,
<&l3init_clkctrl DRA7_PCIE1_CLKCTRL 9>,
<&l3init_clkctrl DRA7_PCIE1_CLKCTRL 10>,
<&optfclk_pciephy_div>,
<&sys_clkin1>;
clock-names = "dpll_ref", "dpll_ref_m2",
@ -1415,9 +1440,9 @@
syscon-pcs = <&scm_conf_pcie 0x10>;
clocks = <&dpll_pcie_ref_ck>,
<&dpll_pcie_ref_m2ldo_ck>,
<&optfclk_pciephy2_32khz>,
<&optfclk_pciephy2_clk>,
<&optfclk_pciephy2_div_clk>,
<&l3init_clkctrl DRA7_PCIE2_CLKCTRL 8>,
<&l3init_clkctrl DRA7_PCIE2_CLKCTRL 9>,
<&l3init_clkctrl DRA7_PCIE2_CLKCTRL 10>,
<&optfclk_pciephy_div>,
<&sys_clkin1>;
clock-names = "dpll_ref", "dpll_ref_m2",
@ -1434,7 +1459,7 @@
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
phys = <&sata_phy>;
phy-names = "sata-phy";
clocks = <&sata_ref_clk>;
clocks = <&l3init_clkctrl DRA7_SATA_CLKCTRL 8>;
ti,hwmods = "sata";
ports-implemented = <0x1>;
};
@ -1462,7 +1487,7 @@
reg = <0x4a084000 0x400>;
syscon-phy-power = <&scm_conf 0x300>;
clocks = <&usb_phy1_always_on_clk32k>,
<&usb_otg_ss1_refclk960m>;
<&l3init_clkctrl DRA7_USB_OTG_SS1_CLKCTRL 8>;
clock-names = "wkupclk",
"refclk";
#phy-cells = <0>;
@ -1474,7 +1499,7 @@
reg = <0x4a085000 0x400>;
syscon-phy-power = <&scm_conf 0xe74>;
clocks = <&usb_phy2_always_on_clk32k>,
<&usb_otg_ss2_refclk960m>;
<&l3init_clkctrl DRA7_USB_OTG_SS2_CLKCTRL 8>;
clock-names = "wkupclk",
"refclk";
#phy-cells = <0>;
@ -1489,7 +1514,7 @@
syscon-phy-power = <&scm_conf 0x370>;
clocks = <&usb_phy3_always_on_clk32k>,
<&sys_clkin1>,
<&usb_otg_ss1_refclk960m>;
<&l3init_clkctrl DRA7_USB_OTG_SS1_CLKCTRL 8>;
clock-names = "wkupclk",
"sysclk",
"refclk";
@ -1498,11 +1523,17 @@
};
target-module@4a0dd000 {
compatible = "ti,sysc-omap4-sr";
compatible = "ti,sysc-omap4-sr", "ti,sysc";
ti,hwmods = "smartreflex_core";
reg = <0x4a0dd000 0x4>,
<0x4a0dd008 0x4>;
reg-names = "rev", "sysc";
reg = <0x4a0dd038 0x4>;
reg-names = "sysc";
ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
clocks = <&coreaon_clkctrl DRA7_SMARTREFLEX_CORE_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x4a0dd000 0x001000>;
@ -1511,11 +1542,17 @@
};
target-module@4a0d9000 {
compatible = "ti,sysc-omap4-sr";
compatible = "ti,sysc-omap4-sr", "ti,sysc";
ti,hwmods = "smartreflex_mpu";
reg = <0x4a0d9000 0x4>,
<0x4a0d9008 0x4>;
reg-names = "rev", "sysc";
reg = <0x4a0d9038 0x4>;
reg-names = "sysc";
ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
clocks = <&coreaon_clkctrl DRA7_SMARTREFLEX_MPU_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x4a0d9000 0x001000>;
@ -1547,6 +1584,7 @@
dr_mode = "otg";
snps,dis_u3_susphy_quirk;
snps,dis_u2_susphy_quirk;
snps,dis_metastability_quirk;
};
};
@ -1636,7 +1674,7 @@
ti,hwmods = "atl";
ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>,
<&atl_clkin2_ck>, <&atl_clkin3_ck>;
clocks = <&atl_gfclk_mux>;
clocks = <&atl_clkctrl DRA7_ATL_CLKCTRL 26>;
clock-names = "fck";
status = "disabled";
};
@ -1652,8 +1690,8 @@
interrupt-names = "tx", "rx";
dmas = <&edma_xbar 129 1>, <&edma_xbar 128 1>;
dma-names = "tx", "rx";
clocks = <&mcasp1_aux_gfclk_mux>, <&mcasp1_ahclkx_mux>,
<&mcasp1_ahclkr_mux>;
clocks = <&ipu_clkctrl DRA7_MCASP1_CLKCTRL 22>, <&ipu_clkctrl DRA7_MCASP1_CLKCTRL 24>,
<&ipu_clkctrl DRA7_MCASP1_CLKCTRL 28>;
clock-names = "fck", "ahclkx", "ahclkr";
status = "disabled";
};
@ -1669,8 +1707,9 @@
interrupt-names = "tx", "rx";
dmas = <&edma_xbar 131 1>, <&edma_xbar 130 1>;
dma-names = "tx", "rx";
clocks = <&mcasp2_aux_gfclk_mux>, <&mcasp2_ahclkx_mux>,
<&mcasp2_ahclkr_mux>;
clocks = <&l4per_clkctrl DRA7_MCASP2_CLKCTRL 22>,
<&l4per_clkctrl DRA7_MCASP2_CLKCTRL 24>,
<&l4per_clkctrl DRA7_MCASP2_CLKCTRL 28>;
clock-names = "fck", "ahclkx", "ahclkr";
status = "disabled";
};
@ -1686,7 +1725,8 @@
interrupt-names = "tx", "rx";
dmas = <&edma_xbar 133 1>, <&edma_xbar 132 1>;
dma-names = "tx", "rx";
clocks = <&mcasp3_aux_gfclk_mux>, <&mcasp3_ahclkx_mux>;
clocks = <&l4per_clkctrl DRA7_MCASP3_CLKCTRL 22>,
<&l4per_clkctrl DRA7_MCASP3_CLKCTRL 24>;
clock-names = "fck", "ahclkx";
status = "disabled";
};
@ -1702,7 +1742,8 @@
interrupt-names = "tx", "rx";
dmas = <&edma_xbar 135 1>, <&edma_xbar 134 1>;
dma-names = "tx", "rx";
clocks = <&mcasp4_aux_gfclk_mux>, <&mcasp4_ahclkx_mux>;
clocks = <&l4per_clkctrl DRA7_MCASP4_CLKCTRL 22>,
<&l4per_clkctrl DRA7_MCASP4_CLKCTRL 24>;
clock-names = "fck", "ahclkx";
status = "disabled";
};
@ -1718,7 +1759,8 @@
interrupt-names = "tx", "rx";
dmas = <&edma_xbar 137 1>, <&edma_xbar 136 1>;
dma-names = "tx", "rx";
clocks = <&mcasp5_aux_gfclk_mux>, <&mcasp5_ahclkx_mux>;
clocks = <&l4per_clkctrl DRA7_MCASP5_CLKCTRL 22>,
<&l4per_clkctrl DRA7_MCASP5_CLKCTRL 24>;
clock-names = "fck", "ahclkx";
status = "disabled";
};
@ -1734,7 +1776,8 @@
interrupt-names = "tx", "rx";
dmas = <&edma_xbar 139 1>, <&edma_xbar 138 1>;
dma-names = "tx", "rx";
clocks = <&mcasp6_aux_gfclk_mux>, <&mcasp6_ahclkx_mux>;
clocks = <&l4per_clkctrl DRA7_MCASP6_CLKCTRL 22>,
<&l4per_clkctrl DRA7_MCASP6_CLKCTRL 24>;
clock-names = "fck", "ahclkx";
status = "disabled";
};
@ -1750,7 +1793,8 @@
interrupt-names = "tx", "rx";
dmas = <&edma_xbar 141 1>, <&edma_xbar 140 1>;
dma-names = "tx", "rx";
clocks = <&mcasp7_aux_gfclk_mux>, <&mcasp7_ahclkx_mux>;
clocks = <&l4per_clkctrl DRA7_MCASP7_CLKCTRL 22>,
<&l4per_clkctrl DRA7_MCASP7_CLKCTRL 24>;
clock-names = "fck", "ahclkx";
status = "disabled";
};
@ -1766,7 +1810,8 @@
interrupt-names = "tx", "rx";
dmas = <&edma_xbar 143 1>, <&edma_xbar 142 1>;
dma-names = "tx", "rx";
clocks = <&mcasp8_aux_gfclk_mux>, <&mcasp8_ahclkx_mux>;
clocks = <&l4per_clkctrl DRA7_MCASP8_CLKCTRL 22>,
<&l4per_clkctrl DRA7_MCASP8_CLKCTRL 24>;
clock-names = "fck", "ahclkx";
status = "disabled";
};
@ -1788,7 +1833,7 @@
mac: ethernet@48484000 {
compatible = "ti,dra7-cpsw","ti,cpsw";
ti,hwmods = "gmac";
clocks = <&gmac_main_clk>, <&gmac_rft_clk_mux>;
clocks = <&gmac_main_clk>, <&l3init_clkctrl DRA7_GMAC_CLKCTRL 25>;
clock-names = "fck", "cpts";
cpdma_channels = <8>;
ale_entries = <1024>;
@ -1858,7 +1903,7 @@
reg = <0x4ae3c000 0x2000>;
syscon-raminit = <&scm_conf 0x558 0>;
interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&dcan1_sys_clk_mux>;
clocks = <&wkupaon_clkctrl DRA7_DCAN1_CLKCTRL 24>;
status = "disabled";
};
@ -1889,7 +1934,7 @@
reg = <0x58001000 0x1000>;
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "dss_dispc";
clocks = <&dss_dss_clk>;
clocks = <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 8>;
clock-names = "fck";
/* CTRL_CORE_SMA_SW_1 */
syscon-pol = <&scm_conf 0x534>;
@ -1905,8 +1950,11 @@
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
ti,hwmods = "dss_hdmi";
clocks = <&dss_48mhz_clk>, <&dss_hdmi_clk>;
clocks = <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 9>,
<&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 10>;
clock-names = "fck", "sys_clk";
dmas = <&sdma_xbar 76>;
dma-names = "audio_tx";
};
};
@ -2052,6 +2100,19 @@
clocks = <&l3_iclk_div>;
clock-names = "fck";
};
opp_supply_mpu: opp-supply@4a003b20 {
compatible = "ti,omap5-opp-supply";
reg = <0x4a003b20 0xc>;
ti,efuse-settings = <
/* uV offset */
1060000 0x0
1160000 0x4
1210000 0x8
>;
ti,absolute-max-voltage-uv = <1500000>;
};
};
thermal_zones: thermal-zones {
@ -2089,4 +2150,20 @@
temperature = <120000>; /* milli Celsius */
};
/include/ "dra7xx-clocks.dtsi"
#include "dra7xx-clocks.dtsi"
&core_crit {
temperature = <120000>; /* milli Celsius */
};
&gpu_crit {
temperature = <120000>; /* milli Celsius */
};
&dspeve_crit {
temperature = <120000>; /* milli Celsius */
};
&iva_crit {
temperature = <120000>; /* milli Celsius */
};

4
sys/gnu/dts/arm/dra72-evm-common.dtsi
View File

@ -514,7 +514,7 @@
&atl {
assigned-clocks = <&abe_dpll_sys_clk_mux>,
<&atl_gfclk_mux>,
<&atl_clkctrl DRA7_ATL_CLKCTRL 26>,
<&dpll_abe_ck>,
<&dpll_abe_m2x2_ck>,
<&atl_clkin2_ck>;
@ -532,7 +532,7 @@
&mcasp3 {
#sound-dai-cells = <0>;
assigned-clocks = <&mcasp3_ahclkx_mux>;
assigned-clocks = <&l4per_clkctrl DRA7_MCASP3_CLKCTRL 24>;
assigned-clock-parents = <&atl_clkin2_ck>;
status = "okay";

4
sys/gnu/dts/arm/dra72-evm-tps65917.dtsi
View File

@ -148,3 +148,7 @@
&mmc1 {
vqmmc-supply = <&ldo1_reg>;
};
&cpu0 {
vdd-supply = <&smps1_reg>;
};

16
sys/gnu/dts/arm/dra72x.dtsi
View File

@ -25,8 +25,8 @@
<0x58004300 0x20>;
reg-names = "dss", "pll1_clkctrl", "pll1";
clocks = <&dss_dss_clk>,
<&dss_video1_clk>;
clocks = <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 8>,
<&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 12>;
clock-names = "fck", "video1_clk";
};
@ -50,3 +50,15 @@
status = "disabled";
};
};
&pcie1_rc {
compatible = "ti,dra726-pcie-rc", "ti,dra7-pcie";
};
&pcie1_ep {
compatible = "ti,dra726-pcie-ep", "ti,dra7-pcie-ep";
};
&pcie2_rc {
compatible = "ti,dra726-pcie-rc", "ti,dra7-pcie";
};

18
sys/gnu/dts/arm/dra74x.dtsi
View File

@ -93,9 +93,9 @@
reg-names = "dss", "pll1_clkctrl", "pll1",
"pll2_clkctrl", "pll2";
clocks = <&dss_dss_clk>,
<&dss_video1_clk>,
<&dss_video2_clk>;
clocks = <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 8>,
<&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 12>,
<&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 13>;
clock-names = "fck", "video1_clk", "video2_clk";
};
@ -124,3 +124,15 @@
status = "disabled";
};
};
&pcie1_rc {
compatible = "ti,dra746-pcie-rc", "ti,dra7-pcie";
};
&pcie1_ep {
compatible = "ti,dra746-pcie-ep", "ti,dra7-pcie-ep";
};
&pcie2_rc {
compatible = "ti,dra746-pcie-rc", "ti,dra7-pcie";
};

17
sys/gnu/dts/arm/dra76-evm.dts
View File

@ -148,6 +148,7 @@
compatible = "ti,tps65917";
reg = <0x58>;
ti,system-power-controller;
ti,palmas-override-powerhold;
interrupt-controller;
#interrupt-cells = <2>;
@ -421,3 +422,19 @@
spi-max-frequency = <96000000>;
};
};
&pcie2_phy {
status = "okay";
};
&pcie1_rc {
num-lanes = <2>;
phys = <&pcie1_phy>, <&pcie2_phy>;
phy-names = "pcie-phy0", "pcie-phy1";
};
&pcie1_ep {
num-lanes = <2>;
phys = <&pcie1_phy>, <&pcie2_phy>;
phy-names = "pcie-phy0", "pcie-phy1";
};

909
sys/gnu/dts/arm/dra7xx-clocks.dtsi
View File

@ -11,25 +11,25 @@
atl_clkin0_ck: atl_clkin0_ck {
#clock-cells = <0>;
compatible = "ti,dra7-atl-clock";
clocks = <&atl_gfclk_mux>;
clocks = <&atl_clkctrl DRA7_ATL_CLKCTRL 26>;
};
atl_clkin1_ck: atl_clkin1_ck {
#clock-cells = <0>;
compatible = "ti,dra7-atl-clock";
clocks = <&atl_gfclk_mux>;
clocks = <&atl_clkctrl DRA7_ATL_CLKCTRL 26>;
};
atl_clkin2_ck: atl_clkin2_ck {
#clock-cells = <0>;
compatible = "ti,dra7-atl-clock";
clocks = <&atl_gfclk_mux>;
clocks = <&atl_clkctrl DRA7_ATL_CLKCTRL 26>;
};
atl_clkin3_ck: atl_clkin3_ck {
#clock-cells = <0>;
compatible = "ti,dra7-atl-clock";
clocks = <&atl_gfclk_mux>;
clocks = <&atl_clkctrl DRA7_ATL_CLKCTRL 26>;
};
hdmi_clkin_ck: hdmi_clkin_ck {
@ -809,70 +809,6 @@
assigned-clock-parents = <&dpll_core_h22x2_ck>;
};
mcasp1_ahclkr_mux: mcasp1_ahclkr_mux@550 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
ti,bit-shift = <28>;
reg = <0x0550>;
};
mcasp1_ahclkx_mux: mcasp1_ahclkx_mux@550 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
ti,bit-shift = <24>;
reg = <0x0550>;
};
mcasp1_aux_gfclk_mux: mcasp1_aux_gfclk_mux@550 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
ti,bit-shift = <22>;
reg = <0x0550>;
};
timer5_gfclk_mux: timer5_gfclk_mux@558 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
ti,bit-shift = <24>;
reg = <0x0558>;
};
timer6_gfclk_mux: timer6_gfclk_mux@560 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
ti,bit-shift = <24>;
reg = <0x0560>;
};
timer7_gfclk_mux: timer7_gfclk_mux@568 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
ti,bit-shift = <24>;
reg = <0x0568>;
};
timer8_gfclk_mux: timer8_gfclk_mux@570 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
ti,bit-shift = <24>;
reg = <0x0570>;
};
uart6_gfclk_mux: uart6_gfclk_mux@580 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
ti,bit-shift = <24>;
reg = <0x0580>;
};
dummy_ck: dummy_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
@ -1188,39 +1124,8 @@
clocks = <&sys_clkin1>, <&abe_lp_clk_div>;
reg = <0x0108>;
};
gpio1_dbclk: gpio1_dbclk@1838 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
ti,bit-shift = <8>;
reg = <0x1838>;
};
dcan1_sys_clk_mux: dcan1_sys_clk_mux@1888 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&sys_clkin2>;
ti,bit-shift = <24>;
reg = <0x1888>;
};
timer1_gfclk_mux: timer1_gfclk_mux@1840 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
ti,bit-shift = <24>;
reg = <0x1840>;
};
uart10_gfclk_mux: uart10_gfclk_mux@1880 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
ti,bit-shift = <24>;
reg = <0x1880>;
};
};
&cm_core_clocks {
dpll_pcie_ref_ck: dpll_pcie_ref_ck@200 {
#clock-cells = <0>;
@ -1255,22 +1160,6 @@
reg = <0x021c>, <0x0220>;
};
optfclk_pciephy1_32khz: optfclk_pciephy1_32khz@4a0093b0 {
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
#clock-cells = <0>;
reg = <0x13b0>;
ti,bit-shift = <8>;
};
optfclk_pciephy2_32khz: optfclk_pciephy2_32khz@4a0093b8 {
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
#clock-cells = <0>;
reg = <0x13b8>;
ti,bit-shift = <8>;
};
optfclk_pciephy_div: optfclk_pciephy_div@4a00821c {
compatible = "ti,divider-clock";
clocks = <&apll_pcie_ck>;
@ -1281,38 +1170,6 @@
ti,max-div = <2>;
};
optfclk_pciephy1_clk: optfclk_pciephy1_clk@4a0093b0 {
compatible = "ti,gate-clock";
clocks = <&apll_pcie_ck>;
#clock-cells = <0>;
reg = <0x13b0>;
ti,bit-shift = <9>;
};
optfclk_pciephy2_clk: optfclk_pciephy2_clk@4a0093b8 {
compatible = "ti,gate-clock";
clocks = <&apll_pcie_ck>;
#clock-cells = <0>;
reg = <0x13b8>;
ti,bit-shift = <9>;
};
optfclk_pciephy1_div_clk: optfclk_pciephy1_div_clk@4a0093b0 {
compatible = "ti,gate-clock";
clocks = <&optfclk_pciephy_div>;
#clock-cells = <0>;
reg = <0x13b0>;
ti,bit-shift = <10>;
};
optfclk_pciephy2_div_clk: optfclk_pciephy2_div_clk@4a0093b8 {
compatible = "ti,gate-clock";
clocks = <&optfclk_pciephy_div>;
#clock-cells = <0>;
reg = <0x13b8>;
ti,bit-shift = <10>;
};
apll_pcie_clkvcoldo: apll_pcie_clkvcoldo {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
@ -1541,167 +1398,6 @@
reg = <0x06c0>;
};
dss_32khz_clk: dss_32khz_clk@1120 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
ti,bit-shift = <11>;
reg = <0x1120>;
};
dss_48mhz_clk: dss_48mhz_clk@1120 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&func_48m_fclk>;
ti,bit-shift = <9>;
reg = <0x1120>;
};
dss_dss_clk: dss_dss_clk@1120 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&dpll_per_h12x2_ck>;
ti,bit-shift = <8>;
reg = <0x1120>;
ti,set-rate-parent;
};
dss_hdmi_clk: dss_hdmi_clk@1120 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&hdmi_dpll_clk_mux>;
ti,bit-shift = <10>;
reg = <0x1120>;
};
dss_video1_clk: dss_video1_clk@1120 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&video1_dpll_clk_mux>;
ti,bit-shift = <12>;
reg = <0x1120>;
};
dss_video2_clk: dss_video2_clk@1120 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&video2_dpll_clk_mux>;
ti,bit-shift = <13>;
reg = <0x1120>;
};
gpio2_dbclk: gpio2_dbclk@1760 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
ti,bit-shift = <8>;
reg = <0x1760>;
};
gpio3_dbclk: gpio3_dbclk@1768 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
ti,bit-shift = <8>;
reg = <0x1768>;
};
gpio4_dbclk: gpio4_dbclk@1770 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
ti,bit-shift = <8>;
reg = <0x1770>;
};
gpio5_dbclk: gpio5_dbclk@1778 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
ti,bit-shift = <8>;
reg = <0x1778>;
};
gpio6_dbclk: gpio6_dbclk@1780 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
ti,bit-shift = <8>;
reg = <0x1780>;
};
gpio7_dbclk: gpio7_dbclk@1810 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
ti,bit-shift = <8>;
reg = <0x1810>;
};
gpio8_dbclk: gpio8_dbclk@1818 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
ti,bit-shift = <8>;
reg = <0x1818>;
};
mmc1_clk32k: mmc1_clk32k@1328 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
ti,bit-shift = <8>;
reg = <0x1328>;
};
mmc2_clk32k: mmc2_clk32k@1330 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
ti,bit-shift = <8>;
reg = <0x1330>;
};
mmc3_clk32k: mmc3_clk32k@1820 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
ti,bit-shift = <8>;
reg = <0x1820>;
};
mmc4_clk32k: mmc4_clk32k@1828 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
ti,bit-shift = <8>;
reg = <0x1828>;
};
sata_ref_clk: sata_ref_clk@1388 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_clkin1>;
ti,bit-shift = <8>;
reg = <0x1388>;
};
usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m@13f0 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&l3init_960m_gfclk>;
ti,bit-shift = <8>;
reg = <0x13f0>;
};
usb_otg_ss2_refclk960m: usb_otg_ss2_refclk960m@1340 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&l3init_960m_gfclk>;
ti,bit-shift = <8>;
reg = <0x1340>;
};
usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k@640 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@ -1726,38 +1422,6 @@
reg = <0x0698>;
};
atl_dpll_clk_mux: atl_dpll_clk_mux@c00 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_32k_ck>, <&video1_clkin_ck>, <&video2_clkin_ck>, <&hdmi_clkin_ck>;
ti,bit-shift = <24>;
reg = <0x0c00>;
};
atl_gfclk_mux: atl_gfclk_mux@c00 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&l3_iclk_div>, <&dpll_abe_m2_ck>, <&atl_dpll_clk_mux>;
ti,bit-shift = <26>;
reg = <0x0c00>;
};
rmii_50mhz_clk_mux: rmii_50mhz_clk_mux@13d0 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&dpll_gmac_h11x2_ck>, <&rmii_clk_ck>;
ti,bit-shift = <24>;
reg = <0x13d0>;
};
gmac_rft_clk_mux: gmac_rft_clk_mux@13d0 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&video1_clkin_ck>, <&video2_clkin_ck>, <&dpll_abe_m2_ck>, <&hdmi_clkin_ck>, <&l3_iclk_div>;
ti,bit-shift = <25>;
reg = <0x13d0>;
};
gpu_core_gclk_mux: gpu_core_gclk_mux@1220 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
@ -1787,362 +1451,6 @@
ti,dividers = <8>, <16>, <32>;
};
mcasp2_ahclkr_mux: mcasp2_ahclkr_mux@1860 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
ti,bit-shift = <28>;
reg = <0x1860>;
};
mcasp2_ahclkx_mux: mcasp2_ahclkx_mux@1860 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
ti,bit-shift = <24>;
reg = <0x1860>;
};
mcasp2_aux_gfclk_mux: mcasp2_aux_gfclk_mux@1860 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
ti,bit-shift = <22>;
reg = <0x1860>;
};
mcasp3_ahclkx_mux: mcasp3_ahclkx_mux@1868 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
ti,bit-shift = <24>;
reg = <0x1868>;
assigned-clocks = <&mcasp3_ahclkx_mux>;
assigned-clock-parents = <&abe_24m_fclk>;
};
mcasp3_aux_gfclk_mux: mcasp3_aux_gfclk_mux@1868 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
ti,bit-shift = <22>;
reg = <0x1868>;
};
mcasp4_ahclkx_mux: mcasp4_ahclkx_mux@1898 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
ti,bit-shift = <24>;
reg = <0x1898>;
};
mcasp4_aux_gfclk_mux: mcasp4_aux_gfclk_mux@1898 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
ti,bit-shift = <22>;
reg = <0x1898>;
};
mcasp5_ahclkx_mux: mcasp5_ahclkx_mux@1878 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
ti,bit-shift = <24>;
reg = <0x1878>;
};
mcasp5_aux_gfclk_mux: mcasp5_aux_gfclk_mux@1878 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
ti,bit-shift = <22>;
reg = <0x1878>;
};
mcasp6_ahclkx_mux: mcasp6_ahclkx_mux@1904 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
ti,bit-shift = <24>;
reg = <0x1904>;
};
mcasp6_aux_gfclk_mux: mcasp6_aux_gfclk_mux@1904 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
ti,bit-shift = <22>;
reg = <0x1904>;
};
mcasp7_ahclkx_mux: mcasp7_ahclkx_mux@1908 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
ti,bit-shift = <24>;
reg = <0x1908>;
};
mcasp7_aux_gfclk_mux: mcasp7_aux_gfclk_mux@1908 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
ti,bit-shift = <22>;
reg = <0x1908>;
};
mcasp8_ahclkx_mux: mcasp8_ahclkx_mux@1890 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
ti,bit-shift = <22>;
reg = <0x1890>;
};
mcasp8_aux_gfclk_mux: mcasp8_aux_gfclk_mux@1890 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
ti,bit-shift = <24>;
reg = <0x1890>;
};
mmc1_fclk_mux: mmc1_fclk_mux@1328 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
ti,bit-shift = <24>;
reg = <0x1328>;
};
mmc1_fclk_div: mmc1_fclk_div@1328 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&mmc1_fclk_mux>;
ti,bit-shift = <25>;
ti,max-div = <4>;
reg = <0x1328>;
ti,index-power-of-two;
};
mmc2_fclk_mux: mmc2_fclk_mux@1330 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
ti,bit-shift = <24>;
reg = <0x1330>;
};
mmc2_fclk_div: mmc2_fclk_div@1330 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&mmc2_fclk_mux>;
ti,bit-shift = <25>;
ti,max-div = <4>;
reg = <0x1330>;
ti,index-power-of-two;
};
mmc3_gfclk_mux: mmc3_gfclk_mux@1820 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
ti,bit-shift = <24>;
reg = <0x1820>;
};
mmc3_gfclk_div: mmc3_gfclk_div@1820 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&mmc3_gfclk_mux>;
ti,bit-shift = <25>;
ti,max-div = <4>;
reg = <0x1820>;
ti,index-power-of-two;
};
mmc4_gfclk_mux: mmc4_gfclk_mux@1828 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
ti,bit-shift = <24>;
reg = <0x1828>;
};
mmc4_gfclk_div: mmc4_gfclk_div@1828 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&mmc4_gfclk_mux>;
ti,bit-shift = <25>;
ti,max-div = <4>;
reg = <0x1828>;
ti,index-power-of-two;
};
qspi_gfclk_mux: qspi_gfclk_mux@1838 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_128m_clk>, <&dpll_per_h13x2_ck>;
ti,bit-shift = <24>;
reg = <0x1838>;
};
qspi_gfclk_div: qspi_gfclk_div@1838 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&qspi_gfclk_mux>;
ti,bit-shift = <25>;
ti,max-div = <4>;
reg = <0x1838>;
ti,index-power-of-two;
};
timer10_gfclk_mux: timer10_gfclk_mux@1728 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
ti,bit-shift = <24>;
reg = <0x1728>;
};
timer11_gfclk_mux: timer11_gfclk_mux@1730 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
ti,bit-shift = <24>;
reg = <0x1730>;
};
timer13_gfclk_mux: timer13_gfclk_mux@17c8 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
ti,bit-shift = <24>;
reg = <0x17c8>;
};
timer14_gfclk_mux: timer14_gfclk_mux@17d0 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
ti,bit-shift = <24>;
reg = <0x17d0>;
};
timer15_gfclk_mux: timer15_gfclk_mux@17d8 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
ti,bit-shift = <24>;
reg = <0x17d8>;
};
timer16_gfclk_mux: timer16_gfclk_mux@1830 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
ti,bit-shift = <24>;
reg = <0x1830>;
};
timer2_gfclk_mux: timer2_gfclk_mux@1738 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
ti,bit-shift = <24>;
reg = <0x1738>;
};
timer3_gfclk_mux: timer3_gfclk_mux@1740 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
ti,bit-shift = <24>;
reg = <0x1740>;
};
timer4_gfclk_mux: timer4_gfclk_mux@1748 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
ti,bit-shift = <24>;
reg = <0x1748>;
};
timer9_gfclk_mux: timer9_gfclk_mux@1750 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
ti,bit-shift = <24>;
reg = <0x1750>;
};
uart1_gfclk_mux: uart1_gfclk_mux@1840 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
ti,bit-shift = <24>;
reg = <0x1840>;
};
uart2_gfclk_mux: uart2_gfclk_mux@1848 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
ti,bit-shift = <24>;
reg = <0x1848>;
};
uart3_gfclk_mux: uart3_gfclk_mux@1850 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
ti,bit-shift = <24>;
reg = <0x1850>;
};
uart4_gfclk_mux: uart4_gfclk_mux@1858 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
ti,bit-shift = <24>;
reg = <0x1858>;
};
uart5_gfclk_mux: uart5_gfclk_mux@1870 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
ti,bit-shift = <24>;
reg = <0x1870>;
};
uart7_gfclk_mux: uart7_gfclk_mux@18d0 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
ti,bit-shift = <24>;
reg = <0x18d0>;
};
uart8_gfclk_mux: uart8_gfclk_mux@18e0 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
ti,bit-shift = <24>;
reg = <0x18e0>;
};
uart9_gfclk_mux: uart9_gfclk_mux@18e8 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
ti,bit-shift = <24>;
reg = <0x18e8>;
};
vip1_gclk_mux: vip1_gclk_mux@1020 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
@ -2216,3 +1524,210 @@
reg = <0x6c4>;
};
};
&cm_core_aon {
mpu_cm: mpu_cm@300 {
compatible = "ti,omap4-cm";
reg = <0x300 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x300 0x100>;
mpu_clkctrl: clk@20 {
compatible = "ti,clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
};
ipu_cm: ipu_cm@500 {
compatible = "ti,omap4-cm";
reg = <0x500 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x500 0x100>;
ipu_clkctrl: clk@40 {
compatible = "ti,clkctrl";
reg = <0x40 0x44>;
#clock-cells = <2>;
};
};
rtc_cm: rtc_cm@700 {
compatible = "ti,omap4-cm";
reg = <0x700 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x700 0x100>;
rtc_clkctrl: clk@40 {
compatible = "ti,clkctrl";
reg = <0x40 0x8>;
#clock-cells = <2>;
};
};
};
&cm_core {
coreaon_cm: coreaon_cm@600 {
compatible = "ti,omap4-cm";
reg = <0x600 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x600 0x100>;
coreaon_clkctrl: clk@20 {
compatible = "ti,clkctrl";
reg = <0x20 0x1c>;
#clock-cells = <2>;
};
};
l3main1_cm: l3main1_cm@700 {
compatible = "ti,omap4-cm";
reg = <0x700 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x700 0x100>;
l3main1_clkctrl: clk@20 {
compatible = "ti,clkctrl";
reg = <0x20 0x74>;
#clock-cells = <2>;
};
};
dma_cm: dma_cm@a00 {
compatible = "ti,omap4-cm";
reg = <0xa00 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xa00 0x100>;
dma_clkctrl: clk@20 {
compatible = "ti,clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
};
emif_cm: emif_cm@b00 {
compatible = "ti,omap4-cm";
reg = <0xb00 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xb00 0x100>;
emif_clkctrl: clk@20 {
compatible = "ti,clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
};
atl_cm: atl_cm@c00 {
compatible = "ti,omap4-cm";
reg = <0xc00 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xc00 0x100>;
atl_clkctrl: clk@0 {
compatible = "ti,clkctrl";
reg = <0x0 0x4>;
#clock-cells = <2>;
};
};
l4cfg_cm: l4cfg_cm@d00 {
compatible = "ti,omap4-cm";
reg = <0xd00 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xd00 0x100>;
l4cfg_clkctrl: clk@20 {
compatible = "ti,clkctrl";
reg = <0x20 0x84>;
#clock-cells = <2>;
};
};
l3instr_cm: l3instr_cm@e00 {
compatible = "ti,omap4-cm";
reg = <0xe00 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xe00 0x100>;
l3instr_clkctrl: clk@20 {
compatible = "ti,clkctrl";
reg = <0x20 0xc>;
#clock-cells = <2>;
};
};
dss_cm: dss_cm@1100 {
compatible = "ti,omap4-cm";
reg = <0x1100 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x1100 0x100>;
dss_clkctrl: clk@20 {
compatible = "ti,clkctrl";
reg = <0x20 0x14>;
#clock-cells = <2>;
};
};
l3init_cm: l3init_cm@1300 {
compatible = "ti,omap4-cm";
reg = <0x1300 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x1300 0x100>;
l3init_clkctrl: clk@20 {
compatible = "ti,clkctrl";
reg = <0x20 0xd4>;
#clock-cells = <2>;
};
};
l4per_cm: l4per_cm@1700 {
compatible = "ti,omap4-cm";
reg = <0x1700 0x300>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x1700 0x300>;
l4per_clkctrl: clk@0 {
compatible = "ti,clkctrl";
reg = <0x0 0x20c>;
#clock-cells = <2>;
assigned-clocks = <&l4per_clkctrl DRA7_MCASP3_CLKCTRL 24>;
assigned-clock-parents = <&abe_24m_fclk>;
};
};
};
&prm {
wkupaon_cm: wkupaon_cm@1800 {
compatible = "ti,omap4-cm";
reg = <0x1800 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x1800 0x100>;
wkupaon_clkctrl: clk@20 {
compatible = "ti,clkctrl";
reg = <0x20 0x6c>;
#clock-cells = <2>;
};
};
};

2
sys/gnu/dts/arm/efm32gg-dk3750.dts
View File

@ -37,7 +37,7 @@
};
eeprom@50 {
compatible = "microchip,24c02";
compatible = "microchip,24c02", "atmel,24c02";
reg = <0x50>;
pagesize = <16>;
};

12
sys/gnu/dts/arm/ethernut5.dts
View File

@ -36,6 +36,18 @@
status = "okay";
};
tcb0: timer@fffa0000 {
timer@0 {
compatible = "atmel,tcb-timer";
reg = <0>, <1>;
};
timer@2 {
compatible = "atmel,tcb-timer";
reg = <2>;
};
};
usart0: serial@fffb0000 {
status = "okay";
};

5
sys/gnu/dts/arm/exynos3250-artik5-eval.dts
View File

@ -1,3 +1,4 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Samsung's Exynos3250 based ARTIK5 evaluation board device tree source
*
@ -6,10 +7,6 @@
*
* Device tree source file for Samsung's ARTIK5 evaluation board
* which is based on Samsung Exynos3250 SoC.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;

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