Import device-tree files from Linux 6.3
Sponsored by: Beckhoff Automation GmbH & Co. KG
This commit is contained in:
Emmanuel Vadot
commit
cb7aa33ac6
@ -28,7 +28,7 @@ $(obj)/%.example.dts: $(src)/%.yaml check_dtschema_version FORCE
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find_all_cmd = find $(srctree)/$(src) \( -name '*.yaml' ! \
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-name 'processed-schema*' \)
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find_cmd = $(find_all_cmd) | grep -F "$(DT_SCHEMA_FILES)"
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find_cmd = $(find_all_cmd) | grep -F -e "$(subst :," -e ",$(DT_SCHEMA_FILES))"
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CHK_DT_DOCS := $(shell $(find_cmd))
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quiet_cmd_yamllint = LINT $(src)
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@ -31,6 +31,7 @@ properties:
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- description: Mercury+ AA1 boards
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items:
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- enum:
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- enclustra,mercury-pe1
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- google,chameleon-v3
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- const: enclustra,mercury-aa1
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- const: altr,socfpga-arria10
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@ -154,6 +154,7 @@ properties:
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items:
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- enum:
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- khadas,vim3
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- radxa,zero2
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- const: amlogic,a311d
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- const: amlogic,g12b
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@ -165,6 +166,7 @@ properties:
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- azw,gtking-pro
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- hardkernel,odroid-go-ultra
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- hardkernel,odroid-n2
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- hardkernel,odroid-n2l
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- hardkernel,odroid-n2-plus
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- khadas,vim3
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- ugoos,am6
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@ -176,6 +178,7 @@ properties:
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- enum:
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- amediatech,x96-air
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- amediatech,x96-air-gbit
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- bananapi,bpi-m2-pro
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- bananapi,bpi-m5
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- cyx,a95xf3-air
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- cyx,a95xf3-air-gbit
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@ -78,6 +78,7 @@ properties:
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- facebook,cloudripper-bmc
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- facebook,elbert-bmc
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- facebook,fuji-bmc
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- facebook,greatlakes-bmc
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- ibm,everest-bmc
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- ibm,rainier-bmc
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- ibm,tacoma-bmc
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@ -85,6 +86,7 @@ properties:
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- jabil,rbp-bmc
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- qcom,dc-scm-v1-bmc
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- quanta,s6q-bmc
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- ufispace,ncplite-bmc
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- const: aspeed,ast2600
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additionalProperties: true
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@ -91,9 +91,11 @@ properties:
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- const: atmel,sama5d2
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- const: atmel,sama5
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- description: SAM9X60-EK board
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- description: Microchip SAM9X60 Evaluation Boards
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items:
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- const: microchip,sam9x60ek
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- enum:
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- microchip,sam9x60ek
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- microchip,sam9x60-curiosity
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- const: microchip,sam9x60
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- const: atmel,at91sam9
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@ -141,6 +141,7 @@ properties:
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- arm,cortex-a78ae
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- arm,cortex-a510
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- arm,cortex-a710
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- arm,cortex-a715
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- arm,cortex-m0
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- arm,cortex-m0+
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- arm,cortex-m1
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@ -151,6 +152,7 @@ properties:
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- arm,cortex-r7
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- arm,cortex-x1
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- arm,cortex-x2
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- arm,cortex-x3
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- arm,neoverse-e1
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- arm,neoverse-n1
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- arm,neoverse-n2
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@ -257,7 +259,7 @@ properties:
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capacity-dmips-mhz:
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description:
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u32 value representing CPU capacity (see ./cpu-capacity.txt) in
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u32 value representing CPU capacity (see ../cpu/cpu-capacity.txt) in
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DMIPS/MHz, relative to highest capacity-dmips-mhz
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in the system.
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@ -88,12 +88,56 @@ properties:
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items:
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- enum:
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- armadeus,imx28-apf28 # APF28 SoM
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- armadeus,imx28-apf28dev # APF28 SoM on APF28Dev board
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- bluegiga,apx4devkit # Bluegiga APx4 SoM on dev board
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- crystalfontz,cfa10036 # Crystalfontz CFA-10036 SoM
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- eukrea,mbmx28lc
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- fsl,imx28-evk
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- i2se,duckbill
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- i2se,duckbill-2
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- karo,tx28 # Ka-Ro electronics TX28 module
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- lwn,imx28-xea
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- msr,m28cu3 # M28 SoM with custom base board
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- schulercontrol,imx28-sps1
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- technologic,imx28-ts4600
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- const: fsl,imx28
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- description: i.MX28 Aries M28 SoM Board
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items:
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- const: aries,m28
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- const: denx,m28
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- const: fsl,imx28
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- description: i.MX28 Aries M28EVK Board
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items:
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- const: aries,m28evk
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- const: denx,m28evk
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- const: fsl,imx28
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- description: i.MX28 Armadeus Systems APF28Dev Board
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items:
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- const: armadeus,imx28-apf28dev
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- const: armadeus,imx28-apf28
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- const: fsl,imx28
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- description: i.MX28 Crystalfontz CFA-10036 based Boards
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items:
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- enum:
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- crystalfontz,cfa10037
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- crystalfontz,cfa10049
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- crystalfontz,cfa10057
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- crystalfontz,cfa10058
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- const: crystalfontz,cfa10036
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- const: fsl,imx28
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- description: i.MX28 Crystalfontz CFA-10037 based Boards
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items:
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- enum:
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- crystalfontz,cfa10055
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- crystalfontz,cfa10056
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- const: crystalfontz,cfa10037
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- const: crystalfontz,cfa10036
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- const: fsl,imx28
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- description: i.MX28 Duckbill 2 based Boards
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items:
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- enum:
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@ -103,6 +147,19 @@ properties:
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- const: i2se,duckbill-2
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- const: fsl,imx28
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- description: i.MX28 Eukrea Electromatique MBMX283LC Board
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items:
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- const: eukrea,mbmx283lc
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- const: eukrea,mbmx28lc
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- const: fsl,imx28
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- description: i.MX28 Eukrea Electromatique MBMX287LC Board
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items:
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- const: eukrea,mbmx287lc
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- const: eukrea,mbmx283lc
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- const: eukrea,mbmx28lc
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- const: fsl,imx28
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- description: i.MX31 based Boards
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items:
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- enum:
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@ -173,6 +230,7 @@ properties:
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- kiebackpeter,imx53-ddc # K+P imx53 DDC
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- kiebackpeter,imx53-hsc # K+P imx53 HSC
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- menlo,m53menlo # i.MX53 Menlo board
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- starterkit,sk-imx53
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- voipac,imx53-dmm-668 # Voipac i.MX53 X53-DMM-668
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- const: fsl,imx53
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@ -644,6 +702,16 @@ properties:
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- const: armadeus,imx6ull-opos6ul # OPOS6UL (i.MX6ULL) SoM
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- const: fsl,imx6ull
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- description: i.MX6ULL DHCOM SoM based Boards
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items:
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- enum:
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- dh,imx6ull-dhcom-drc02
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- dh,imx6ull-dhcom-pdk2
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- dh,imx6ull-dhcom-picoitx
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- const: dh,imx6ull-dhcom-som # The DHCOR is soldered on the DHCOM
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- const: dh,imx6ull-dhcor-som
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- const: fsl,imx6ull
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- description: i.MX6ULL PHYTEC phyBOARD-Segin
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items:
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- enum:
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@ -815,7 +883,6 @@ properties:
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- enum:
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- beacon,imx8mm-beacon-kit # i.MX8MM Beacon Development Kit
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- boundary,imx8mm-nitrogen8mm # i.MX8MM Nitrogen Board
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- cloos,imx8mm-phg # i.MX8MM Cloos PHG Board
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- dmo,imx8mm-data-modul-edm-sbc # i.MX8MM eDM SBC
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- emtrion,emcon-mx8mm-avari # emCON-MX8MM SoM on Avari Base
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- fsl,imx8mm-ddr4-evk # i.MX8MM DDR4 EVK Board
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@ -830,7 +897,6 @@ properties:
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- innocomm,wb15-evk # i.MX8MM Innocomm EVK board with WB15 SoM
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- kontron,imx8mm-sl # i.MX8MM Kontron SL (N801X) SOM
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- kontron,imx8mm-osm-s # i.MX8MM Kontron OSM-S (N802X) SOM
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- menlo,mx8menlo # i.MX8MM Menlo board with Verdin SoM
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- toradex,verdin-imx8mm # Verdin iMX8M Mini Modules
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- toradex,verdin-imx8mm-nonwifi # Verdin iMX8M Mini Modules without Wi-Fi / BT
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- toradex,verdin-imx8mm-wifi # Verdin iMX8M Mini Wi-Fi / BT Modules
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@ -861,8 +927,10 @@ properties:
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- description: Toradex Boards with Verdin iMX8M Mini Modules
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items:
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- enum:
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- menlo,mx8menlo # Verdin iMX8M Mini Module on i.MX8MM Menlo board
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- toradex,verdin-imx8mm-nonwifi-dahlia # Verdin iMX8M Mini Module on Dahlia
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- toradex,verdin-imx8mm-nonwifi-dev # Verdin iMX8M Mini Module on Verdin Development Board
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- toradex,verdin-imx8mm-nonwifi-yavia # Verdin iMX8M Mini Module on Yavia
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- const: toradex,verdin-imx8mm-nonwifi # Verdin iMX8M Mini Module without Wi-Fi / BT
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- const: toradex,verdin-imx8mm # Verdin iMX8M Mini Module
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- const: fsl,imx8mm
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@ -872,6 +940,7 @@ properties:
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- enum:
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- toradex,verdin-imx8mm-wifi-dahlia # Verdin iMX8M Mini Wi-Fi / BT Module on Dahlia
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- toradex,verdin-imx8mm-wifi-dev # Verdin iMX8M Mini Wi-Fi / BT M. on Verdin Development B.
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- toradex,verdin-imx8mm-wifi-yavia # Verdin iMX8M Mini Wi-Fi / BT Module on Yavia
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- const: toradex,verdin-imx8mm-wifi # Verdin iMX8M Mini Wi-Fi / BT Module
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- const: toradex,verdin-imx8mm # Verdin iMX8M Mini Module
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- const: fsl,imx8mm
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@ -895,6 +964,7 @@ properties:
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one compatible is needed.
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items:
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- enum:
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- cloos,imx8mm-phg # i.MX8MM Cloos PHG Board
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- tq,imx8mm-tqma8mqml-mba8mx # TQ-Systems GmbH i.MX8MM TQMa8MQML SOM on MBa8Mx
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- const: tq,imx8mm-tqma8mqml # TQ-Systems GmbH i.MX8MM TQMa8MQML SOM
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- const: fsl,imx8mm
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@ -931,10 +1001,11 @@ properties:
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- description: i.MX8MP based Boards
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items:
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- enum:
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- dh,imx8mp-dhcom-som # i.MX8MP DHCOM SoM
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- dh,imx8mp-dhcom-pdk2 # i.MX8MP DHCOM SoM on PDK2 board
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- beacon,imx8mp-beacon-kit # i.MX8MP Beacon Development Kit
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- fsl,imx8mp-evk # i.MX8MP EVK Board
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- gateworks,imx8mp-gw74xx # i.MX8MP Gateworks Board
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- polyhex,imx8mp-debix # Polyhex Debix boards
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- polyhex,imx8mp-debix-model-a # Polyhex Debix Model A Board
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- toradex,verdin-imx8mp # Verdin iMX8M Plus Modules
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- toradex,verdin-imx8mp-nonwifi # Verdin iMX8M Plus Modules without Wi-Fi / BT
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- toradex,verdin-imx8mp-wifi # Verdin iMX8M Plus Wi-Fi / BT Modules
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@ -947,6 +1018,12 @@ properties:
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- const: avnet,sm2s-imx8mp # SM2S-IMX8PLUS SoM
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- const: fsl,imx8mp
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- description: i.MX8MP DHCOM based Boards
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items:
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- const: dh,imx8mp-dhcom-pdk2 # i.MX8MP DHCOM SoM on PDK2 board
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- const: dh,imx8mp-dhcom-som # i.MX8MP DHCOM SoM
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- const: fsl,imx8mp
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- description: Engicam i.Core MX8M Plus SoM based boards
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items:
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- enum:
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@ -965,6 +1042,7 @@ properties:
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- enum:
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- toradex,verdin-imx8mp-nonwifi-dahlia # Verdin iMX8M Plus Module on Dahlia
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- toradex,verdin-imx8mp-nonwifi-dev # Verdin iMX8M Plus Module on Verdin Development Board
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- toradex,verdin-imx8mp-nonwifi-yavia # Verdin iMX8M Plus Module on Yavia
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- const: toradex,verdin-imx8mp-nonwifi # Verdin iMX8M Plus Module without Wi-Fi / BT
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- const: toradex,verdin-imx8mp # Verdin iMX8M Plus Module
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- const: fsl,imx8mp
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@ -974,6 +1052,7 @@ properties:
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- enum:
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- toradex,verdin-imx8mp-wifi-dahlia # Verdin iMX8M Plus Wi-Fi / BT Module on Dahlia
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- toradex,verdin-imx8mp-wifi-dev # Verdin iMX8M Plus Wi-Fi / BT M. on Verdin Development B.
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- toradex,verdin-imx8mp-wifi-yavia # Verdin iMX8M Plus Wi-Fi / BT Module on Yavia
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- const: toradex,verdin-imx8mp-wifi # Verdin iMX8M Plus Wi-Fi / BT Module
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- const: toradex,verdin-imx8mp # Verdin iMX8M Plus Module
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- const: fsl,imx8mp
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@ -999,12 +1078,17 @@ properties:
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- fsl,imx8mq-evk # i.MX8MQ EVK Board
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- google,imx8mq-phanbell # Google Coral Edge TPU
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- kontron,pitx-imx8m # Kontron pITX-imx8m Board
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- mntre,reform2 # MNT Reform2 Laptop
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- purism,librem5-devkit # Purism Librem5 devkit
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- solidrun,hummingboard-pulse # SolidRun Hummingboard Pulse
|
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- technexion,pico-pi-imx8m # TechNexion PICO-PI-8M evk
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- const: fsl,imx8mq
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- description: i.MX8MQ NITROGEN SoM based Boards
|
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items:
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- const: mntre,reform2 # MNT Reform2 Laptop
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- const: boundary,imx8mq-nitrogen8m-som # i.MX8MQ NITROGEN SoM
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- const: fsl,imx8mq
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- description: Purism Librem5 phones
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items:
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- enum:
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@ -244,6 +244,10 @@ properties:
|
||||
- enum:
|
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- mediatek,mt8183-pumpkin
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- const: mediatek,mt8183
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- items:
|
||||
- enum:
|
||||
- mediatek,mt8365-evk
|
||||
- const: mediatek,mt8365
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- items:
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||||
- enum:
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- mediatek,mt8516-pumpkin
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@ -10,6 +10,7 @@ Required Properties:
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- "mediatek,mt7622-ethsys", "syscon"
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- "mediatek,mt7623-ethsys", "mediatek,mt2701-ethsys", "syscon"
|
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- "mediatek,mt7629-ethsys", "syscon"
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- "mediatek,mt7981-ethsys", "syscon"
|
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- "mediatek,mt7986-ethsys", "syscon"
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- #clock-cells: Must be 1
|
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- #reset-cells: Must be 1
|
||||
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||||
@ -28,6 +28,7 @@ properties:
|
||||
- mediatek,mt6797-infracfg
|
||||
- mediatek,mt7622-infracfg
|
||||
- mediatek,mt7629-infracfg
|
||||
- mediatek,mt7981-infracfg
|
||||
- mediatek,mt7986-infracfg
|
||||
- mediatek,mt8135-infracfg
|
||||
- mediatek,mt8167-infracfg
|
||||
|
||||
@ -31,7 +31,11 @@ properties:
|
||||
- mediatek,mt8173-mmsys
|
||||
- mediatek,mt8183-mmsys
|
||||
- mediatek,mt8186-mmsys
|
||||
- mediatek,mt8188-vdosys0
|
||||
- mediatek,mt8192-mmsys
|
||||
- mediatek,mt8195-vdosys1
|
||||
- mediatek,mt8195-vppsys0
|
||||
- mediatek,mt8195-vppsys1
|
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- mediatek,mt8365-mmsys
|
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- const: syscon
|
||||
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||||
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||||
@ -28,11 +28,9 @@ properties:
|
||||
- mediatek,mt8195-imp_iic_wrap_s
|
||||
- mediatek,mt8195-imp_iic_wrap_w
|
||||
- mediatek,mt8195-mfgcfg
|
||||
- mediatek,mt8195-vppsys0
|
||||
- mediatek,mt8195-wpesys
|
||||
- mediatek,mt8195-wpesys_vpp0
|
||||
- mediatek,mt8195-wpesys_vpp1
|
||||
- mediatek,mt8195-vppsys1
|
||||
- mediatek,mt8195-imgsys
|
||||
- mediatek,mt8195-imgsys1_dip_top
|
||||
- mediatek,mt8195-imgsys1_dip_nr
|
||||
@ -92,13 +90,6 @@ examples:
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
- |
|
||||
vppsys0: clock-controller@14000000 {
|
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compatible = "mediatek,mt8195-vppsys0";
|
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reg = <0x14000000 0x1000>;
|
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#clock-cells = <1>;
|
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};
|
||||
|
||||
- |
|
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wpesys: clock-controller@14e00000 {
|
||||
compatible = "mediatek,mt8195-wpesys";
|
||||
@ -120,13 +111,6 @@ examples:
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
- |
|
||||
vppsys1: clock-controller@14f00000 {
|
||||
compatible = "mediatek,mt8195-vppsys1";
|
||||
reg = <0x14f00000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
- |
|
||||
imgsys: clock-controller@15000000 {
|
||||
compatible = "mediatek,mt8195-imgsys";
|
||||
|
||||
@ -8,6 +8,8 @@ Required Properties:
|
||||
- compatible: Should be:
|
||||
- "mediatek,mt7622-sgmiisys", "syscon"
|
||||
- "mediatek,mt7629-sgmiisys", "syscon"
|
||||
- "mediatek,mt7981-sgmiisys_0", "syscon"
|
||||
- "mediatek,mt7981-sgmiisys_1", "syscon"
|
||||
- "mediatek,mt7986-sgmiisys_0", "syscon"
|
||||
- "mediatek,mt7986-sgmiisys_1", "syscon"
|
||||
- #clock-cells: Must be 1
|
||||
|
||||
129
sys/contrib/device-tree/Bindings/arm/qcom,coresight-tpda.yaml
Normal file
129
sys/contrib/device-tree/Bindings/arm/qcom,coresight-tpda.yaml
Normal file
@ -0,0 +1,129 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
|
||||
# Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/qcom,coresight-tpda.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Trace, Profiling and Diagnostics Aggregator - TPDA
|
||||
|
||||
description: |
|
||||
TPDAs are responsible for packetization and timestamping of data sets
|
||||
utilizing the MIPI STPv2 packet protocol. Pulling data sets from one or
|
||||
more attached TPDM and pushing the resultant (packetized) data out a
|
||||
master ATB interface. Performing an arbitrated ATB interleaving (funneling)
|
||||
task for free-flowing data from TPDM (i.e. CMB and DSB data set flows).
|
||||
|
||||
There is no strict binding between TPDM and TPDA. TPDA can have multiple
|
||||
TPDMs connect to it. But There must be only one TPDA in the path from the
|
||||
TPDM source to TMC sink. TPDM can directly connect to TPDA's inport or
|
||||
connect to funnel which will connect to TPDA's inport.
|
||||
|
||||
We can use the commands are similar to the below to validate TPDMs.
|
||||
Enable coresight sink first.
|
||||
|
||||
echo 1 > /sys/bus/coresight/devices/tmc_etf0/enable_sink
|
||||
echo 1 > /sys/bus/coresight/devices/tpdm0/enable_source
|
||||
echo 1 > /sys/bus/coresight/devices/tpdm0/integration_test
|
||||
echo 2 > /sys/bus/coresight/devices/tpdm0/integration_test
|
||||
|
||||
The test data will be collected in the coresight sink which is enabled.
|
||||
If rwp register of the sink is keeping updating when do integration_test
|
||||
(by cat tmc_etf0/mgmt/rwp), it means there is data generated from TPDM
|
||||
to sink.
|
||||
|
||||
maintainers:
|
||||
- Mao Jinlong <quic_jinlmao@quicinc.com>
|
||||
- Tao Zhang <quic_taozha@quicinc.com>
|
||||
|
||||
# Need a custom select here or 'arm,primecell' will match on lots of nodes
|
||||
select:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,coresight-tpda
|
||||
required:
|
||||
- compatible
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
pattern: "^tpda(@[0-9a-f]+)$"
|
||||
compatible:
|
||||
items:
|
||||
- const: qcom,coresight-tpda
|
||||
- const: arm,primecell
|
||||
|
||||
reg:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: apb_pclk
|
||||
|
||||
in-ports:
|
||||
type: object
|
||||
description: |
|
||||
Input connections from TPDM to TPDA
|
||||
$ref: /schemas/graph.yaml#/properties/ports
|
||||
|
||||
out-ports:
|
||||
type: object
|
||||
description: |
|
||||
Output connections from the TPDA to legacy CoreSight trace bus.
|
||||
$ref: /schemas/graph.yaml#/properties/ports
|
||||
|
||||
properties:
|
||||
port:
|
||||
description:
|
||||
Output connection from the TPDA to legacy CoreSight Trace bus.
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- in-ports
|
||||
- out-ports
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
# minimum tpda definition.
|
||||
- |
|
||||
tpda@6004000 {
|
||||
compatible = "qcom,coresight-tpda", "arm,primecell";
|
||||
reg = <0x6004000 0x1000>;
|
||||
|
||||
clocks = <&aoss_qmp>;
|
||||
clock-names = "apb_pclk";
|
||||
|
||||
in-ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
tpda_qdss_0_in_tpdm_dcc: endpoint {
|
||||
remote-endpoint =
|
||||
<&tpdm_dcc_out_tpda_qdss_0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
out-ports {
|
||||
port {
|
||||
tpda_qdss_out_funnel_in0: endpoint {
|
||||
remote-endpoint =
|
||||
<&funnel_in0_in_tpda_qdss>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
...
|
||||
@ -0,0 +1,93 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
|
||||
# Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/qcom,coresight-tpdm.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Trace, Profiling and Diagnostics Monitor - TPDM
|
||||
|
||||
description: |
|
||||
The TPDM or Monitor serves as data collection component for various dataset
|
||||
types specified in the QPMDA spec. It covers Implementation defined ((ImplDef),
|
||||
Basic Counts (BC), Tenure Counts (TC), Continuous Multi-Bit (CMB), and Discrete
|
||||
Single Bit (DSB). It performs data collection in the data producing clock
|
||||
domain and transfers it to the data collection time domain, generally ATB
|
||||
clock domain.
|
||||
|
||||
The primary use case of the TPDM is to collect data from different data
|
||||
sources and send it to a TPDA for packetization, timestamping, and funneling.
|
||||
|
||||
maintainers:
|
||||
- Mao Jinlong <quic_jinlmao@quicinc.com>
|
||||
- Tao Zhang <quic_taozha@quicinc.com>
|
||||
|
||||
# Need a custom select here or 'arm,primecell' will match on lots of nodes
|
||||
select:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,coresight-tpdm
|
||||
required:
|
||||
- compatible
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
pattern: "^tpdm(@[0-9a-f]+)$"
|
||||
compatible:
|
||||
items:
|
||||
- const: qcom,coresight-tpdm
|
||||
- const: arm,primecell
|
||||
|
||||
reg:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: apb_pclk
|
||||
|
||||
out-ports:
|
||||
description: |
|
||||
Output connections from the TPDM to coresight funnel/TPDA.
|
||||
$ref: /schemas/graph.yaml#/properties/ports
|
||||
|
||||
properties:
|
||||
port:
|
||||
description: Output connection from the TPDM to coresight
|
||||
funnel/TPDA.
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
# minimum TPDM definition. TPDM connect to coresight TPDA.
|
||||
- |
|
||||
tpdm@684c000 {
|
||||
compatible = "qcom,coresight-tpdm", "arm,primecell";
|
||||
reg = <0x0684c000 0x1000>;
|
||||
|
||||
clocks = <&aoss_qmp>;
|
||||
clock-names = "apb_pclk";
|
||||
|
||||
out-ports {
|
||||
port {
|
||||
tpdm_prng_out_tpda_qdss: endpoint {
|
||||
remote-endpoint =
|
||||
<&tpda_qdss_in_tpdm_prng>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
...
|
||||
@ -35,6 +35,8 @@ description: |
|
||||
mdm9615
|
||||
msm8226
|
||||
msm8916
|
||||
msm8939
|
||||
msm8953
|
||||
msm8956
|
||||
msm8974
|
||||
msm8976
|
||||
@ -47,11 +49,13 @@ description: |
|
||||
qru1000
|
||||
sa8155p
|
||||
sa8540p
|
||||
sa8775p
|
||||
sc7180
|
||||
sc7280
|
||||
sc8180x
|
||||
sc8280xp
|
||||
sda660
|
||||
sdm450
|
||||
sdm630
|
||||
sdm632
|
||||
sdm636
|
||||
@ -62,6 +66,7 @@ description: |
|
||||
sdx65
|
||||
sm4250
|
||||
sm6115
|
||||
sm6115p
|
||||
sm6125
|
||||
sm6350
|
||||
sm6375
|
||||
@ -70,6 +75,7 @@ description: |
|
||||
sm8250
|
||||
sm8350
|
||||
sm8450
|
||||
sm8550
|
||||
|
||||
The 'board' element must be one of the following strings:
|
||||
|
||||
@ -84,6 +90,7 @@ description: |
|
||||
liquid
|
||||
mtp
|
||||
qrd
|
||||
ride
|
||||
sbc
|
||||
x100
|
||||
|
||||
@ -160,6 +167,12 @@ properties:
|
||||
- samsung,s3ve3g
|
||||
- const: qcom,msm8226
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- sony,kanuti-tulip
|
||||
- square,apq8039-t2
|
||||
- const: qcom,msm8939
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- sony,kugo-row
|
||||
@ -194,8 +207,10 @@ properties:
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- acer,a1-724
|
||||
- alcatel,idol347
|
||||
- asus,z00l
|
||||
- gplus,fl8005a
|
||||
- huawei,g7
|
||||
- longcheer,l8910
|
||||
- samsung,a3u-eur
|
||||
@ -203,8 +218,13 @@ properties:
|
||||
- samsung,e5
|
||||
- samsung,e7
|
||||
- samsung,grandmax
|
||||
- samsung,gt510
|
||||
- samsung,gt58
|
||||
- samsung,j5
|
||||
- samsung,j5x
|
||||
- samsung,serranove
|
||||
- thwc,uf896
|
||||
- thwc,ufi001c
|
||||
- wingtech,wt88047
|
||||
- const: qcom,msm8916
|
||||
|
||||
@ -213,6 +233,15 @@ properties:
|
||||
- const: qcom,msm8916-v1-qrd/9-v1
|
||||
- const: qcom,msm8916
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- motorola,potter
|
||||
- xiaomi,daisy
|
||||
- xiaomi,mido
|
||||
- xiaomi,tissot
|
||||
- xiaomi,vince
|
||||
- const: qcom,msm8953
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- lg,bullhead
|
||||
@ -627,6 +656,12 @@ properties:
|
||||
- const: google,hoglin
|
||||
- const: qcom,sc7280
|
||||
|
||||
- description: Qualcomm Technologies, Inc. sc7280 CRD Pro platform (newest rev)
|
||||
items:
|
||||
- const: google,zoglin-sku1536
|
||||
- const: google,hoglin-sku1536
|
||||
- const: qcom,sc7280
|
||||
|
||||
- description: Qualcomm Technologies, Inc. sc7280 IDP SKU1 platform
|
||||
items:
|
||||
- const: qcom,sc7280-idp
|
||||
@ -679,6 +714,18 @@ properties:
|
||||
- const: google,zombie-sku512
|
||||
- const: qcom,sc7280
|
||||
|
||||
- description: Google Zombie with NVMe (newest rev)
|
||||
items:
|
||||
- const: google,zombie-sku2
|
||||
- const: google,zombie-sku3
|
||||
- const: google,zombie-sku515
|
||||
- const: qcom,sc7280
|
||||
|
||||
- description: Google Zombie with LTE and NVMe (newest rev)
|
||||
items:
|
||||
- const: google,zombie-sku514
|
||||
- const: qcom,sc7280
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- lenovo,flex-5g
|
||||
@ -693,6 +740,11 @@ properties:
|
||||
- qcom,sc8280xp-qrd
|
||||
- const: qcom,sc8280xp
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- motorola,ali
|
||||
- const: qcom,sdm450
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- sony,discovery-row
|
||||
@ -709,6 +761,7 @@ properties:
|
||||
- items:
|
||||
- enum:
|
||||
- fairphone,fp3
|
||||
- motorola,ocean
|
||||
- const: qcom,sdm632
|
||||
|
||||
- items:
|
||||
@ -762,6 +815,11 @@ properties:
|
||||
- qcom,sa8540p-ride
|
||||
- const: qcom,sa8540p
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,sa8775p-ride
|
||||
- const: qcom,sa8775p
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- google,cheza
|
||||
@ -790,6 +848,12 @@ properties:
|
||||
- oneplus,billie2
|
||||
- const: qcom,sm4250
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- lenovo,j606f
|
||||
- const: qcom,sm6115p
|
||||
- const: qcom,sm6115
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- sony,pdx201
|
||||
@ -826,6 +890,7 @@ properties:
|
||||
- qcom,sm8250-mtp
|
||||
- sony,pdx203-generic
|
||||
- sony,pdx206-generic
|
||||
- xiaomi,elish
|
||||
- const: qcom,sm8250
|
||||
|
||||
- items:
|
||||
@ -845,6 +910,11 @@ properties:
|
||||
- sony,pdx224
|
||||
- const: qcom,sm8450
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,sm8550-mtp
|
||||
- const: qcom,sm8550
|
||||
|
||||
# Board compatibles go above
|
||||
|
||||
qcom,msm-id:
|
||||
@ -922,15 +992,22 @@ allOf:
|
||||
- qcom,apq8026
|
||||
- qcom,apq8094
|
||||
- qcom,apq8096
|
||||
- qcom,msm8939
|
||||
- qcom,msm8953
|
||||
- qcom,msm8956
|
||||
- qcom,msm8992
|
||||
- qcom,msm8994
|
||||
- qcom,msm8996
|
||||
- qcom,msm8998
|
||||
- qcom,sdm450
|
||||
- qcom,sdm630
|
||||
- qcom,sdm632
|
||||
- qcom,sdm636
|
||||
- qcom,sdm845
|
||||
- qcom,sdx55
|
||||
- qcom,sdx65
|
||||
- qcom,sm4250
|
||||
- qcom,sm6115
|
||||
- qcom,sm6125
|
||||
- qcom,sm6350
|
||||
- qcom,sm7225
|
||||
@ -954,6 +1031,8 @@ allOf:
|
||||
- oneplus,dumpling
|
||||
- oneplus,enchilada
|
||||
- oneplus,fajita
|
||||
- oneplus,oneplus3
|
||||
- oneplus,oneplus3t
|
||||
then:
|
||||
properties:
|
||||
qcom,board-id:
|
||||
|
||||
@ -90,11 +90,33 @@ properties:
|
||||
- const: chipspark,rayeager-px2
|
||||
- const: rockchip,rk3066a
|
||||
|
||||
- description: Edgeble Neural Compute Module 2(Neu2) SoM based boards
|
||||
items:
|
||||
- const: edgeble,neural-compute-module-2-io # Edgeble Neural Compute Module 2 IO Board
|
||||
- const: edgeble,neural-compute-module-2 # Edgeble Neural Compute Module 2 SoM
|
||||
- const: rockchip,rv1126
|
||||
|
||||
- description: Edgeble Neural Compute Module 6(Neu6) Model A SoM based boards
|
||||
items:
|
||||
- const: edgeble,neural-compute-module-6a-io # Edgeble Neural Compute Module 6A IO Board
|
||||
- const: edgeble,neural-compute-module-6a # Edgeble Neural Compute Module 6A SoM
|
||||
- const: rockchip,rk3588
|
||||
|
||||
- description: Elgin RV1108 R1
|
||||
items:
|
||||
- const: elgin,rv1108-r1
|
||||
- const: rockchip,rv1108
|
||||
|
||||
- description: EmbedFire LubanCat 1
|
||||
items:
|
||||
- const: embedfire,lubancat-1
|
||||
- const: rockchip,rk3566
|
||||
|
||||
- description: EmbedFire LubanCat 2
|
||||
items:
|
||||
- const: embedfire,lubancat-2
|
||||
- const: rockchip,rk3568
|
||||
|
||||
- description: Engicam PX30.Core C.TOUCH 2.0
|
||||
items:
|
||||
- const: engicam,px30-core-ctouch2
|
||||
@ -599,6 +621,20 @@ properties:
|
||||
- const: pine64,soquartz
|
||||
- const: rockchip,rk3566
|
||||
|
||||
- description: Radxa Compute Module 3(CM3)
|
||||
items:
|
||||
- enum:
|
||||
- radxa,cm3-io
|
||||
- const: radxa,cm3
|
||||
- const: rockchip,rk3566
|
||||
|
||||
- description: Radxa CM3 Industrial
|
||||
items:
|
||||
- enum:
|
||||
- radxa,e25
|
||||
- const: radxa,cm3i
|
||||
- const: rockchip,rk3568
|
||||
|
||||
- description: Radxa Rock
|
||||
items:
|
||||
- const: radxa,rock
|
||||
@ -652,6 +688,16 @@ properties:
|
||||
- const: radxa,rock3a
|
||||
- const: rockchip,rk3568
|
||||
|
||||
- description: Radxa ROCK 5 Model A
|
||||
items:
|
||||
- const: radxa,rock-5a
|
||||
- const: rockchip,rk3588s
|
||||
|
||||
- description: Radxa ROCK 5 Model B
|
||||
items:
|
||||
- const: radxa,rock-5b
|
||||
- const: rockchip,rk3588
|
||||
|
||||
- description: Rikomagic MK808 v1
|
||||
items:
|
||||
- const: rikomagic,mk808
|
||||
@ -689,6 +735,11 @@ properties:
|
||||
- const: rockchip,rk3036-evb
|
||||
- const: rockchip,rk3036
|
||||
|
||||
- description: Rockchip RK3128 Evaluation board
|
||||
items:
|
||||
- const: rockchip,rk3128-evb
|
||||
- const: rockchip,rk3128
|
||||
|
||||
- description: Rockchip RK3228 Evaluation board
|
||||
items:
|
||||
- const: rockchip,rk3228-evb
|
||||
@ -736,6 +787,11 @@ properties:
|
||||
- const: rockchip,rk3399-sapphire-excavator
|
||||
- const: rockchip,rk3399
|
||||
|
||||
- description: Rockchip RK3588 Evaluation board
|
||||
items:
|
||||
- const: rockchip,rk3588-evb1-v10
|
||||
- const: rockchip,rk3588
|
||||
|
||||
- description: Rockchip RV1108 Evaluation board
|
||||
items:
|
||||
- const: rockchip,rv1108-evb
|
||||
@ -761,6 +817,11 @@ properties:
|
||||
- const: tronsmart,orion-r68-meta
|
||||
- const: rockchip,rk3368
|
||||
|
||||
- description: Xunlong Orange Pi R1 Plus
|
||||
items:
|
||||
- const: xunlong,orangepi-r1-plus
|
||||
- const: rockchip,rk3328
|
||||
|
||||
- description: Zkmagic A95X Z2
|
||||
items:
|
||||
- const: zkmagic,a95x-z2
|
||||
|
||||
@ -27,6 +27,7 @@ select:
|
||||
- rockchip,rk3399-pmu
|
||||
- rockchip,rk3568-pmu
|
||||
- rockchip,rk3588-pmu
|
||||
- rockchip,rv1126-pmu
|
||||
|
||||
required:
|
||||
- compatible
|
||||
@ -43,6 +44,7 @@ properties:
|
||||
- rockchip,rk3399-pmu
|
||||
- rockchip,rk3568-pmu
|
||||
- rockchip,rk3588-pmu
|
||||
- rockchip,rv1126-pmu
|
||||
- const: syscon
|
||||
- const: simple-mfd
|
||||
|
||||
|
||||
@ -171,6 +171,7 @@ properties:
|
||||
- hardkernel,odroid-xu3-lite # Hardkernel Odroid XU3 Lite
|
||||
- hardkernel,odroid-xu4 # Hardkernel Odroid XU4
|
||||
- hardkernel,odroid-hc1 # Hardkernel Odroid HC1
|
||||
- samsung,k3g # Samsung Galaxy S5 (SM-G900H)
|
||||
- const: samsung,exynos5800
|
||||
- const: samsung,exynos5
|
||||
|
||||
|
||||
@ -38,10 +38,17 @@ properties:
|
||||
- ti,am642-sk
|
||||
- const: ti,am642
|
||||
|
||||
- description: K3 AM642 SoC PHYTEC phyBOARD-Electra
|
||||
items:
|
||||
- const: phytec,am642-phyboard-electra-rdk
|
||||
- const: phytec,am64-phycore-som
|
||||
- const: ti,am642
|
||||
|
||||
- description: K3 AM654 SoC
|
||||
items:
|
||||
- enum:
|
||||
- siemens,iot2050-advanced
|
||||
- siemens,iot2050-advanced-m2
|
||||
- siemens,iot2050-advanced-pg2
|
||||
- siemens,iot2050-basic
|
||||
- siemens,iot2050-basic-pg2
|
||||
@ -69,9 +76,17 @@ properties:
|
||||
- description: K3 J721s2 SoC
|
||||
items:
|
||||
- enum:
|
||||
- ti,am68-sk
|
||||
- ti,j721s2-evm
|
||||
- const: ti,j721s2
|
||||
|
||||
- description: K3 J784s4 SoC
|
||||
items:
|
||||
- enum:
|
||||
- ti,am69-sk
|
||||
- ti,j784s4-evm
|
||||
- const: ti,j784s4
|
||||
|
||||
additionalProperties: true
|
||||
|
||||
...
|
||||
|
||||
@ -35,6 +35,7 @@ required:
|
||||
|
||||
allOf:
|
||||
- $ref: pata-common.yaml#
|
||||
- $ref: /schemas/memory-controllers/intel,ixp4xx-expansion-peripheral-props.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
|
||||
@ -0,0 +1,37 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/bus/aspeed,ast2600-ahbc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: ASPEED Advanced High-Performance Bus Controller (AHBC)
|
||||
|
||||
maintainers:
|
||||
- Neal Liu <neal_liu@aspeedtech.com>
|
||||
- Chia-Wei Wang <chiawei_wang@aspeedtech.com>
|
||||
|
||||
description: |
|
||||
Advanced High-performance Bus Controller (AHBC) supports plenty of mechanisms
|
||||
including a priority arbiter, an address decoder and a data multiplexer
|
||||
to control the overall operations of Advanced High-performance Bus (AHB).
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- aspeed,ast2600-ahbc
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
ahbc@1e600000 {
|
||||
compatible = "aspeed,ast2600-ahbc";
|
||||
reg = <0x1e600000 0x100>;
|
||||
};
|
||||
@ -40,10 +40,10 @@ properties:
|
||||
maxItems: 1
|
||||
|
||||
"#address-cells":
|
||||
const: 1
|
||||
enum: [ 1, 2 ]
|
||||
|
||||
"#size-cells":
|
||||
const: 1
|
||||
enum: [ 1, 2 ]
|
||||
|
||||
ranges: true
|
||||
|
||||
|
||||
@ -54,6 +54,7 @@ properties:
|
||||
- idt,5p49v5925
|
||||
- idt,5p49v5933
|
||||
- idt,5p49v5935
|
||||
- idt,5p49v60
|
||||
- idt,5p49v6901
|
||||
- idt,5p49v6965
|
||||
- idt,5p49v6975
|
||||
|
||||
@ -108,7 +108,7 @@ examples:
|
||||
};
|
||||
|
||||
- |
|
||||
clock-controller@30390000 {
|
||||
clock-controller@30380000 {
|
||||
compatible = "fsl,imx8mq-ccm";
|
||||
reg = <0x30380000 0x10000>;
|
||||
#clock-cells = <1>;
|
||||
|
||||
@ -0,0 +1,63 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/loongson,ls2k-clk.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Loongson-2 SoC Clock Control Module
|
||||
|
||||
maintainers:
|
||||
- Yinbo Zhu <zhuyinbo@loongson.cn>
|
||||
|
||||
description: |
|
||||
Loongson-2 SoC clock control module is an integrated clock controller, which
|
||||
generates and supplies to all modules.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- loongson,ls2k-clk
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: 100m ref
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: ref_100m
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
description:
|
||||
The clock consumer should specify the desired clock by having the clock
|
||||
ID in its "clocks" phandle cell. See include/dt-bindings/clock/loongson,ls2k-clk.h
|
||||
for the full list of Loongson-2 SoC clock IDs.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#clock-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
ref_100m: clock-ref-100m {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <100000000>;
|
||||
clock-output-names = "ref_100m";
|
||||
};
|
||||
|
||||
clk: clock-controller@1fe00480 {
|
||||
compatible = "loongson,ls2k-clk";
|
||||
reg = <0x1fe00480 0x58>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&ref_100m>;
|
||||
clock-names = "ref_100m";
|
||||
};
|
||||
@ -20,6 +20,7 @@ properties:
|
||||
- enum:
|
||||
- mediatek,mt6797-apmixedsys
|
||||
- mediatek,mt7622-apmixedsys
|
||||
- mediatek,mt7981-apmixedsys
|
||||
- mediatek,mt7986-apmixedsys
|
||||
- mediatek,mt8135-apmixedsys
|
||||
- mediatek,mt8173-apmixedsys
|
||||
|
||||
@ -35,6 +35,7 @@ properties:
|
||||
- mediatek,mt6779-topckgen
|
||||
- mediatek,mt6795-topckgen
|
||||
- mediatek,mt7629-topckgen
|
||||
- mediatek,mt7981-topckgen
|
||||
- mediatek,mt7986-topckgen
|
||||
- mediatek,mt8167-topckgen
|
||||
- mediatek,mt8183-topckgen
|
||||
|
||||
@ -21,12 +21,16 @@ properties:
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: AHB
|
||||
- description: Board XO source
|
||||
- description: Board active XO source
|
||||
- description: Sleep clock source
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: iface
|
||||
- const: bi_tcxo
|
||||
- const: bi_tcxo_ao
|
||||
- const: sleep_clk
|
||||
|
||||
'#clock-cells':
|
||||
@ -38,9 +42,18 @@ properties:
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
power-domains:
|
||||
items:
|
||||
- description: MMCX power domain
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required-opps:
|
||||
maxItems: 1
|
||||
description:
|
||||
OPP node describing required MMCX performance point.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
@ -54,13 +67,16 @@ additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,gcc-sm8250.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
clock-controller@ad00000 {
|
||||
compatible = "qcom,sm8250-camcc";
|
||||
reg = <0x0ad00000 0x10000>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
||||
clocks = <&gcc GCC_CAMERA_AHB_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK_A>,
|
||||
<&sleep_clk>;
|
||||
clock-names = "bi_tcxo", "sleep_clk";
|
||||
clock-names = "iface", "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
|
||||
@ -25,6 +25,30 @@ properties:
|
||||
compatible:
|
||||
const: qcom,gcc-apq8084
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: XO source
|
||||
- description: Sleep clock source
|
||||
- description: UFS RX symbol 0 clock
|
||||
- description: UFS RX symbol 1 clock
|
||||
- description: UFS TX symbol 0 clock
|
||||
- description: UFS TX symbol 1 clock
|
||||
- description: SATA ASIC0 clock
|
||||
- description: SATA RX clock
|
||||
- description: PCIe PIPE clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: xo
|
||||
- const: sleep_clk
|
||||
- const: ufs_rx_symbol_0_clk_src
|
||||
- const: ufs_rx_symbol_1_clk_src
|
||||
- const: ufs_tx_symbol_0_clk_src
|
||||
- const: ufs_tx_symbol_1_clk_src
|
||||
- const: sata_asic0_clk
|
||||
- const: sata_rx_clk
|
||||
- const: pcie_pipe
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
@ -32,11 +56,31 @@ unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
/* UFS PHY on APQ8084 is not supported (yet), so these bindings just serve an example */
|
||||
clock-controller@fc400000 {
|
||||
compatible = "qcom,gcc-apq8084";
|
||||
reg = <0xfc400000 0x4000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
|
||||
clocks = <&xo_board>,
|
||||
<&sleep_clk>,
|
||||
<&ufsphy 0>,
|
||||
<&ufsphy 1>,
|
||||
<&ufsphy 2>,
|
||||
<&ufsphy 3>,
|
||||
<&sata 0>,
|
||||
<&sata 1>,
|
||||
<&pcie_phy>;
|
||||
clock-names = "xo",
|
||||
"sleep_clk",
|
||||
"ufs_rx_symbol_0_clk_src",
|
||||
"ufs_rx_symbol_1_clk_src",
|
||||
"ufs_tx_symbol_0_clk_src",
|
||||
"ufs_tx_symbol_1_clk_src",
|
||||
"sata_asic0_clk",
|
||||
"sata_rx_clk",
|
||||
"pcie_pipe";
|
||||
};
|
||||
...
|
||||
|
||||
@ -25,7 +25,6 @@ properties:
|
||||
- description: Board XO source
|
||||
- description: Sleep clock source
|
||||
- description: Audio reference clock (Optional clock)
|
||||
- description: PLL test clock source (Optional clock)
|
||||
minItems: 2
|
||||
|
||||
clock-names:
|
||||
@ -33,7 +32,6 @@ properties:
|
||||
- const: xo
|
||||
- const: sleep_clk
|
||||
- const: aud_ref_clk # Optional clock
|
||||
- const: core_bi_pll_test_se # Optional clock
|
||||
minItems: 2
|
||||
|
||||
required:
|
||||
@ -57,11 +55,9 @@ examples:
|
||||
reg = <0x00100000 0xb0000>;
|
||||
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
|
||||
<&sleep>,
|
||||
<0>,
|
||||
<0>;
|
||||
clock-names = "xo",
|
||||
"sleep_clk",
|
||||
"aud_ref_clk",
|
||||
"core_bi_pll_test_se";
|
||||
"aud_ref_clk";
|
||||
};
|
||||
...
|
||||
|
||||
@ -20,26 +20,31 @@ properties:
|
||||
compatible:
|
||||
const: qcom,gcc-qcs404
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
clocks:
|
||||
items:
|
||||
- description: XO source
|
||||
- description: Sleep clock source
|
||||
- description: PCIe 0 PIPE clock (optional)
|
||||
- description: DSI phy instance 0 dsi clock
|
||||
- description: DSI phy instance 0 byte clock
|
||||
- description: HDMI phy PLL clock
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
protected-clocks:
|
||||
description:
|
||||
Protected clock specifier list as per common clock binding.
|
||||
clock-names:
|
||||
items:
|
||||
- const: cxo
|
||||
- const: sleep_clk
|
||||
- const: pcie_0_pipe_clk_src
|
||||
- const: dsi0pll
|
||||
- const: dsi0pllbyte
|
||||
- const: hdmi_pll
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
|
||||
additionalProperties: false
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
@ -48,5 +53,6 @@ examples:
|
||||
reg = <0x01800000 0x80000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
...
|
||||
|
||||
@ -55,6 +55,10 @@ properties:
|
||||
- description: First EMAC controller reference clock
|
||||
- description: Second EMAC controller reference clock
|
||||
|
||||
power-domains:
|
||||
items:
|
||||
- description: CX domain
|
||||
|
||||
protected-clocks:
|
||||
maxItems: 389
|
||||
|
||||
@ -70,6 +74,8 @@ unevaluatedProperties: false
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/power/qcom-rpmpd.h>
|
||||
|
||||
clock-controller@100000 {
|
||||
compatible = "qcom,gcc-sc8280xp";
|
||||
reg = <0x00100000 0x1f0000>;
|
||||
@ -106,6 +112,7 @@ examples:
|
||||
<&pcie4_lane>,
|
||||
<&rxc0_ref_clk>,
|
||||
<&rxc1_ref_clk>;
|
||||
power-domains = <&rpmhpd SC8280XP_CX>;
|
||||
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
|
||||
@ -24,15 +24,11 @@ properties:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: Sleep clock source
|
||||
- description: PLL test clock source (Optional clock)
|
||||
minItems: 2
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: bi_tcxo
|
||||
- const: sleep_clk
|
||||
- const: core_bi_pll_test_se # Optional clock
|
||||
minItems: 2
|
||||
|
||||
required:
|
||||
- compatible
|
||||
@ -51,8 +47,9 @@ examples:
|
||||
compatible = "qcom,gcc-sdx55";
|
||||
reg = <0x00100000 0x1f0000>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
||||
<&sleep_clk>, <&pll_test_clk>;
|
||||
clock-names = "bi_tcxo", "sleep_clk", "core_bi_pll_test_se";
|
||||
<&sleep_clk>;
|
||||
clock-names = "bi_tcxo",
|
||||
"sleep_clk";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
|
||||
@ -26,8 +26,6 @@ properties:
|
||||
- description: Sleep clock source
|
||||
- description: PCIE Pipe clock source
|
||||
- description: USB3 phy wrapper pipe clock source
|
||||
- description: PLL test clock source (Optional clock)
|
||||
minItems: 5
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
@ -36,8 +34,6 @@ properties:
|
||||
- const: sleep_clk
|
||||
- const: pcie_pipe_clk
|
||||
- const: usb3_phy_wrapper_gcc_usb30_pipe_clk
|
||||
- const: core_bi_pll_test_se # Optional clock
|
||||
minItems: 5
|
||||
|
||||
required:
|
||||
- compatible
|
||||
@ -56,9 +52,9 @@ examples:
|
||||
compatible = "qcom,gcc-sdx65";
|
||||
reg = <0x100000 0x1f7400>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>,
|
||||
<&pcie_pipe_clk>, <&usb3_phy_wrapper_gcc_usb30_pipe_clk>, <&pll_test_clk>;
|
||||
<&pcie_pipe_clk>, <&usb3_phy_wrapper_gcc_usb30_pipe_clk>;
|
||||
clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk",
|
||||
"pcie_pipe_clk", "usb3_phy_wrapper_gcc_usb30_pipe_clk", "core_bi_pll_test_se";
|
||||
"pcie_pipe_clk", "usb3_phy_wrapper_gcc_usb30_pipe_clk";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
|
||||
@ -23,7 +23,6 @@ properties:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: Sleep clock source
|
||||
- description: PLL test clock source (Optional clock)
|
||||
- description: PCIE 0 Pipe clock source (Optional clock)
|
||||
- description: PCIE 1 Pipe clock source (Optional clock)
|
||||
- description: UFS card Rx symbol 0 clock source (Optional clock)
|
||||
@ -40,7 +39,6 @@ properties:
|
||||
items:
|
||||
- const: bi_tcxo
|
||||
- const: sleep_clk
|
||||
- const: core_bi_pll_test_se # Optional clock
|
||||
- const: pcie_0_pipe_clk # Optional clock
|
||||
- const: pcie_1_pipe_clk # Optional clock
|
||||
- const: ufs_card_rx_symbol_0_clk # Optional clock
|
||||
|
||||
@ -21,6 +21,7 @@ description: |
|
||||
include/dt-bindings/clock/qcom,gpucc-sm6350.h
|
||||
include/dt-bindings/clock/qcom,gpucc-sm8150.h
|
||||
include/dt-bindings/clock/qcom,gpucc-sm8250.h
|
||||
include/dt-bindings/clock/qcom,gpucc-sm8350.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
@ -33,6 +34,7 @@ properties:
|
||||
- qcom,sm6350-gpucc
|
||||
- qcom,sm8150-gpucc
|
||||
- qcom,sm8250-gpucc
|
||||
- qcom,sm8350-gpucc
|
||||
|
||||
clocks:
|
||||
items:
|
||||
|
||||
@ -32,11 +32,11 @@ properties:
|
||||
|
||||
clocks:
|
||||
minItems: 8
|
||||
maxItems: 10
|
||||
maxItems: 13
|
||||
|
||||
clock-names:
|
||||
minItems: 8
|
||||
maxItems: 10
|
||||
maxItems: 13
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
@ -137,6 +137,46 @@ allOf:
|
||||
- const: edp_link_clk
|
||||
- const: edp_vco_div
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,mmcc-apq8084
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: Board sleep source
|
||||
- description: MMSS GPLL0 voted clock
|
||||
- description: GPLL0 clock
|
||||
- description: GPLL0 voted clock
|
||||
- description: GPLL1 clock
|
||||
- description: DSI phy instance 0 dsi clock
|
||||
- description: DSI phy instance 0 byte clock
|
||||
- description: DSI phy instance 1 dsi clock
|
||||
- description: DSI phy instance 1 byte clock
|
||||
- description: HDMI phy PLL clock
|
||||
- description: eDP phy PLL link clock
|
||||
- description: eDP phy PLL vco clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: xo
|
||||
- const: sleep_clk
|
||||
- const: mmss_gpll0_vote
|
||||
- const: gpll0
|
||||
- const: gpll0_vote
|
||||
- const: gpll1
|
||||
- const: dsi0pll
|
||||
- const: dsi0pllbyte
|
||||
- const: dsi1pll
|
||||
- const: dsi1pllbyte
|
||||
- const: hdmipll
|
||||
- const: edp_link_clk
|
||||
- const: edp_vco_div
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
@ -229,7 +269,6 @@ allOf:
|
||||
- description: HDMI phy PLL clock
|
||||
- description: DisplayPort phy PLL link clock
|
||||
- description: DisplayPort phy PLL vco clock
|
||||
- description: Test clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
@ -242,7 +281,6 @@ allOf:
|
||||
- const: hdmipll
|
||||
- const: dplink
|
||||
- const: dpvco
|
||||
- const: core_bi_pll_test_se
|
||||
|
||||
- if:
|
||||
properties:
|
||||
|
||||
@ -27,10 +27,12 @@ properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: XO source
|
||||
- description: SYS APCS AUX clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: xo
|
||||
- const: sys_apcs_aux
|
||||
|
||||
required:
|
||||
- compatible
|
||||
@ -48,6 +50,6 @@ examples:
|
||||
reg = <0x6400000 0x90000>;
|
||||
#clock-cells = <1>;
|
||||
|
||||
clocks = <&xo_board>;
|
||||
clock-names = "xo";
|
||||
clocks = <&xo_board>, <&apcs_glb>;
|
||||
clock-names = "xo", "sys_apcs_aux";
|
||||
};
|
||||
|
||||
53
sys/contrib/device-tree/Bindings/clock/qcom,msm8996-cbf.yaml
Normal file
53
sys/contrib/device-tree/Bindings/clock/qcom,msm8996-cbf.yaml
Normal file
@ -0,0 +1,53 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,msm8996-cbf.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm MSM8996 Core Bus Fabric (CBF) clock controller
|
||||
|
||||
maintainers:
|
||||
- Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
||||
|
||||
description: >
|
||||
The clock controller for the Qualcomm MSM8996 CBF clock, which drives the
|
||||
interconnect between two CPU clusters.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,msm8996-cbf
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: XO source
|
||||
- description: SYS APCS AUX clock
|
||||
|
||||
'#clock-cells':
|
||||
const: 0
|
||||
|
||||
'#interconnect-cells':
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- '#clock-cells'
|
||||
- '#interconnect-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmcc.h>
|
||||
clock-controller@9a11000 {
|
||||
compatible = "qcom,msm8996-cbf";
|
||||
reg = <0x09a11000 0x10000>;
|
||||
clocks = <&rpmcc RPM_SMD_BB_CLK1>, <&apcs_glb>;
|
||||
#clock-cells = <0>;
|
||||
#interconnect-cells = <1>;
|
||||
};
|
||||
...
|
||||
51
sys/contrib/device-tree/Bindings/clock/qcom,qdu1000-gcc.yaml
Normal file
51
sys/contrib/device-tree/Bindings/clock/qcom,qdu1000-gcc.yaml
Normal file
@ -0,0 +1,51 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,qdu1000-gcc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller for QDU1000 and QRU1000
|
||||
|
||||
maintainers:
|
||||
- Melody Olvera <quic_molvera@quicinc.com>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module which supports the clocks, resets and
|
||||
power domains on QDU1000 and QRU1000
|
||||
|
||||
See also:: include/dt-bindings/clock/qcom,qdu1000-gcc.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,qdu1000-gcc
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: Sleep clock source
|
||||
- description: PCIE 0 Pipe clock source
|
||||
- description: PCIE 0 Phy Auxiliary clock source
|
||||
- description: USB3 Phy wrapper pipe clock source
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
clock-controller@100000 {
|
||||
compatible = "qcom,qdu1000-gcc";
|
||||
reg = <0x00100000 0x001f4200>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>,
|
||||
<&pcie_0_pipe_clk>, <&pcie_0_phy_aux_clk>,
|
||||
<&usb3_phy_wrapper_pipe_clk>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
@ -18,6 +18,7 @@ properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,qdu1000-rpmh-clk
|
||||
- qcom,sa8775p-rpmh-clk
|
||||
- qcom,sc7180-rpmh-clk
|
||||
- qcom,sc7280-rpmh-clk
|
||||
- qcom,sc8180x-rpmh-clk
|
||||
@ -31,6 +32,7 @@ properties:
|
||||
- qcom,sm8250-rpmh-clk
|
||||
- qcom,sm8350-rpmh-clk
|
||||
- qcom,sm8450-rpmh-clk
|
||||
- qcom,sm8550-rpmh-clk
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
84
sys/contrib/device-tree/Bindings/clock/qcom,sa8775p-gcc.yaml
Normal file
84
sys/contrib/device-tree/Bindings/clock/qcom,sa8775p-gcc.yaml
Normal file
@ -0,0 +1,84 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,sa8775p-gcc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller on sa8775p
|
||||
|
||||
maintainers:
|
||||
- Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module provides the clocks, resets and
|
||||
power domains on sa8775p.
|
||||
|
||||
See also:: include/dt-bindings/clock/qcom,sa8775p-gcc.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sa8775p-gcc
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: XO reference clock
|
||||
- description: Sleep clock
|
||||
- description: UFS memory first RX symbol clock
|
||||
- description: UFS memory second RX symbol clock
|
||||
- description: UFS memory first TX symbol clock
|
||||
- description: UFS card first RX symbol clock
|
||||
- description: UFS card second RX symbol clock
|
||||
- description: UFS card first TX symbol clock
|
||||
- description: Primary USB3 PHY wrapper pipe clock
|
||||
- description: Secondary USB3 PHY wrapper pipe clock
|
||||
- description: PCIe 0 pipe clock
|
||||
- description: PCIe 1 pipe clock
|
||||
- description: PCIe PHY clock
|
||||
- description: First EMAC controller reference clock
|
||||
- description: Second EMAC controller reference clock
|
||||
|
||||
protected-clocks:
|
||||
maxItems: 240
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/power/qcom-rpmpd.h>
|
||||
|
||||
gcc: clock-controller@100000 {
|
||||
compatible = "qcom,sa8775p-gcc";
|
||||
reg = <0x100000 0xc7018>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
||||
<&sleep_clk>,
|
||||
<&ufs_phy_rx_symbol_0_clk>,
|
||||
<&ufs_phy_rx_symbol_1_clk>,
|
||||
<&ufs_phy_tx_symbol_0_clk>,
|
||||
<&ufs_card_rx_symbol_0_clk>,
|
||||
<&ufs_card_rx_symbol_1_clk>,
|
||||
<&ufs_card_tx_symbol_0_clk>,
|
||||
<&usb_0_ssphy>,
|
||||
<&usb_1_ssphy>,
|
||||
<&pcie_0_pipe_clk>,
|
||||
<&pcie_1_pipe_clk>,
|
||||
<&pcie_phy_pipe_clk>,
|
||||
<&rxc0_ref_clk>,
|
||||
<&rxc1_ref_clk>;
|
||||
power-domains = <&rpmhpd SA8775P_CX>;
|
||||
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
...
|
||||
@ -0,0 +1,49 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,sm6350-camcc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Camera Clock & Reset Controller on SM6350
|
||||
|
||||
maintainers:
|
||||
- Konrad Dybcio <konrad.dybcio@linaro.org>
|
||||
|
||||
description: |
|
||||
Qualcomm camera clock control module provides the clocks, resets and power
|
||||
domains on SM6350.
|
||||
|
||||
See also:: include/dt-bindings/clock/qcom,sm6350-camcc.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sm6350-camcc
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
clock-controller@ad00000 {
|
||||
compatible = "qcom,sm6350-camcc";
|
||||
reg = <0x0ad00000 0x16000>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
...
|
||||
@ -32,6 +32,7 @@ properties:
|
||||
A phandle and PM domain specifier for the MMCX power domain.
|
||||
|
||||
required-opps:
|
||||
maxItems: 1
|
||||
description:
|
||||
A phandle to an OPP node describing required MMCX performance point.
|
||||
|
||||
|
||||
105
sys/contrib/device-tree/Bindings/clock/qcom,sm8550-dispcc.yaml
Normal file
105
sys/contrib/device-tree/Bindings/clock/qcom,sm8550-dispcc.yaml
Normal file
@ -0,0 +1,105 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,sm8550-dispcc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Display Clock & Reset Controller for SM8550
|
||||
|
||||
maintainers:
|
||||
- Bjorn Andersson <andersson@kernel.org>
|
||||
- Neil Armstrong <neil.armstrong@linaro.org>
|
||||
|
||||
description: |
|
||||
Qualcomm display clock control module provides the clocks, resets and power
|
||||
domains on SM8550.
|
||||
|
||||
See also:: include/dt-bindings/clock/qcom,sm8550-dispcc.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,sm8550-dispcc
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: Board Always On XO source
|
||||
- description: Display's AHB clock
|
||||
- description: sleep clock
|
||||
- description: Byte clock from DSI PHY0
|
||||
- description: Pixel clock from DSI PHY0
|
||||
- description: Byte clock from DSI PHY1
|
||||
- description: Pixel clock from DSI PHY1
|
||||
- description: Link clock from DP PHY0
|
||||
- description: VCO DIV clock from DP PHY0
|
||||
- description: Link clock from DP PHY1
|
||||
- description: VCO DIV clock from DP PHY1
|
||||
- description: Link clock from DP PHY2
|
||||
- description: VCO DIV clock from DP PHY2
|
||||
- description: Link clock from DP PHY3
|
||||
- description: VCO DIV clock from DP PHY3
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
power-domains:
|
||||
description:
|
||||
A phandle and PM domain specifier for the MMCX power domain.
|
||||
maxItems: 1
|
||||
|
||||
required-opps:
|
||||
description:
|
||||
A phandle to an OPP node describing required MMCX performance point.
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,sm8550-gcc.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/power/qcom-rpmpd.h>
|
||||
clock-controller@af00000 {
|
||||
compatible = "qcom,sm8550-dispcc";
|
||||
reg = <0x0af00000 0x10000>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK_A>,
|
||||
<&gcc GCC_DISP_AHB_CLK>,
|
||||
<&sleep_clk>,
|
||||
<&dsi0_phy 0>,
|
||||
<&dsi0_phy 1>,
|
||||
<&dsi1_phy 0>,
|
||||
<&dsi1_phy 1>,
|
||||
<&dp0_phy 0>,
|
||||
<&dp0_phy 1>,
|
||||
<&dp1_phy 0>,
|
||||
<&dp1_phy 1>,
|
||||
<&dp2_phy 0>,
|
||||
<&dp2_phy 1>,
|
||||
<&dp3_phy 0>,
|
||||
<&dp3_phy 1>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
power-domains = <&rpmhpd SM8550_MMCX>;
|
||||
required-opps = <&rpmhpd_opp_low_svs>;
|
||||
};
|
||||
...
|
||||
55
sys/contrib/device-tree/Bindings/clock/qcom,sm8550-tcsr.yaml
Normal file
55
sys/contrib/device-tree/Bindings/clock/qcom,sm8550-tcsr.yaml
Normal file
@ -0,0 +1,55 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,sm8550-tcsr.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm TCSR Clock Controller on SM8550
|
||||
|
||||
maintainers:
|
||||
- Bjorn Andersson <andersson@kernel.org>
|
||||
|
||||
description: |
|
||||
Qualcomm TCSR clock control module provides the clocks, resets and
|
||||
power domains on SM8550
|
||||
|
||||
See also:: include/dt-bindings/clock/qcom,sm8550-tcsr.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: qcom,sm8550-tcsr
|
||||
- const: syscon
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: TCXO pad clock
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
|
||||
clock-controller@1fc0000 {
|
||||
compatible = "qcom,sm8550-tcsr", "syscon";
|
||||
reg = <0x1fc0000 0x30000>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
...
|
||||
71
sys/contrib/device-tree/Bindings/clock/qcom,spmi-clkdiv.yaml
Normal file
71
sys/contrib/device-tree/Bindings/clock/qcom,spmi-clkdiv.yaml
Normal file
@ -0,0 +1,71 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,spmi-clkdiv.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm SPMI PMIC clock divider
|
||||
|
||||
maintainers:
|
||||
- Bjorn Andersson <andersson@kernel.org>
|
||||
- Stephen Boyd <sboyd@kernel.org>
|
||||
|
||||
description: |
|
||||
Qualcomm SPMI PMIC clock divider configures the clock frequency of a set of
|
||||
outputs on the PMIC. These clocks are typically wired through alternate
|
||||
functions on GPIO pins.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,spmi-clkdiv
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: xo
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
qcom,num-clkdivs:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: Number of CLKDIV peripherals.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- "#clock-cells"
|
||||
- qcom,num-clkdivs
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
pmic {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
clock-controller@5b00 {
|
||||
compatible = "qcom,spmi-clkdiv";
|
||||
reg = <0x5b00>;
|
||||
clocks = <&xo_board>;
|
||||
clock-names = "xo";
|
||||
#clock-cells = <1>;
|
||||
qcom,num-clkdivs = <3>;
|
||||
|
||||
assigned-clocks = <&pm8998_clk_divs 1>,
|
||||
<&pm8998_clk_divs 2>,
|
||||
<&pm8998_clk_divs 3>;
|
||||
assigned-clock-rates = <9600000>,
|
||||
<9600000>,
|
||||
<9600000>;
|
||||
};
|
||||
};
|
||||
@ -30,12 +30,12 @@ properties:
|
||||
- qcom,sm8250-videocc
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
minItems: 1
|
||||
maxItems: 3
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: bi_tcxo
|
||||
minItems: 1
|
||||
maxItems: 3
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
@ -68,6 +68,57 @@ required:
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,sc7180-videocc
|
||||
- qcom,sdm845-videocc
|
||||
- qcom,sm8150-videocc
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
clock-names:
|
||||
items:
|
||||
- const: bi_tcxo
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,sc7280-videocc
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: Board active XO source
|
||||
clock-names:
|
||||
items:
|
||||
- const: bi_tcxo
|
||||
- const: bi_tcxo_ao
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,sm8250-videocc
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: AHB
|
||||
- description: Board XO source
|
||||
- description: Board active XO source
|
||||
clock-names:
|
||||
items:
|
||||
- const: iface
|
||||
- const: bi_tcxo
|
||||
- const: bi_tcxo_ao
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
|
||||
@ -8,7 +8,6 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
title: SiFive FU540 Power Reset Clock Interrupt Controller (PRCI)
|
||||
|
||||
maintainers:
|
||||
- Sagar Kadam <sagar.kadam@sifive.com>
|
||||
- Paul Walmsley <paul.walmsley@sifive.com>
|
||||
|
||||
description:
|
||||
|
||||
@ -61,40 +61,7 @@ required:
|
||||
|
||||
examples:
|
||||
- |
|
||||
sysctrl@61840000 {
|
||||
compatible = "socionext,uniphier-sysctrl", "simple-mfd", "syscon";
|
||||
reg = <0x61840000 0x4000>;
|
||||
|
||||
clock {
|
||||
compatible = "socionext,uniphier-ld11-clock";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
// other nodes ...
|
||||
};
|
||||
|
||||
- |
|
||||
mioctrl@59810000 {
|
||||
compatible = "socionext,uniphier-mioctrl", "simple-mfd", "syscon";
|
||||
reg = <0x59810000 0x800>;
|
||||
|
||||
clock {
|
||||
compatible = "socionext,uniphier-ld11-mio-clock";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
// other nodes ...
|
||||
};
|
||||
|
||||
- |
|
||||
perictrl@59820000 {
|
||||
compatible = "socionext,uniphier-perictrl", "simple-mfd", "syscon";
|
||||
reg = <0x59820000 0x200>;
|
||||
|
||||
clock {
|
||||
compatible = "socionext,uniphier-ld11-peri-clock";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
// other nodes ...
|
||||
clock-controller {
|
||||
compatible = "socionext,uniphier-ld11-clock";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
238
sys/contrib/device-tree/Bindings/cpu/cpu-capacity.txt
Normal file
238
sys/contrib/device-tree/Bindings/cpu/cpu-capacity.txt
Normal file
@ -0,0 +1,238 @@
|
||||
==========================================
|
||||
CPU capacity bindings
|
||||
==========================================
|
||||
|
||||
==========================================
|
||||
1 - Introduction
|
||||
==========================================
|
||||
|
||||
Some systems may be configured to have cpus with different power/performance
|
||||
characteristics within the same chip. In this case, additional information has
|
||||
to be made available to the kernel for it to be aware of such differences and
|
||||
take decisions accordingly.
|
||||
|
||||
==========================================
|
||||
2 - CPU capacity definition
|
||||
==========================================
|
||||
|
||||
CPU capacity is a number that provides the scheduler information about CPUs
|
||||
heterogeneity. Such heterogeneity can come from micro-architectural differences
|
||||
(e.g., ARM big.LITTLE systems) or maximum frequency at which CPUs can run
|
||||
(e.g., SMP systems with multiple frequency domains). Heterogeneity in this
|
||||
context is about differing performance characteristics; this binding tries to
|
||||
capture a first-order approximation of the relative performance of CPUs.
|
||||
|
||||
CPU capacities are obtained by running a suitable benchmark. This binding makes
|
||||
no guarantees on the validity or suitability of any particular benchmark, the
|
||||
final capacity should, however, be:
|
||||
|
||||
* A "single-threaded" or CPU affine benchmark
|
||||
* Divided by the running frequency of the CPU executing the benchmark
|
||||
* Not subject to dynamic frequency scaling of the CPU
|
||||
|
||||
For the time being we however advise usage of the Dhrystone benchmark. What
|
||||
above thus becomes:
|
||||
|
||||
CPU capacities are obtained by running the Dhrystone benchmark on each CPU at
|
||||
max frequency (with caches enabled). The obtained DMIPS score is then divided
|
||||
by the frequency (in MHz) at which the benchmark has been run, so that
|
||||
DMIPS/MHz are obtained. Such values are then normalized w.r.t. the highest
|
||||
score obtained in the system.
|
||||
|
||||
==========================================
|
||||
3 - capacity-dmips-mhz
|
||||
==========================================
|
||||
|
||||
capacity-dmips-mhz is an optional cpu node [1] property: u32 value
|
||||
representing CPU capacity expressed in normalized DMIPS/MHz. At boot time, the
|
||||
maximum frequency available to the cpu is then used to calculate the capacity
|
||||
value internally used by the kernel.
|
||||
|
||||
capacity-dmips-mhz property is all-or-nothing: if it is specified for a cpu
|
||||
node, it has to be specified for every other cpu nodes, or the system will
|
||||
fall back to the default capacity value for every CPU. If cpufreq is not
|
||||
available, final capacities are calculated by directly using capacity-dmips-
|
||||
mhz values (normalized w.r.t. the highest value found while parsing the DT).
|
||||
|
||||
===========================================
|
||||
4 - Examples
|
||||
===========================================
|
||||
|
||||
Example 1 (ARM 64-bit, 6-cpu system, two clusters):
|
||||
The capacities-dmips-mhz or DMIPS/MHz values (scaled to 1024)
|
||||
are 1024 and 578 for cluster0 and cluster1. Further normalization
|
||||
is done by the operating system based on cluster0@max-freq=1100 and
|
||||
cluster1@max-freq=850, final capacities are 1024 for cluster0 and
|
||||
446 for cluster1 (578*850/1100).
|
||||
|
||||
cpus {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu-map {
|
||||
cluster0 {
|
||||
core0 {
|
||||
cpu = <&A57_0>;
|
||||
};
|
||||
core1 {
|
||||
cpu = <&A57_1>;
|
||||
};
|
||||
};
|
||||
|
||||
cluster1 {
|
||||
core0 {
|
||||
cpu = <&A53_0>;
|
||||
};
|
||||
core1 {
|
||||
cpu = <&A53_1>;
|
||||
};
|
||||
core2 {
|
||||
cpu = <&A53_2>;
|
||||
};
|
||||
core3 {
|
||||
cpu = <&A53_3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
idle-states {
|
||||
entry-method = "psci";
|
||||
|
||||
CPU_SLEEP_0: cpu-sleep-0 {
|
||||
compatible = "arm,idle-state";
|
||||
arm,psci-suspend-param = <0x0010000>;
|
||||
local-timer-stop;
|
||||
entry-latency-us = <100>;
|
||||
exit-latency-us = <250>;
|
||||
min-residency-us = <150>;
|
||||
};
|
||||
|
||||
CLUSTER_SLEEP_0: cluster-sleep-0 {
|
||||
compatible = "arm,idle-state";
|
||||
arm,psci-suspend-param = <0x1010000>;
|
||||
local-timer-stop;
|
||||
entry-latency-us = <800>;
|
||||
exit-latency-us = <700>;
|
||||
min-residency-us = <2500>;
|
||||
};
|
||||
};
|
||||
|
||||
A57_0: cpu@0 {
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x0 0x0>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&A57_L2>;
|
||||
clocks = <&scpi_dvfs 0>;
|
||||
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
|
||||
capacity-dmips-mhz = <1024>;
|
||||
};
|
||||
|
||||
A57_1: cpu@1 {
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x0 0x1>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&A57_L2>;
|
||||
clocks = <&scpi_dvfs 0>;
|
||||
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
|
||||
capacity-dmips-mhz = <1024>;
|
||||
};
|
||||
|
||||
A53_0: cpu@100 {
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x0 0x100>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&A53_L2>;
|
||||
clocks = <&scpi_dvfs 1>;
|
||||
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
|
||||
capacity-dmips-mhz = <578>;
|
||||
};
|
||||
|
||||
A53_1: cpu@101 {
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x0 0x101>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&A53_L2>;
|
||||
clocks = <&scpi_dvfs 1>;
|
||||
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
|
||||
capacity-dmips-mhz = <578>;
|
||||
};
|
||||
|
||||
A53_2: cpu@102 {
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x0 0x102>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&A53_L2>;
|
||||
clocks = <&scpi_dvfs 1>;
|
||||
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
|
||||
capacity-dmips-mhz = <578>;
|
||||
};
|
||||
|
||||
A53_3: cpu@103 {
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x0 0x103>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&A53_L2>;
|
||||
clocks = <&scpi_dvfs 1>;
|
||||
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
|
||||
capacity-dmips-mhz = <578>;
|
||||
};
|
||||
|
||||
A57_L2: l2-cache0 {
|
||||
compatible = "cache";
|
||||
};
|
||||
|
||||
A53_L2: l2-cache1 {
|
||||
compatible = "cache";
|
||||
};
|
||||
};
|
||||
|
||||
Example 2 (ARM 32-bit, 4-cpu system, two clusters,
|
||||
cpus 0,1@1GHz, cpus 2,3@500MHz):
|
||||
capacities-dmips-mhz are scaled w.r.t. 2 (cpu@0 and cpu@1), this means that first
|
||||
cpu@0 and cpu@1 are twice fast than cpu@2 and cpu@3 (at the same frequency)
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <0>;
|
||||
capacity-dmips-mhz = <2>;
|
||||
};
|
||||
|
||||
cpu1: cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <1>;
|
||||
capacity-dmips-mhz = <2>;
|
||||
};
|
||||
|
||||
cpu2: cpu@2 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <0x100>;
|
||||
capacity-dmips-mhz = <1>;
|
||||
};
|
||||
|
||||
cpu3: cpu@3 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <0x101>;
|
||||
capacity-dmips-mhz = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
===========================================
|
||||
5 - References
|
||||
===========================================
|
||||
|
||||
[1] ARM Linux Kernel documentation - CPUs bindings
|
||||
Documentation/devicetree/bindings/arm/cpus.yaml
|
||||
@ -26,8 +26,13 @@ properties:
|
||||
items:
|
||||
- enum:
|
||||
- qcom,qdu1000-cpufreq-epss
|
||||
- qcom,sc7280-cpufreq-epss
|
||||
- qcom,sc8280xp-cpufreq-epss
|
||||
- qcom,sm6375-cpufreq-epss
|
||||
- qcom,sm8250-cpufreq-epss
|
||||
- qcom,sm8350-cpufreq-epss
|
||||
- qcom,sm8450-cpufreq-epss
|
||||
- qcom,sm8550-cpufreq-epss
|
||||
- const: qcom,cpufreq-epss
|
||||
|
||||
reg:
|
||||
|
||||
@ -17,6 +17,9 @@ description: |
|
||||
on the CPU OPP in use. The CPUFreq driver sets the CPR power domain level
|
||||
according to the required OPPs defined in the CPU OPP tables.
|
||||
|
||||
For old implementation efuses are parsed to select the correct opp table and
|
||||
voltage and CPR is not supported/used.
|
||||
|
||||
select:
|
||||
properties:
|
||||
compatible:
|
||||
@ -33,37 +36,65 @@ select:
|
||||
required:
|
||||
- compatible
|
||||
|
||||
properties:
|
||||
cpus:
|
||||
type: object
|
||||
|
||||
patternProperties:
|
||||
'^cpu@[0-9a-f]+$':
|
||||
type: object
|
||||
|
||||
properties:
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
power-domain-names:
|
||||
items:
|
||||
- const: cpr
|
||||
|
||||
required:
|
||||
- power-domains
|
||||
- power-domain-names
|
||||
|
||||
patternProperties:
|
||||
'^opp-table(-[a-z0-9]+)?$':
|
||||
if:
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
const: operating-points-v2-kryo-cpu
|
||||
then:
|
||||
$ref: /schemas/opp/opp-v2-kryo-cpu.yaml#
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
const: operating-points-v2-qcom-level
|
||||
then:
|
||||
$ref: /schemas/opp/opp-v2-qcom-level.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
const: operating-points-v2-kryo-cpu
|
||||
contains:
|
||||
enum:
|
||||
- qcom,qcs404
|
||||
|
||||
then:
|
||||
properties:
|
||||
cpus:
|
||||
type: object
|
||||
|
||||
patternProperties:
|
||||
'^cpu@[0-9a-f]+$':
|
||||
type: object
|
||||
|
||||
properties:
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
power-domain-names:
|
||||
items:
|
||||
- const: cpr
|
||||
|
||||
required:
|
||||
- power-domains
|
||||
- power-domain-names
|
||||
|
||||
patternProperties:
|
||||
'^opp-?[0-9]+$':
|
||||
required:
|
||||
- required-opps
|
||||
'^opp-table(-[a-z0-9]+)?$':
|
||||
if:
|
||||
properties:
|
||||
compatible:
|
||||
const: operating-points-v2-kryo-cpu
|
||||
then:
|
||||
patternProperties:
|
||||
'^opp-?[0-9]+$':
|
||||
required:
|
||||
- required-opps
|
||||
|
||||
additionalProperties: true
|
||||
|
||||
|
||||
@ -14,6 +14,7 @@ properties:
|
||||
enum:
|
||||
- allwinner,sun8i-h3-crypto
|
||||
- allwinner,sun8i-r40-crypto
|
||||
- allwinner,sun20i-d1-crypto
|
||||
- allwinner,sun50i-a64-crypto
|
||||
- allwinner,sun50i-h5-crypto
|
||||
- allwinner,sun50i-h6-crypto
|
||||
@ -29,6 +30,7 @@ properties:
|
||||
- description: Bus clock
|
||||
- description: Module clock
|
||||
- description: MBus clock
|
||||
- description: TRNG clock (RC oscillator)
|
||||
minItems: 2
|
||||
|
||||
clock-names:
|
||||
@ -36,6 +38,7 @@ properties:
|
||||
- const: bus
|
||||
- const: mod
|
||||
- const: ram
|
||||
- const: trng
|
||||
minItems: 2
|
||||
|
||||
resets:
|
||||
@ -44,19 +47,33 @@ properties:
|
||||
if:
|
||||
properties:
|
||||
compatible:
|
||||
const: allwinner,sun50i-h6-crypto
|
||||
enum:
|
||||
- allwinner,sun20i-d1-crypto
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 3
|
||||
minItems: 4
|
||||
clock-names:
|
||||
minItems: 3
|
||||
minItems: 4
|
||||
else:
|
||||
properties:
|
||||
clocks:
|
||||
maxItems: 2
|
||||
clock-names:
|
||||
maxItems: 2
|
||||
if:
|
||||
properties:
|
||||
compatible:
|
||||
const: allwinner,sun50i-h6-crypto
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 3
|
||||
maxItems: 3
|
||||
clock-names:
|
||||
minItems: 3
|
||||
maxItems: 3
|
||||
else:
|
||||
properties:
|
||||
clocks:
|
||||
maxItems: 2
|
||||
clock-names:
|
||||
maxItems: 2
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
@ -0,0 +1,49 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/crypto/aspeed,ast2600-acry.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: ASPEED ACRY ECDSA/RSA Hardware Accelerator Engines
|
||||
|
||||
maintainers:
|
||||
- Neal Liu <neal_liu@aspeedtech.com>
|
||||
|
||||
description:
|
||||
The ACRY ECDSA/RSA engines is designed to accelerate the throughput
|
||||
of ECDSA/RSA signature and verification. Basically, ACRY can be
|
||||
divided into two independent engines - ECC Engine and RSA Engine.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- aspeed,ast2600-acry
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: acry base address & size
|
||||
- description: acry sram base address & size
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- interrupts
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/ast2600-clock.h>
|
||||
acry: crypto@1e6fa000 {
|
||||
compatible = "aspeed,ast2600-acry";
|
||||
reg = <0x1e6fa000 0x400>, <0x1e710000 0x1800>;
|
||||
interrupts = <160>;
|
||||
clocks = <&syscon ASPEED_CLK_GATE_RSACLK>;
|
||||
};
|
||||
@ -6,12 +6,18 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: STMicroelectronics STM32 HASH
|
||||
|
||||
description: The STM32 HASH block is built on the HASH block found in
|
||||
the STn8820 SoC introduced in 2007, and subsequently used in the U8500
|
||||
SoC in 2010.
|
||||
|
||||
maintainers:
|
||||
- Lionel Debieve <lionel.debieve@foss.st.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- st,stn8820-hash
|
||||
- stericsson,ux500-hash
|
||||
- st,stm32f456-hash
|
||||
- st,stm32f756-hash
|
||||
|
||||
@ -41,11 +47,26 @@ properties:
|
||||
maximum: 2
|
||||
default: 0
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- interrupts
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
const: stericsson,ux500-hash
|
||||
then:
|
||||
properties:
|
||||
interrupts: false
|
||||
else:
|
||||
required:
|
||||
- interrupts
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
|
||||
180
sys/contrib/device-tree/Bindings/display/bridge/cdns,dsi.yaml
Normal file
180
sys/contrib/device-tree/Bindings/display/bridge/cdns,dsi.yaml
Normal file
@ -0,0 +1,180 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/bridge/cdns,dsi.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Cadence DSI bridge
|
||||
|
||||
maintainers:
|
||||
- Boris Brezillon <boris.brezillon@bootlin.com>
|
||||
|
||||
description: |
|
||||
CDNS DSI is a bridge device which converts DPI to DSI
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- cdns,dsi
|
||||
- ti,j721e-dsi
|
||||
|
||||
reg:
|
||||
minItems: 1
|
||||
items:
|
||||
- description:
|
||||
Register block for controller's registers.
|
||||
- description:
|
||||
Register block for wrapper settings registers in case of TI J7 SoCs.
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: PSM clock, used by the IP
|
||||
- description: sys clock, used by the IP
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: dsi_p_clk
|
||||
- const: dsi_sys_clk
|
||||
|
||||
phys:
|
||||
maxItems: 1
|
||||
|
||||
phy-names:
|
||||
const: dphy
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
reset-names:
|
||||
const: dsi_p_rst
|
||||
|
||||
ports:
|
||||
$ref: /schemas/graph.yaml#/properties/ports
|
||||
|
||||
properties:
|
||||
port@0:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description:
|
||||
Output port representing the DSI output. It can have
|
||||
at most 4 endpoints. The endpoint number is directly encoding
|
||||
the DSI virtual channel used by this device.
|
||||
|
||||
port@1:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description:
|
||||
Input port representing the DPI input.
|
||||
|
||||
required:
|
||||
- port@1
|
||||
|
||||
allOf:
|
||||
- $ref: ../dsi-controller.yaml#
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: ti,j721e-dsi
|
||||
then:
|
||||
properties:
|
||||
reg:
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
else:
|
||||
properties:
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- clocks
|
||||
- clock-names
|
||||
- phys
|
||||
- phy-names
|
||||
- ports
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
bus {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
dsi@fd0c0000 {
|
||||
compatible = "cdns,dsi";
|
||||
reg = <0x0 0xfd0c0000 0x0 0x1000>;
|
||||
clocks = <&pclk>, <&sysclk>;
|
||||
clock-names = "dsi_p_clk", "dsi_sys_clk";
|
||||
interrupts = <1>;
|
||||
phys = <&dphy0>;
|
||||
phy-names = "dphy";
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
endpoint {
|
||||
remote-endpoint = <&xxx_dpi_output>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
panel@0 {
|
||||
compatible = "panasonic,vvx10f034n00";
|
||||
reg = <0>;
|
||||
power-supply = <&vcc_lcd_reg>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
- |
|
||||
bus {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
dsi@fd0c0000 {
|
||||
compatible = "cdns,dsi";
|
||||
reg = <0x0 0xfd0c0000 0x0 0x1000>;
|
||||
clocks = <&pclk>, <&sysclk>;
|
||||
clock-names = "dsi_p_clk", "dsi_sys_clk";
|
||||
interrupts = <1>;
|
||||
phys = <&dphy1>;
|
||||
phy-names = "dphy";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&dsi_panel_input>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
endpoint {
|
||||
remote-endpoint = <&xxx_dpi_output>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -16,7 +16,9 @@ description: |
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: fsl,imx8mp-ldb
|
||||
enum:
|
||||
- fsl,imx8mp-ldb
|
||||
- fsl,imx93-ldb
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
@ -57,6 +59,18 @@ required:
|
||||
- clocks
|
||||
- ports
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: fsl,imx93-ldb
|
||||
then:
|
||||
properties:
|
||||
ports:
|
||||
properties:
|
||||
port@2: false
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
|
||||
@ -52,9 +52,49 @@ properties:
|
||||
maxItems: 1
|
||||
description: extcon specifier for the Power Delivery
|
||||
|
||||
port:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: A port node pointing to DPI host port node
|
||||
ports:
|
||||
$ref: /schemas/graph.yaml#/properties/ports
|
||||
|
||||
properties:
|
||||
port@0:
|
||||
$ref: /schemas/graph.yaml#/$defs/port-base
|
||||
unevaluatedProperties: false
|
||||
description: A port node pointing to DPI host port node
|
||||
|
||||
properties:
|
||||
endpoint:
|
||||
$ref: /schemas/graph.yaml#/$defs/endpoint-base
|
||||
unevaluatedProperties: false
|
||||
|
||||
properties:
|
||||
link-frequencies:
|
||||
minItems: 1
|
||||
maxItems: 1
|
||||
description: Allowed max link frequencies in Hz
|
||||
|
||||
port@1:
|
||||
$ref: /schemas/graph.yaml#/$defs/port-base
|
||||
unevaluatedProperties: false
|
||||
description: Video port for DP output
|
||||
|
||||
properties:
|
||||
endpoint:
|
||||
$ref: /schemas/graph.yaml#/$defs/endpoint-base
|
||||
unevaluatedProperties: false
|
||||
|
||||
properties:
|
||||
data-lanes:
|
||||
minItems: 1
|
||||
uniqueItems: true
|
||||
items:
|
||||
- enum: [ 0, 1 ]
|
||||
- const: 1
|
||||
- const: 2
|
||||
- const: 3
|
||||
|
||||
required:
|
||||
- port@0
|
||||
- port@1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
@ -63,6 +103,7 @@ required:
|
||||
- interrupts
|
||||
- reset-gpios
|
||||
- extcon
|
||||
- ports
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
@ -85,9 +126,24 @@ examples:
|
||||
reset-gpios = <&pio 179 1>;
|
||||
extcon = <&usbc_extcon>;
|
||||
|
||||
port {
|
||||
it6505_in: endpoint {
|
||||
remote-endpoint = <&dpi_out>;
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
it6505_in: endpoint {
|
||||
remote-endpoint = <&dpi_out>;
|
||||
link-frequencies = /bits/ 64 <150000000>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
it6505_out: endpoint {
|
||||
remote-endpoint = <&dp_in>;
|
||||
data-lanes = <0 1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -17,7 +17,9 @@ description: |
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: ite,it66121
|
||||
enum:
|
||||
- ite,it66121
|
||||
- ite,it6610
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
@ -11,13 +11,14 @@ maintainers:
|
||||
|
||||
description: |
|
||||
This binding describes the MIPI DSI/CSI-2 encoder embedded in the Renesas
|
||||
R-Car V3U SoC. The encoder can operate in either DSI or CSI-2 mode, with up
|
||||
R-Car Gen4 SoCs. The encoder can operate in either DSI or CSI-2 mode, with up
|
||||
to four data lanes.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- renesas,r8a779a0-dsi-csi2-tx # for V3U
|
||||
- renesas,r8a779g0-dsi-csi2-tx # for V4H
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
@ -22,6 +22,7 @@ properties:
|
||||
items:
|
||||
- enum:
|
||||
- renesas,r9a07g044-mipi-dsi # RZ/G2{L,LC}
|
||||
- renesas,r9a07g054-mipi-dsi # RZ/V2L
|
||||
- const: renesas,rzg2l-mipi-dsi
|
||||
|
||||
reg:
|
||||
|
||||
108
sys/contrib/device-tree/Bindings/display/bridge/sil,sii8620.yaml
Normal file
108
sys/contrib/device-tree/Bindings/display/bridge/sil,sii8620.yaml
Normal file
@ -0,0 +1,108 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/bridge/sil,sii8620.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Silicon Image SiI8620 HDMI/MHL bridge
|
||||
|
||||
maintainers:
|
||||
- Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: sil,sii8620
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: xtal
|
||||
|
||||
cvcc10-supply:
|
||||
description: Digital Core Supply Voltage (1.0V)
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
iovcc18-supply:
|
||||
description: I/O Supply Voltage (1.8V)
|
||||
|
||||
reset-gpios:
|
||||
maxItems: 1
|
||||
|
||||
ports:
|
||||
$ref: /schemas/graph.yaml#/properties/ports
|
||||
unevaluatedProperties: false
|
||||
|
||||
properties:
|
||||
port@0:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description:
|
||||
Video port for HDMI (encoder) input
|
||||
|
||||
port@1:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description:
|
||||
MHL to connector port
|
||||
|
||||
required:
|
||||
- port@0
|
||||
- port@1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- cvcc10-supply
|
||||
- interrupts
|
||||
- iovcc18-supply
|
||||
- reset-gpios
|
||||
- ports
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
i2c {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
bridge@39 {
|
||||
reg = <0x39>;
|
||||
compatible = "sil,sii8620";
|
||||
cvcc10-supply = <&ldo36_reg>;
|
||||
iovcc18-supply = <&ldo34_reg>;
|
||||
interrupt-parent = <&gpf0>;
|
||||
interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reset-gpios = <&gpv7 0 GPIO_ACTIVE_LOW>;
|
||||
clocks = <&pmu_system_controller 0>;
|
||||
clock-names = "xtal";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
mhl_to_hdmi: endpoint {
|
||||
remote-endpoint = <&hdmi_to_mhl>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
mhl_to_musb_con: endpoint {
|
||||
remote-endpoint = <&musb_con_to_mhl>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -31,6 +31,7 @@ properties:
|
||||
- items:
|
||||
- enum:
|
||||
- mediatek,mt8186-disp-aal
|
||||
- mediatek,mt8188-disp-aal
|
||||
- mediatek,mt8192-disp-aal
|
||||
- mediatek,mt8195-disp-aal
|
||||
- const: mediatek,mt8183-disp-aal
|
||||
|
||||
@ -27,12 +27,13 @@ properties:
|
||||
- const: mediatek,mt8192-disp-ccorr
|
||||
- items:
|
||||
- enum:
|
||||
- mediatek,mt8188-disp-ccorr
|
||||
- mediatek,mt8195-disp-ccorr
|
||||
- const: mediatek,mt8192-disp-ccorr
|
||||
- items:
|
||||
- enum:
|
||||
- mediatek,mt8186-disp-ccorr
|
||||
- const: mediatek,mt8183-disp-ccorr
|
||||
- const: mediatek,mt8192-disp-ccorr
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
@ -37,6 +37,7 @@ properties:
|
||||
- enum:
|
||||
- mediatek,mt8183-disp-color
|
||||
- mediatek,mt8186-disp-color
|
||||
- mediatek,mt8188-disp-color
|
||||
- mediatek,mt8192-disp-color
|
||||
- mediatek,mt8195-disp-color
|
||||
- const: mediatek,mt8173-disp-color
|
||||
|
||||
@ -27,6 +27,7 @@ properties:
|
||||
- items:
|
||||
- enum:
|
||||
- mediatek,mt8186-disp-dither
|
||||
- mediatek,mt8188-disp-dither
|
||||
- mediatek,mt8192-disp-dither
|
||||
- mediatek,mt8195-disp-dither
|
||||
- const: mediatek,mt8183-disp-dither
|
||||
|
||||
@ -28,6 +28,7 @@ properties:
|
||||
- items:
|
||||
- enum:
|
||||
- mediatek,mt8186-disp-gamma
|
||||
- mediatek,mt8188-disp-gamma
|
||||
- mediatek,mt8192-disp-gamma
|
||||
- mediatek,mt8195-disp-gamma
|
||||
- const: mediatek,mt8183-disp-gamma
|
||||
|
||||
@ -36,6 +36,7 @@ properties:
|
||||
- const: mediatek,mt2701-disp-ovl
|
||||
- items:
|
||||
- enum:
|
||||
- mediatek,mt8188-disp-ovl
|
||||
- mediatek,mt8195-disp-ovl
|
||||
- const: mediatek,mt8183-disp-ovl
|
||||
- items:
|
||||
|
||||
@ -26,6 +26,7 @@ properties:
|
||||
- items:
|
||||
- enum:
|
||||
- mediatek,mt8186-disp-postmask
|
||||
- mediatek,mt8188-disp-postmask
|
||||
- const: mediatek,mt8192-disp-postmask
|
||||
|
||||
reg:
|
||||
|
||||
@ -31,6 +31,10 @@ properties:
|
||||
- const: mediatek,mt8183-disp-rdma
|
||||
- items:
|
||||
- const: mediatek,mt8195-disp-rdma
|
||||
- items:
|
||||
- enum:
|
||||
- mediatek,mt8188-disp-rdma
|
||||
- const: mediatek,mt8195-disp-rdma
|
||||
- items:
|
||||
- enum:
|
||||
- mediatek,mt7623-disp-rdma
|
||||
|
||||
@ -21,6 +21,9 @@ properties:
|
||||
- qcom,sc7280-edp
|
||||
- qcom,sc8180x-dp
|
||||
- qcom,sc8180x-edp
|
||||
- qcom,sc8280xp-dp
|
||||
- qcom,sc8280xp-edp
|
||||
- qcom,sdm845-dp
|
||||
- qcom,sm8350-dp
|
||||
|
||||
reg:
|
||||
@ -68,8 +71,7 @@ properties:
|
||||
items:
|
||||
- const: dp
|
||||
|
||||
operating-points-v2:
|
||||
maxItems: 1
|
||||
operating-points-v2: true
|
||||
|
||||
opp-table: true
|
||||
|
||||
@ -81,6 +83,7 @@ properties:
|
||||
|
||||
data-lanes:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
deprecated: true
|
||||
minItems: 1
|
||||
maxItems: 4
|
||||
items:
|
||||
@ -102,8 +105,28 @@ properties:
|
||||
description: Input endpoint of the controller
|
||||
|
||||
port@1:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
$ref: /schemas/graph.yaml#/$defs/port-base
|
||||
description: Output endpoint of the controller
|
||||
properties:
|
||||
endpoint:
|
||||
$ref: /schemas/media/video-interfaces.yaml#
|
||||
unevaluatedProperties: false
|
||||
properties:
|
||||
data-lanes:
|
||||
minItems: 1
|
||||
maxItems: 4
|
||||
items:
|
||||
enum: [ 0, 1, 2, 3 ]
|
||||
|
||||
link-frequencies:
|
||||
minItems: 1
|
||||
maxItems: 4
|
||||
items:
|
||||
enum: [ 1620000000, 2700000000, 5400000000, 8100000000 ]
|
||||
|
||||
required:
|
||||
- port@0
|
||||
- port@1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
@ -127,11 +150,10 @@ allOf:
|
||||
enum:
|
||||
- qcom,sc7280-edp
|
||||
- qcom,sc8180x-edp
|
||||
- qcom,sc8280xp-edp
|
||||
then:
|
||||
properties:
|
||||
"#sound-dai-cells": false
|
||||
reg:
|
||||
maxItems: 4
|
||||
else:
|
||||
properties:
|
||||
aux-bus: false
|
||||
@ -193,6 +215,8 @@ examples:
|
||||
reg = <1>;
|
||||
endpoint {
|
||||
remote-endpoint = <&typec>;
|
||||
data-lanes = <0 1>;
|
||||
link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -13,7 +13,15 @@ maintainers:
|
||||
description: |
|
||||
Common properties for QCom DPU display controller.
|
||||
|
||||
# Do not select this by default, otherwise it is also selected for all
|
||||
# display-controller@ nodes
|
||||
select:
|
||||
false
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
pattern: '^display-controller@[0-9a-f]+$'
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
@ -40,10 +48,6 @@ properties:
|
||||
- port@0
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- clocks
|
||||
- interrupts
|
||||
- power-domains
|
||||
- operating-points-v2
|
||||
|
||||
@ -9,14 +9,33 @@ title: Qualcomm Display DSI controller
|
||||
maintainers:
|
||||
- Krishna Manikandan <quic_mkrishn@quicinc.com>
|
||||
|
||||
allOf:
|
||||
- $ref: "../dsi-controller.yaml#"
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,mdss-dsi-ctrl
|
||||
- qcom,dsi-ctrl-6g-qcm2290
|
||||
oneOf:
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,apq8064-dsi-ctrl
|
||||
- qcom,msm8916-dsi-ctrl
|
||||
- qcom,msm8953-dsi-ctrl
|
||||
- qcom,msm8974-dsi-ctrl
|
||||
- qcom,msm8996-dsi-ctrl
|
||||
- qcom,msm8998-dsi-ctrl
|
||||
- qcom,qcm2290-dsi-ctrl
|
||||
- qcom,sc7180-dsi-ctrl
|
||||
- qcom,sc7280-dsi-ctrl
|
||||
- qcom,sdm660-dsi-ctrl
|
||||
- qcom,sdm845-dsi-ctrl
|
||||
- qcom,sm8150-dsi-ctrl
|
||||
- qcom,sm8250-dsi-ctrl
|
||||
- qcom,sm8350-dsi-ctrl
|
||||
- qcom,sm8450-dsi-ctrl
|
||||
- qcom,sm8550-dsi-ctrl
|
||||
- const: qcom,mdss-dsi-ctrl
|
||||
- items:
|
||||
- enum:
|
||||
- dsi-ctrl-6g-qcm2290
|
||||
- const: qcom,mdss-dsi-ctrl
|
||||
deprecated: true
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
@ -28,22 +47,23 @@ properties:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Display byte clock
|
||||
- description: Display byte interface clock
|
||||
- description: Display pixel clock
|
||||
- description: Display core clock
|
||||
- description: Display AHB clock
|
||||
- description: Display AXI clock
|
||||
description: |
|
||||
Several clocks are used, depending on the variant. Typical ones are::
|
||||
- bus:: Display AHB clock.
|
||||
- byte:: Display byte clock.
|
||||
- byte_intf:: Display byte interface clock.
|
||||
- core:: Display core clock.
|
||||
- core_mss:: Core MultiMedia SubSystem clock.
|
||||
- iface:: Display AXI clock.
|
||||
- mdp_core:: MDP Core clock.
|
||||
- mnoc:: MNOC clock
|
||||
- pixel:: Display pixel clock.
|
||||
minItems: 3
|
||||
maxItems: 9
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: byte
|
||||
- const: byte_intf
|
||||
- const: pixel
|
||||
- const: core
|
||||
- const: iface
|
||||
- const: bus
|
||||
minItems: 3
|
||||
maxItems: 9
|
||||
|
||||
phys:
|
||||
maxItems: 1
|
||||
@ -52,10 +72,6 @@ properties:
|
||||
deprecated: true
|
||||
const: dsi
|
||||
|
||||
"#address-cells": true
|
||||
|
||||
"#size-cells": true
|
||||
|
||||
syscon-sfpb:
|
||||
description: A phandle to mmss_sfpb syscon node (only for DSIv2).
|
||||
$ref: "/schemas/types.yaml#/definitions/phandle"
|
||||
@ -67,12 +83,16 @@ properties:
|
||||
2 DSI links.
|
||||
|
||||
assigned-clocks:
|
||||
maxItems: 2
|
||||
minItems: 2
|
||||
maxItems: 4
|
||||
description: |
|
||||
Parents of "byte" and "pixel" for the given platform.
|
||||
For DSIv2 platforms this should contain "byte", "esc", "src" and
|
||||
"pixel_src" clocks.
|
||||
|
||||
assigned-clock-parents:
|
||||
maxItems: 2
|
||||
minItems: 2
|
||||
maxItems: 4
|
||||
description: |
|
||||
The Byte clock and Pixel clock PLL outputs provided by a DSI PHY block.
|
||||
|
||||
@ -103,7 +123,7 @@ properties:
|
||||
properties:
|
||||
data-lanes:
|
||||
maxItems: 4
|
||||
minItems: 4
|
||||
minItems: 1
|
||||
items:
|
||||
enum: [ 0, 1, 2, 3 ]
|
||||
|
||||
@ -119,7 +139,7 @@ properties:
|
||||
properties:
|
||||
data-lanes:
|
||||
maxItems: 4
|
||||
minItems: 4
|
||||
minItems: 1
|
||||
items:
|
||||
enum: [ 0, 1, 2, 3 ]
|
||||
|
||||
@ -127,6 +147,26 @@ properties:
|
||||
- port@0
|
||||
- port@1
|
||||
|
||||
avdd-supply:
|
||||
description:
|
||||
Phandle to vdd regulator device node
|
||||
|
||||
vcca-supply:
|
||||
description:
|
||||
Phandle to vdd regulator device node
|
||||
|
||||
vdd-supply:
|
||||
description:
|
||||
VDD regulator
|
||||
|
||||
vddio-supply:
|
||||
description:
|
||||
VDD-IO regulator
|
||||
|
||||
vdda-supply:
|
||||
description:
|
||||
VDDA regulator
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
@ -139,7 +179,192 @@ required:
|
||||
- assigned-clock-parents
|
||||
- ports
|
||||
|
||||
additionalProperties: false
|
||||
allOf:
|
||||
- $ref: ../dsi-controller.yaml#
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,apq8064-dsi-ctrl
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
maxItems: 7
|
||||
clock-names:
|
||||
items:
|
||||
- const: iface
|
||||
- const: bus
|
||||
- const: core_mmss
|
||||
- const: src
|
||||
- const: byte
|
||||
- const: pixel
|
||||
- const: core
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,msm8916-dsi-ctrl
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
maxItems: 6
|
||||
clock-names:
|
||||
items:
|
||||
- const: mdp_core
|
||||
- const: iface
|
||||
- const: bus
|
||||
- const: byte
|
||||
- const: pixel
|
||||
- const: core
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,msm8953-dsi-ctrl
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
maxItems: 6
|
||||
clock-names:
|
||||
items:
|
||||
- const: mdp_core
|
||||
- const: iface
|
||||
- const: bus
|
||||
- const: byte
|
||||
- const: pixel
|
||||
- const: core
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,msm8974-dsi-ctrl
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
maxItems: 7
|
||||
clock-names:
|
||||
items:
|
||||
- const: mdp_core
|
||||
- const: iface
|
||||
- const: bus
|
||||
- const: byte
|
||||
- const: pixel
|
||||
- const: core
|
||||
- const: core_mmss
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,msm8996-dsi-ctrl
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
maxItems: 7
|
||||
clock-names:
|
||||
items:
|
||||
- const: mdp_core
|
||||
- const: byte
|
||||
- const: iface
|
||||
- const: bus
|
||||
- const: core_mmss
|
||||
- const: pixel
|
||||
- const: core
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,msm8998-dsi-ctrl
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
maxItems: 6
|
||||
clock-names:
|
||||
items:
|
||||
- const: byte
|
||||
- const: byte_intf
|
||||
- const: pixel
|
||||
- const: core
|
||||
- const: iface
|
||||
- const: bus
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,sc7180-dsi-ctrl
|
||||
- qcom,sc7280-dsi-ctrl
|
||||
- qcom,sm8150-dsi-ctrl
|
||||
- qcom,sm8250-dsi-ctrl
|
||||
- qcom,sm8350-dsi-ctrl
|
||||
- qcom,sm8450-dsi-ctrl
|
||||
- qcom,sm8550-dsi-ctrl
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
maxItems: 6
|
||||
clock-names:
|
||||
items:
|
||||
- const: byte
|
||||
- const: byte_intf
|
||||
- const: pixel
|
||||
- const: core
|
||||
- const: iface
|
||||
- const: bus
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,sdm660-dsi-ctrl
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
maxItems: 9
|
||||
clock-names:
|
||||
items:
|
||||
- const: mdp_core
|
||||
- const: byte
|
||||
- const: byte_intf
|
||||
- const: mnoc
|
||||
- const: iface
|
||||
- const: bus
|
||||
- const: core_mmss
|
||||
- const: pixel
|
||||
- const: core
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,sdm845-dsi-ctrl
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
maxItems: 6
|
||||
clock-names:
|
||||
items:
|
||||
- const: byte
|
||||
- const: byte_intf
|
||||
- const: pixel
|
||||
- const: core
|
||||
- const: iface
|
||||
- const: bus
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
@ -149,7 +374,7 @@ examples:
|
||||
#include <dt-bindings/power/qcom-rpmpd.h>
|
||||
|
||||
dsi@ae94000 {
|
||||
compatible = "qcom,mdss-dsi-ctrl";
|
||||
compatible = "qcom,sc7180-dsi-ctrl", "qcom,mdss-dsi-ctrl";
|
||||
reg = <0x0ae94000 0x400>;
|
||||
reg-names = "dsi_ctrl";
|
||||
|
||||
|
||||
@ -16,6 +16,7 @@ properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,dsi-phy-28nm-hpm
|
||||
- qcom,dsi-phy-28nm-hpm-fam-b
|
||||
- qcom,dsi-phy-28nm-lp
|
||||
- qcom,dsi-phy-28nm-8960
|
||||
|
||||
|
||||
@ -18,6 +18,10 @@ properties:
|
||||
- qcom,dsi-phy-7nm
|
||||
- qcom,dsi-phy-7nm-8150
|
||||
- qcom,sc7280-dsi-phy-7nm
|
||||
- qcom,sm6375-dsi-phy-7nm
|
||||
- qcom,sm8350-dsi-phy-5nm
|
||||
- qcom,sm8450-dsi-phy-5nm
|
||||
- qcom,sm8550-dsi-phy-4nm
|
||||
|
||||
reg:
|
||||
items:
|
||||
@ -44,7 +48,6 @@ required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- vdds-supply
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
|
||||
@ -4,14 +4,13 @@
|
||||
$id: http://devicetree.org/schemas/display/msm/dsi-phy-common.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Description of Qualcomm Display DSI PHY common dt properties
|
||||
title: Qualcomm Display DSI PHY Common Properties
|
||||
|
||||
maintainers:
|
||||
- Krishna Manikandan <quic_mkrishn@quicinc.com>
|
||||
|
||||
description: |
|
||||
This defines the DSI PHY dt properties which are common for all
|
||||
dsi phy versions.
|
||||
description:
|
||||
Common properties for Qualcomm Display DSI PHY.
|
||||
|
||||
properties:
|
||||
"#clock-cells":
|
||||
|
||||
@ -89,7 +89,7 @@ properties:
|
||||
help bring the GPU out of secure mode.
|
||||
properties:
|
||||
memory-region:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
maxItems: 1
|
||||
|
||||
firmware-name:
|
||||
description: |
|
||||
@ -149,6 +149,8 @@ allOf:
|
||||
description: GPU 3D engine clock
|
||||
- const: rbbmtimer
|
||||
description: GPU RBBM Timer for Adreno 5xx series
|
||||
- const: rbcpr
|
||||
description: GPU RB Core Power Reduction clock
|
||||
minItems: 2
|
||||
maxItems: 7
|
||||
|
||||
|
||||
@ -15,7 +15,15 @@ description:
|
||||
Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
|
||||
sub-blocks like DPU display controller, DSI and DP interfaces etc.
|
||||
|
||||
# Do not select this by default, otherwise it is also selected for qcom,mdss
|
||||
# devices.
|
||||
select:
|
||||
false
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
pattern: "^display-subsystem@[0-9a-f]+$"
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
@ -70,7 +78,6 @@ properties:
|
||||
- description: MDSS_CORE reset
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- power-domains
|
||||
|
||||
156
sys/contrib/device-tree/Bindings/display/msm/qcom,mdp5.yaml
Normal file
156
sys/contrib/device-tree/Bindings/display/msm/qcom,mdp5.yaml
Normal file
@ -0,0 +1,156 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/msm/qcom,mdp5.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Adreno/Snapdragon Mobile Display controller (MDP5)
|
||||
|
||||
description:
|
||||
MDP5 display controller found in SoCs like MSM8974, APQ8084, MSM8916, MSM8994
|
||||
and MSM8996.
|
||||
|
||||
maintainers:
|
||||
- Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
||||
- Rob Clark <robdclark@gmail.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- const: qcom,mdp5
|
||||
deprecated: true
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,apq8084-mdp5
|
||||
- qcom,msm8916-mdp5
|
||||
- qcom,msm8917-mdp5
|
||||
- qcom,msm8953-mdp5
|
||||
- qcom,msm8974-mdp5
|
||||
- qcom,msm8976-mdp5
|
||||
- qcom,msm8994-mdp5
|
||||
- qcom,msm8996-mdp5
|
||||
- qcom,sdm630-mdp5
|
||||
- qcom,sdm660-mdp5
|
||||
- const: qcom,mdp5
|
||||
|
||||
$nodename:
|
||||
pattern: '^display-controller@[0-9a-f]+$'
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: mdp_phys
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
minItems: 4
|
||||
maxItems: 7
|
||||
|
||||
clock-names:
|
||||
oneOf:
|
||||
- minItems: 4
|
||||
items:
|
||||
- const: iface
|
||||
- const: bus
|
||||
- const: core
|
||||
- const: vsync
|
||||
- const: lut
|
||||
- const: tbu
|
||||
- const: tbu_rt
|
||||
#MSM8996 has additional iommu clock
|
||||
- items:
|
||||
- const: iface
|
||||
- const: bus
|
||||
- const: core
|
||||
- const: iommu
|
||||
- const: vsync
|
||||
|
||||
interconnects:
|
||||
minItems: 1
|
||||
items:
|
||||
- description: Interconnect path from mdp0 (or a single mdp) port to the data bus
|
||||
- description: Interconnect path from mdp1 port to the data bus
|
||||
- description: Interconnect path from rotator port to the data bus
|
||||
|
||||
interconnect-names:
|
||||
minItems: 1
|
||||
items:
|
||||
- const: mdp0-mem
|
||||
- const: mdp1-mem
|
||||
- const: rotator-mem
|
||||
|
||||
iommus:
|
||||
items:
|
||||
- description: apps SMMU with the Stream-ID mask for Hard-Fail port0
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
operating-points-v2: true
|
||||
opp-table:
|
||||
type: object
|
||||
|
||||
ports:
|
||||
$ref: /schemas/graph.yaml#/properties/ports
|
||||
description: >
|
||||
Contains the list of output ports from DPU device. These ports
|
||||
connect to interfaces that are external to the DPU hardware,
|
||||
such as DSI, DP etc. MDP5 devices support up to 4 ports:
|
||||
one or two DSI ports, HDMI and eDP.
|
||||
|
||||
patternProperties:
|
||||
"^port@[0-3]+$":
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
|
||||
# at least one port is required
|
||||
required:
|
||||
- port@0
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- clocks
|
||||
- clock-names
|
||||
- ports
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,gcc-msm8916.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
display-controller@1a01000 {
|
||||
compatible = "qcom,mdp5";
|
||||
reg = <0x1a01000 0x90000>;
|
||||
reg-names = "mdp_phys";
|
||||
|
||||
interrupt-parent = <&mdss>;
|
||||
interrupts = <0>;
|
||||
|
||||
clocks = <&gcc GCC_MDSS_AHB_CLK>,
|
||||
<&gcc GCC_MDSS_AXI_CLK>,
|
||||
<&gcc GCC_MDSS_MDP_CLK>,
|
||||
<&gcc GCC_MDSS_VSYNC_CLK>;
|
||||
clock-names = "iface",
|
||||
"bus",
|
||||
"core",
|
||||
"vsync";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
endpoint {
|
||||
remote-endpoint = <&dsi0_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
...
|
||||
@ -15,6 +15,9 @@ description:
|
||||
encapsulates sub-blocks like MDP5, DSI, HDMI, eDP, etc.
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
pattern: "^display-subsystem@[0-9a-f]+$"
|
||||
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,mdss
|
||||
@ -44,18 +47,30 @@ properties:
|
||||
The MDSS power domain provided by GCC
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
items:
|
||||
- description: Display abh clock
|
||||
- description: Display axi clock
|
||||
- description: Display vsync clock
|
||||
oneOf:
|
||||
- minItems: 3
|
||||
items:
|
||||
- description: Display abh clock
|
||||
- description: Display axi clock
|
||||
- description: Display vsync clock
|
||||
- description: Display core clock
|
||||
- minItems: 1
|
||||
items:
|
||||
- description: Display abh clock
|
||||
- description: Display core clock
|
||||
|
||||
clock-names:
|
||||
minItems: 1
|
||||
items:
|
||||
- const: iface
|
||||
- const: bus
|
||||
- const: vsync
|
||||
oneOf:
|
||||
- minItems: 3
|
||||
items:
|
||||
- const: iface
|
||||
- const: bus
|
||||
- const: vsync
|
||||
- const: core
|
||||
- minItems: 1
|
||||
items:
|
||||
- const: iface
|
||||
- const: core
|
||||
|
||||
"#address-cells":
|
||||
const: 1
|
||||
@ -84,17 +99,19 @@ required:
|
||||
- ranges
|
||||
|
||||
patternProperties:
|
||||
"^mdp@[1-9a-f][0-9a-f]*$":
|
||||
"^display-controller@[1-9a-f][0-9a-f]*$":
|
||||
type: object
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,mdp5
|
||||
contains:
|
||||
const: qcom,mdp5
|
||||
|
||||
"^dsi@[1-9a-f][0-9a-f]*$":
|
||||
type: object
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,mdss-dsi-ctrl
|
||||
contains:
|
||||
const: qcom,mdss-dsi-ctrl
|
||||
|
||||
"^phy@[1-9a-f][0-9a-f]*$":
|
||||
type: object
|
||||
@ -107,12 +124,6 @@ patternProperties:
|
||||
- qcom,dsi-phy-20nm
|
||||
- qcom,dsi-phy-28nm-hpm
|
||||
- qcom,dsi-phy-28nm-lp
|
||||
|
||||
"^hdmi-phy@[1-9a-f][0-9a-f]*$":
|
||||
type: object
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,hdmi-phy-8084
|
||||
- qcom,hdmi-phy-8660
|
||||
- qcom,hdmi-phy-8960
|
||||
@ -137,7 +148,7 @@ examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,gcc-msm8916.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
mdss@1a00000 {
|
||||
display-subsystem@1a00000 {
|
||||
compatible = "qcom,mdss";
|
||||
reg = <0x1a00000 0x1000>,
|
||||
<0x1ac8000 0x3000>;
|
||||
@ -161,8 +172,8 @@ examples:
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
mdp@1a01000 {
|
||||
compatible = "qcom,mdp5";
|
||||
display-controller@1a01000 {
|
||||
compatible = "qcom,msm8916-mdp5", "qcom,mdp5";
|
||||
reg = <0x01a01000 0x89000>;
|
||||
reg-names = "mdp_phys";
|
||||
|
||||
|
||||
@ -4,7 +4,7 @@
|
||||
$id: http://devicetree.org/schemas/display/msm/qcom,msm8998-dpu.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Display DPU dt properties for MSM8998 target
|
||||
title: Qualcomm Display DPU on MSM8998
|
||||
|
||||
maintainers:
|
||||
- AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
|
||||
@ -13,8 +13,7 @@ $ref: /schemas/display/msm/dpu-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: qcom,msm8998-dpu
|
||||
const: qcom,msm8998-dpu
|
||||
|
||||
reg:
|
||||
items:
|
||||
@ -46,6 +45,13 @@ properties:
|
||||
- const: core
|
||||
- const: vsync
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
|
||||
@ -18,8 +18,7 @@ $ref: /schemas/display/msm/mdss-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: qcom,msm8998-mdss
|
||||
const: qcom,msm8998-mdss
|
||||
|
||||
clocks:
|
||||
items:
|
||||
@ -47,7 +46,9 @@ patternProperties:
|
||||
type: object
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,mdss-dsi-ctrl
|
||||
items:
|
||||
- const: qcom,msm8998-dsi-ctrl
|
||||
- const: qcom,mdss-dsi-ctrl
|
||||
|
||||
"^phy@[0-9a-f]+$":
|
||||
type: object
|
||||
@ -55,6 +56,9 @@ patternProperties:
|
||||
compatible:
|
||||
const: qcom,dsi-phy-10nm-8998
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
@ -126,7 +130,7 @@ examples:
|
||||
};
|
||||
|
||||
dsi@c994000 {
|
||||
compatible = "qcom,mdss-dsi-ctrl";
|
||||
compatible = "qcom,msm8998-dsi-ctrl", "qcom,mdss-dsi-ctrl";
|
||||
reg = <0x0c994000 0x400>;
|
||||
reg-names = "dsi_ctrl";
|
||||
|
||||
@ -196,7 +200,7 @@ examples:
|
||||
};
|
||||
|
||||
dsi@c996000 {
|
||||
compatible = "qcom,mdss-dsi-ctrl";
|
||||
compatible = "qcom,msm8998-dsi-ctrl", "qcom,mdss-dsi-ctrl";
|
||||
reg = <0x0c996000 0x400>;
|
||||
reg-names = "dsi_ctrl";
|
||||
|
||||
|
||||
@ -4,7 +4,7 @@
|
||||
$id: http://devicetree.org/schemas/display/msm/qcom,qcm2290-dpu.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Display DPU dt properties for QCM2290 target
|
||||
title: Qualcomm Display DPU on QCM2290
|
||||
|
||||
maintainers:
|
||||
- Loic Poulain <loic.poulain@linaro.org>
|
||||
@ -13,8 +13,7 @@ $ref: /schemas/display/msm/dpu-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: qcom,qcm2290-dpu
|
||||
const: qcom,qcm2290-dpu
|
||||
|
||||
reg:
|
||||
items:
|
||||
@ -42,6 +41,13 @@ properties:
|
||||
- const: lut
|
||||
- const: vsync
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
|
||||
@ -18,8 +18,7 @@ $ref: /schemas/display/msm/mdss-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: qcom,qcm2290-mdss
|
||||
const: qcom,qcm2290-mdss
|
||||
|
||||
clocks:
|
||||
items:
|
||||
@ -61,6 +60,9 @@ patternProperties:
|
||||
compatible:
|
||||
const: qcom,dsi-phy-14nm-2290
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
|
||||
@ -4,7 +4,7 @@
|
||||
$id: http://devicetree.org/schemas/display/msm/qcom,sc7180-dpu.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Display DPU dt properties for SC7180 target
|
||||
title: Qualcomm Display DPU on SC7180
|
||||
|
||||
maintainers:
|
||||
- Krishna Manikandan <quic_mkrishn@quicinc.com>
|
||||
@ -13,8 +13,7 @@ $ref: /schemas/display/msm/dpu-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: qcom,sc7180-dpu
|
||||
const: qcom,sc7180-dpu
|
||||
|
||||
reg:
|
||||
items:
|
||||
@ -44,6 +43,13 @@ properties:
|
||||
- const: core
|
||||
- const: vsync
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
|
||||
@ -18,8 +18,7 @@ $ref: /schemas/display/msm/mdss-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: qcom,sc7180-mdss
|
||||
const: qcom,sc7180-mdss
|
||||
|
||||
clocks:
|
||||
items:
|
||||
@ -59,7 +58,9 @@ patternProperties:
|
||||
type: object
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,mdss-dsi-ctrl
|
||||
items:
|
||||
- const: qcom,sc7180-dsi-ctrl
|
||||
- const: qcom,mdss-dsi-ctrl
|
||||
|
||||
"^phy@[0-9a-f]+$":
|
||||
type: object
|
||||
@ -67,6 +68,9 @@ patternProperties:
|
||||
compatible:
|
||||
const: qcom,dsi-phy-10nm
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
@ -142,7 +146,7 @@ examples:
|
||||
};
|
||||
|
||||
dsi@ae94000 {
|
||||
compatible = "qcom,mdss-dsi-ctrl";
|
||||
compatible = "qcom,sc7180-dsi-ctrl", "qcom,mdss-dsi-ctrl";
|
||||
reg = <0x0ae94000 0x400>;
|
||||
reg-names = "dsi_ctrl";
|
||||
|
||||
|
||||
@ -4,7 +4,7 @@
|
||||
$id: http://devicetree.org/schemas/display/msm/qcom,sc7280-dpu.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Display DPU dt properties for SC7280
|
||||
title: Qualcomm Display DPU on SC7280
|
||||
|
||||
maintainers:
|
||||
- Krishna Manikandan <quic_mkrishn@quicinc.com>
|
||||
@ -43,6 +43,13 @@ properties:
|
||||
- const: core
|
||||
- const: vsync
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
|
||||
@ -58,7 +58,9 @@ patternProperties:
|
||||
type: object
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,mdss-dsi-ctrl
|
||||
items:
|
||||
- const: qcom,sc7280-dsi-ctrl
|
||||
- const: qcom,mdss-dsi-ctrl
|
||||
|
||||
"^edp@[0-9a-f]+$":
|
||||
type: object
|
||||
@ -74,6 +76,9 @@ patternProperties:
|
||||
- qcom,sc7280-dsi-phy-7nm
|
||||
- qcom,sc7280-edp-phy
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
@ -162,7 +167,7 @@ examples:
|
||||
};
|
||||
|
||||
dsi@ae94000 {
|
||||
compatible = "qcom,mdss-dsi-ctrl";
|
||||
compatible = "qcom,sc7280-dsi-ctrl", "qcom,mdss-dsi-ctrl";
|
||||
reg = <0x0ae94000 0x400>;
|
||||
reg-names = "dsi_ctrl";
|
||||
|
||||
|
||||
@ -0,0 +1,122 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/msm/qcom,sc8280xp-dpu.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm SC8280XP Display Processing Unit
|
||||
|
||||
maintainers:
|
||||
- Bjorn Andersson <andersson@kernel.org>
|
||||
|
||||
description:
|
||||
Device tree bindings for SC8280XP Display Processing Unit.
|
||||
|
||||
$ref: /schemas/display/msm/dpu-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sc8280xp-dpu
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: Address offset and size for mdp register set
|
||||
- description: Address offset and size for vbif register set
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: mdp
|
||||
- const: vbif
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Display hf axi clock
|
||||
- description: Display sf axi clock
|
||||
- description: Display ahb clock
|
||||
- description: Display lut clock
|
||||
- description: Display core clock
|
||||
- description: Display vsync clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: bus
|
||||
- const: nrt_bus
|
||||
- const: iface
|
||||
- const: lut
|
||||
- const: core
|
||||
- const: vsync
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,dispcc-sc8280xp.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interconnect/qcom,sc8280xp.h>
|
||||
#include <dt-bindings/power/qcom-rpmpd.h>
|
||||
|
||||
display-controller@ae01000 {
|
||||
compatible = "qcom,sc8280xp-dpu";
|
||||
reg = <0x0ae01000 0x8f000>,
|
||||
<0x0aeb0000 0x2008>;
|
||||
reg-names = "mdp", "vbif";
|
||||
|
||||
clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
|
||||
<&gcc GCC_DISP_SF_AXI_CLK>,
|
||||
<&dispcc0 DISP_CC_MDSS_AHB_CLK>,
|
||||
<&dispcc0 DISP_CC_MDSS_MDP_LUT_CLK>,
|
||||
<&dispcc0 DISP_CC_MDSS_MDP_CLK>,
|
||||
<&dispcc0 DISP_CC_MDSS_VSYNC_CLK>;
|
||||
clock-names = "bus",
|
||||
"nrt_bus",
|
||||
"iface",
|
||||
"lut",
|
||||
"core",
|
||||
"vsync";
|
||||
|
||||
assigned-clocks = <&dispcc0 DISP_CC_MDSS_MDP_CLK>,
|
||||
<&dispcc0 DISP_CC_MDSS_VSYNC_CLK>;
|
||||
assigned-clock-rates = <460000000>,
|
||||
<19200000>;
|
||||
|
||||
operating-points-v2 = <&mdp_opp_table>;
|
||||
power-domains = <&rpmhpd SC8280XP_MMCX>;
|
||||
|
||||
interrupt-parent = <&mdss0>;
|
||||
interrupts = <0>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
endpoint {
|
||||
remote-endpoint = <&mdss0_dp0_in>;
|
||||
};
|
||||
};
|
||||
|
||||
port@4 {
|
||||
reg = <4>;
|
||||
endpoint {
|
||||
remote-endpoint = <&mdss0_dp1_in>;
|
||||
};
|
||||
};
|
||||
|
||||
port@5 {
|
||||
reg = <5>;
|
||||
endpoint {
|
||||
remote-endpoint = <&mdss0_dp3_in>;
|
||||
};
|
||||
};
|
||||
|
||||
port@6 {
|
||||
reg = <6>;
|
||||
endpoint {
|
||||
remote-endpoint = <&mdss0_dp2_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
...
|
||||
@ -0,0 +1,151 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/msm/qcom,sc8280xp-mdss.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm SC8280XP Mobile Display Subsystem
|
||||
|
||||
maintainers:
|
||||
- Bjorn Andersson <andersson@kernel.org>
|
||||
|
||||
description:
|
||||
Device tree bindings for MSM Mobile Display Subsystem (MDSS) that encapsulates
|
||||
sub-blocks like DPU display controller, DSI and DP interfaces etc.
|
||||
|
||||
$ref: /schemas/display/msm/mdss-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sc8280xp-mdss
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Display AHB clock from gcc
|
||||
- description: Display AHB clock from dispcc
|
||||
- description: Display core clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: iface
|
||||
- const: ahb
|
||||
- const: core
|
||||
|
||||
patternProperties:
|
||||
"^display-controller@[0-9a-f]+$":
|
||||
type: object
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sc8280xp-dpu
|
||||
|
||||
"^displayport-controller@[0-9a-f]+$":
|
||||
type: object
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,sc8280xp-dp
|
||||
- qcom,sc8280xp-edp
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,dispcc-sc8280xp.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interconnect/qcom,sc8280xp.h>
|
||||
#include <dt-bindings/power/qcom-rpmpd.h>
|
||||
|
||||
display-subsystem@ae00000 {
|
||||
compatible = "qcom,sc8280xp-mdss";
|
||||
reg = <0x0ae00000 0x1000>;
|
||||
reg-names = "mdss";
|
||||
|
||||
power-domains = <&dispcc0 MDSS_GDSC>;
|
||||
|
||||
clocks = <&gcc GCC_DISP_AHB_CLK>,
|
||||
<&dispcc0 DISP_CC_MDSS_AHB_CLK>,
|
||||
<&dispcc0 DISP_CC_MDSS_MDP_CLK>;
|
||||
clock-names = "iface",
|
||||
"ahb",
|
||||
"core";
|
||||
|
||||
resets = <&dispcc0 DISP_CC_MDSS_CORE_BCR>;
|
||||
|
||||
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>,
|
||||
<&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>;
|
||||
interconnect-names = "mdp0-mem", "mdp1-mem";
|
||||
|
||||
iommus = <&apps_smmu 0x1000 0x402>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
display-controller@ae01000 {
|
||||
compatible = "qcom,sc8280xp-dpu";
|
||||
reg = <0x0ae01000 0x8f000>,
|
||||
<0x0aeb0000 0x2008>;
|
||||
reg-names = "mdp", "vbif";
|
||||
|
||||
clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
|
||||
<&gcc GCC_DISP_SF_AXI_CLK>,
|
||||
<&dispcc0 DISP_CC_MDSS_AHB_CLK>,
|
||||
<&dispcc0 DISP_CC_MDSS_MDP_LUT_CLK>,
|
||||
<&dispcc0 DISP_CC_MDSS_MDP_CLK>,
|
||||
<&dispcc0 DISP_CC_MDSS_VSYNC_CLK>;
|
||||
clock-names = "bus",
|
||||
"nrt_bus",
|
||||
"iface",
|
||||
"lut",
|
||||
"core",
|
||||
"vsync";
|
||||
|
||||
assigned-clocks = <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>;
|
||||
assigned-clock-rates = <19200000>;
|
||||
|
||||
operating-points-v2 = <&mdss0_mdp_opp_table>;
|
||||
power-domains = <&rpmhpd SC8280XP_MMCX>;
|
||||
|
||||
interrupt-parent = <&mdss0>;
|
||||
interrupts = <0>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
endpoint {
|
||||
remote-endpoint = <&mdss0_dp0_in>;
|
||||
};
|
||||
};
|
||||
|
||||
port@4 {
|
||||
reg = <4>;
|
||||
endpoint {
|
||||
remote-endpoint = <&mdss0_dp1_in>;
|
||||
};
|
||||
};
|
||||
|
||||
port@5 {
|
||||
reg = <5>;
|
||||
endpoint {
|
||||
remote-endpoint = <&mdss0_dp3_in>;
|
||||
};
|
||||
};
|
||||
|
||||
port@6 {
|
||||
reg = <6>;
|
||||
endpoint {
|
||||
remote-endpoint = <&mdss0_dp2_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
...
|
||||
@ -4,7 +4,7 @@
|
||||
$id: http://devicetree.org/schemas/display/msm/qcom,sdm845-dpu.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Display DPU dt properties for SDM845 target
|
||||
title: Qualcomm Display DPU on SDM845
|
||||
|
||||
maintainers:
|
||||
- Krishna Manikandan <quic_mkrishn@quicinc.com>
|
||||
@ -13,8 +13,7 @@ $ref: /schemas/display/msm/dpu-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: qcom,sdm845-dpu
|
||||
const: qcom,sdm845-dpu
|
||||
|
||||
reg:
|
||||
items:
|
||||
@ -42,6 +41,13 @@ properties:
|
||||
- const: core
|
||||
- const: vsync
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
|
||||
@ -18,8 +18,7 @@ $ref: /schemas/display/msm/mdss-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: qcom,sdm845-mdss
|
||||
const: qcom,sdm845-mdss
|
||||
|
||||
clocks:
|
||||
items:
|
||||
@ -47,11 +46,19 @@ patternProperties:
|
||||
compatible:
|
||||
const: qcom,sdm845-dpu
|
||||
|
||||
"^displayport-controller@[0-9a-f]+$":
|
||||
type: object
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sdm845-dp
|
||||
|
||||
"^dsi@[0-9a-f]+$":
|
||||
type: object
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,mdss-dsi-ctrl
|
||||
items:
|
||||
- const: qcom,sdm845-dsi-ctrl
|
||||
- const: qcom,mdss-dsi-ctrl
|
||||
|
||||
"^phy@[0-9a-f]+$":
|
||||
type: object
|
||||
@ -59,6 +66,9 @@ patternProperties:
|
||||
compatible:
|
||||
const: qcom,dsi-phy-10nm
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
@ -128,7 +138,7 @@ examples:
|
||||
};
|
||||
|
||||
dsi@ae94000 {
|
||||
compatible = "qcom,mdss-dsi-ctrl";
|
||||
compatible = "qcom,sdm845-dsi-ctrl", "qcom,mdss-dsi-ctrl";
|
||||
reg = <0x0ae94000 0x400>;
|
||||
reg-names = "dsi_ctrl";
|
||||
|
||||
@ -198,7 +208,7 @@ examples:
|
||||
};
|
||||
|
||||
dsi@ae96000 {
|
||||
compatible = "qcom,mdss-dsi-ctrl";
|
||||
compatible = "qcom,sdm845-dsi-ctrl", "qcom,mdss-dsi-ctrl";
|
||||
reg = <0x0ae96000 0x400>;
|
||||
reg-names = "dsi_ctrl";
|
||||
|
||||
|
||||
@ -4,7 +4,7 @@
|
||||
$id: http://devicetree.org/schemas/display/msm/qcom,sm6115-dpu.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Display DPU dt properties for SM6115 target
|
||||
title: Qualcomm Display DPU on SM6115
|
||||
|
||||
maintainers:
|
||||
- Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
||||
@ -13,8 +13,7 @@ $ref: /schemas/display/msm/dpu-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: qcom,sm6115-dpu
|
||||
const: qcom,sm6115-dpu
|
||||
|
||||
reg:
|
||||
items:
|
||||
|
||||
@ -18,8 +18,7 @@ $ref: /schemas/display/msm/mdss-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: qcom,sm6115-mdss
|
||||
const: qcom,sm6115-mdss
|
||||
|
||||
clocks:
|
||||
items:
|
||||
|
||||
@ -0,0 +1,92 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/msm/qcom,sm8150-dpu.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm SM8150 Display DPU
|
||||
|
||||
maintainers:
|
||||
- Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
||||
|
||||
$ref: /schemas/display/msm/dpu-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sm8150-dpu
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: Address offset and size for mdp register set
|
||||
- description: Address offset and size for vbif register set
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: mdp
|
||||
- const: vbif
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Display ahb clock
|
||||
- description: Display hf axi clock
|
||||
- description: Display core clock
|
||||
- description: Display vsync clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: iface
|
||||
- const: bus
|
||||
- const: core
|
||||
- const: vsync
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,dispcc-sm8150.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-sm8150.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interconnect/qcom,sm8150.h>
|
||||
#include <dt-bindings/power/qcom-rpmpd.h>
|
||||
|
||||
display-controller@ae01000 {
|
||||
compatible = "qcom,sm8150-dpu";
|
||||
reg = <0x0ae01000 0x8f000>,
|
||||
<0x0aeb0000 0x2008>;
|
||||
reg-names = "mdp", "vbif";
|
||||
|
||||
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&gcc GCC_DISP_HF_AXI_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_MDP_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
|
||||
clock-names = "iface", "bus", "core", "vsync";
|
||||
|
||||
assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
|
||||
assigned-clock-rates = <19200000>;
|
||||
|
||||
operating-points-v2 = <&mdp_opp_table>;
|
||||
power-domains = <&rpmhpd SM8150_MMCX>;
|
||||
|
||||
interrupt-parent = <&mdss>;
|
||||
interrupts = <0>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
endpoint {
|
||||
remote-endpoint = <&dsi0_in>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
endpoint {
|
||||
remote-endpoint = <&dsi1_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
...
|
||||
@ -0,0 +1,332 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/msm/qcom,sm8150-mdss.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm SM8150 Display MDSS
|
||||
|
||||
maintainers:
|
||||
- Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
||||
|
||||
description:
|
||||
Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
|
||||
sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
|
||||
bindings of MDSS are mentioned for SM8150 target.
|
||||
|
||||
$ref: /schemas/display/msm/mdss-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: qcom,sm8150-mdss
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Display AHB clock from gcc
|
||||
- description: Display hf axi clock
|
||||
- description: Display sf axi clock
|
||||
- description: Display core clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: iface
|
||||
- const: bus
|
||||
- const: nrt_bus
|
||||
- const: core
|
||||
|
||||
iommus:
|
||||
maxItems: 1
|
||||
|
||||
interconnects:
|
||||
maxItems: 2
|
||||
|
||||
interconnect-names:
|
||||
maxItems: 2
|
||||
|
||||
patternProperties:
|
||||
"^display-controller@[0-9a-f]+$":
|
||||
type: object
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sm8150-dpu
|
||||
|
||||
"^dsi@[0-9a-f]+$":
|
||||
type: object
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: qcom,sm8150-dsi-ctrl
|
||||
- const: qcom,mdss-dsi-ctrl
|
||||
|
||||
"^phy@[0-9a-f]+$":
|
||||
type: object
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,dsi-phy-7nm
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,dispcc-sm8150.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-sm8150.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interconnect/qcom,sm8150.h>
|
||||
#include <dt-bindings/power/qcom-rpmpd.h>
|
||||
|
||||
display-subsystem@ae00000 {
|
||||
compatible = "qcom,sm8150-mdss";
|
||||
reg = <0x0ae00000 0x1000>;
|
||||
reg-names = "mdss";
|
||||
|
||||
interconnects = <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>,
|
||||
<&mmss_noc MASTER_MDP_PORT1 &mc_virt SLAVE_EBI_CH0>;
|
||||
interconnect-names = "mdp0-mem", "mdp1-mem";
|
||||
|
||||
power-domains = <&dispcc MDSS_GDSC>;
|
||||
|
||||
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&gcc GCC_DISP_HF_AXI_CLK>,
|
||||
<&gcc GCC_DISP_SF_AXI_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_MDP_CLK>;
|
||||
clock-names = "iface", "bus", "nrt_bus", "core";
|
||||
|
||||
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
iommus = <&apps_smmu 0x800 0x420>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
display-controller@ae01000 {
|
||||
compatible = "qcom,sm8150-dpu";
|
||||
reg = <0x0ae01000 0x8f000>,
|
||||
<0x0aeb0000 0x2008>;
|
||||
reg-names = "mdp", "vbif";
|
||||
|
||||
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&gcc GCC_DISP_HF_AXI_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_MDP_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
|
||||
clock-names = "iface", "bus", "core", "vsync";
|
||||
|
||||
assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
|
||||
assigned-clock-rates = <19200000>;
|
||||
|
||||
operating-points-v2 = <&mdp_opp_table>;
|
||||
power-domains = <&rpmhpd SM8150_MMCX>;
|
||||
|
||||
interrupt-parent = <&mdss>;
|
||||
interrupts = <0>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
dpu_intf1_out: endpoint {
|
||||
remote-endpoint = <&dsi0_in>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
dpu_intf2_out: endpoint {
|
||||
remote-endpoint = <&dsi1_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
mdp_opp_table: opp-table {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
opp-171428571 {
|
||||
opp-hz = /bits/ 64 <171428571>;
|
||||
required-opps = <&rpmhpd_opp_low_svs>;
|
||||
};
|
||||
|
||||
opp-300000000 {
|
||||
opp-hz = /bits/ 64 <300000000>;
|
||||
required-opps = <&rpmhpd_opp_svs>;
|
||||
};
|
||||
|
||||
opp-345000000 {
|
||||
opp-hz = /bits/ 64 <345000000>;
|
||||
required-opps = <&rpmhpd_opp_svs_l1>;
|
||||
};
|
||||
|
||||
opp-460000000 {
|
||||
opp-hz = /bits/ 64 <460000000>;
|
||||
required-opps = <&rpmhpd_opp_nom>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
dsi@ae94000 {
|
||||
compatible = "qcom,sm8150-dsi-ctrl", "qcom,mdss-dsi-ctrl";
|
||||
reg = <0x0ae94000 0x400>;
|
||||
reg-names = "dsi_ctrl";
|
||||
|
||||
interrupt-parent = <&mdss>;
|
||||
interrupts = <4>;
|
||||
|
||||
clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_PCLK0_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_ESC0_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&gcc GCC_DISP_HF_AXI_CLK>;
|
||||
clock-names = "byte",
|
||||
"byte_intf",
|
||||
"pixel",
|
||||
"core",
|
||||
"iface",
|
||||
"bus";
|
||||
|
||||
assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
|
||||
<&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
|
||||
assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
|
||||
|
||||
operating-points-v2 = <&dsi_opp_table>;
|
||||
power-domains = <&rpmhpd SM8150_MMCX>;
|
||||
|
||||
phys = <&dsi0_phy>;
|
||||
phy-names = "dsi";
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
dsi0_in: endpoint {
|
||||
remote-endpoint = <&dpu_intf1_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
dsi0_out: endpoint {
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
dsi_opp_table: opp-table {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
opp-187500000 {
|
||||
opp-hz = /bits/ 64 <187500000>;
|
||||
required-opps = <&rpmhpd_opp_low_svs>;
|
||||
};
|
||||
|
||||
opp-300000000 {
|
||||
opp-hz = /bits/ 64 <300000000>;
|
||||
required-opps = <&rpmhpd_opp_svs>;
|
||||
};
|
||||
|
||||
opp-358000000 {
|
||||
opp-hz = /bits/ 64 <358000000>;
|
||||
required-opps = <&rpmhpd_opp_svs_l1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
dsi0_phy: phy@ae94400 {
|
||||
compatible = "qcom,dsi-phy-7nm";
|
||||
reg = <0x0ae94400 0x200>,
|
||||
<0x0ae94600 0x280>,
|
||||
<0x0ae94900 0x260>;
|
||||
reg-names = "dsi_phy",
|
||||
"dsi_phy_lane",
|
||||
"dsi_pll";
|
||||
|
||||
#clock-cells = <1>;
|
||||
#phy-cells = <0>;
|
||||
|
||||
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK>;
|
||||
clock-names = "iface", "ref";
|
||||
vdds-supply = <&vreg_dsi_phy>;
|
||||
};
|
||||
|
||||
dsi@ae96000 {
|
||||
compatible = "qcom,sm8150-dsi-ctrl", "qcom,mdss-dsi-ctrl";
|
||||
reg = <0x0ae96000 0x400>;
|
||||
reg-names = "dsi_ctrl";
|
||||
|
||||
interrupt-parent = <&mdss>;
|
||||
interrupts = <5>;
|
||||
|
||||
clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_PCLK1_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_ESC1_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&gcc GCC_DISP_HF_AXI_CLK>;
|
||||
clock-names = "byte",
|
||||
"byte_intf",
|
||||
"pixel",
|
||||
"core",
|
||||
"iface",
|
||||
"bus";
|
||||
|
||||
assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
|
||||
<&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
|
||||
assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
|
||||
|
||||
operating-points-v2 = <&dsi_opp_table>;
|
||||
power-domains = <&rpmhpd SM8150_MMCX>;
|
||||
|
||||
phys = <&dsi1_phy>;
|
||||
phy-names = "dsi";
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
dsi1_in: endpoint {
|
||||
remote-endpoint = <&dpu_intf2_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
dsi1_out: endpoint {
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
dsi1_phy: phy@ae96400 {
|
||||
compatible = "qcom,dsi-phy-7nm";
|
||||
reg = <0x0ae96400 0x200>,
|
||||
<0x0ae96600 0x280>,
|
||||
<0x0ae96900 0x260>;
|
||||
reg-names = "dsi_phy",
|
||||
"dsi_phy_lane",
|
||||
"dsi_pll";
|
||||
|
||||
#clock-cells = <1>;
|
||||
#phy-cells = <0>;
|
||||
|
||||
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK>;
|
||||
clock-names = "iface", "ref";
|
||||
vdds-supply = <&vreg_dsi_phy>;
|
||||
};
|
||||
};
|
||||
...
|
||||
@ -39,6 +39,13 @@ properties:
|
||||
- const: core
|
||||
- const: vsync
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
|
||||
@ -18,8 +18,7 @@ $ref: /schemas/display/msm/mdss-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: qcom,sm8250-mdss
|
||||
const: qcom,sm8250-mdss
|
||||
|
||||
clocks:
|
||||
items:
|
||||
@ -55,7 +54,9 @@ patternProperties:
|
||||
type: object
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,mdss-dsi-ctrl
|
||||
items:
|
||||
- const: qcom,sm8250-dsi-ctrl
|
||||
- const: qcom,mdss-dsi-ctrl
|
||||
|
||||
"^phy@[0-9a-f]+$":
|
||||
type: object
|
||||
@ -63,6 +64,9 @@ patternProperties:
|
||||
compatible:
|
||||
const: qcom,dsi-phy-7nm
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
@ -167,7 +171,7 @@ examples:
|
||||
};
|
||||
|
||||
dsi@ae94000 {
|
||||
compatible = "qcom,mdss-dsi-ctrl";
|
||||
compatible = "qcom,sm8250-dsi-ctrl", "qcom,mdss-dsi-ctrl";
|
||||
reg = <0x0ae94000 0x400>;
|
||||
reg-names = "dsi_ctrl";
|
||||
|
||||
@ -257,7 +261,7 @@ examples:
|
||||
};
|
||||
|
||||
dsi@ae96000 {
|
||||
compatible = "qcom,mdss-dsi-ctrl";
|
||||
compatible = "qcom,sm8250-dsi-ctrl", "qcom,mdss-dsi-ctrl";
|
||||
reg = <0x0ae96000 0x400>;
|
||||
reg-names = "dsi_ctrl";
|
||||
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user