Import DTS from Linux 5.2
This commit is contained in:
parent
0db636cb5e
commit
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Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/vendor/device-tree/dist/; revision=352854 svn path=/vendor/device-tree/5.2/; revision=352855; tag=vendor/device-tree/5.2
4
.gitignore
vendored
Normal file
4
.gitignore
vendored
Normal file
@ -0,0 +1,4 @@
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.*
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!.gitignore
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*.dtb
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@ -5,7 +5,7 @@ DT_MK_SCHEMA ?= dt-mk-schema
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DT_MK_SCHEMA_FLAGS := $(if $(DT_SCHEMA_FILES), -u)
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quiet_cmd_chk_binding = CHKDT $(patsubst $(srctree)/%,%,$<)
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cmd_chk_binding = $(DT_DOC_CHECKER) $< ; \
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cmd_chk_binding = $(DT_DOC_CHECKER) -u $(srctree)/$(src) $< ; \
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$(DT_EXTRACT_EX) $< > $@
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$(obj)/%.example.dts: $(src)/%.yaml FORCE
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@ -11,3 +11,15 @@ Example:
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reg = <0xffd08000 0x1000>;
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cpu1-start-addr = <0xffd080c4>;
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};
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ARM64 - Stratix10
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Required properties:
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- compatible : "altr,sys-mgr-s10"
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- reg : Should contain 1 register range(address and length)
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for system manager register.
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Example:
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sysmgr@ffd12000 {
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compatible = "altr,sys-mgr-s10";
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reg = <0xffd12000 0x228>;
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};
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@ -110,6 +110,7 @@ Board compatible values (alphabetically, grouped by SoC):
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- "amlogic,u200" (Meson g12a s905d2)
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- "amediatech,x96-max" (Meson g12a s905x2)
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- "seirobotics,sei510" (Meson g12a s905x2)
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Amlogic Meson Firmware registers Interface
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------------------------------------------
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@ -216,7 +216,7 @@ Example:
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#size-cells = <0>;
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A57_0: cpu@0 {
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compatible = "arm,cortex-a57","arm,armv8";
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compatible = "arm,cortex-a57";
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reg = <0x0 0x0>;
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device_type = "cpu";
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enable-method = "psci";
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@ -225,7 +225,7 @@ Example:
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.....
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A53_0: cpu@100 {
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compatible = "arm,cortex-a53","arm,armv8";
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compatible = "arm,cortex-a53";
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reg = <0x0 0x100>;
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device_type = "cpu";
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enable-method = "psci";
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@ -25,6 +25,7 @@ compatible: must be one of:
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o "atmel,at91sam9n12"
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o "atmel,at91sam9rl"
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o "atmel,at91sam9xe"
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o "microchip,sam9x60"
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* "atmel,sama5" for SoCs using a Cortex-A5, shall be extended with the specific
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SoC family:
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o "atmel,sama5d2" shall be extended with the specific SoC compatible:
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@ -84,7 +84,7 @@ SHDWC SAMA5D2-Compatible Shutdown Controller
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1) shdwc node
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required properties:
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- compatible: should be "atmel,sama5d2-shdwc".
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- compatible: should be "atmel,sama5d2-shdwc" or "microchip,sam9x60-shdwc".
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- reg: should contain registers location and length
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- clocks: phandle to input clock.
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- #address-cells: should be one. The cell is the wake-up input index.
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@ -96,6 +96,9 @@ optional properties:
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microseconds. It's usually a board-related property.
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- atmel,wakeup-rtc-timer: boolean to enable Real-Time Clock wake-up.
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optional microchip,sam9x60-shdwc properties:
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- atmel,wakeup-rtt-timer: boolean to enable Real-time Timer Wake-up.
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The node contains child nodes for each wake-up input that the platform uses.
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2) input nodes
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@ -8,7 +8,8 @@ through the intermediate links connecting the source to the currently selected
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sink. Each CoreSight component device should use these properties to describe
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its hardware characteristcs.
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* Required properties for all components *except* non-configurable replicators:
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* Required properties for all components *except* non-configurable replicators
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and non-configurable funnels:
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* compatible: These have to be supplemented with "arm,primecell" as
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drivers are using the AMBA bus interface. Possible values include:
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@ -24,8 +25,10 @@ its hardware characteristcs.
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discovered at boot time when the device is probed.
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"arm,coresight-tmc", "arm,primecell";
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- Trace Funnel:
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"arm,coresight-funnel", "arm,primecell";
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- Trace Programmable Funnel:
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"arm,coresight-dynamic-funnel", "arm,primecell";
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"arm,coresight-funnel", "arm,primecell"; (OBSOLETE. For
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backward compatibility and will be removed)
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- Embedded Trace Macrocell (version 3.x) and
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Program Flow Trace Macrocell:
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@ -65,11 +68,17 @@ its hardware characteristcs.
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"stm-stimulus-base", each corresponding to the areas defined in "reg".
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* Required properties for devices that don't show up on the AMBA bus, such as
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non-configurable replicators:
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non-configurable replicators and non-configurable funnels:
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* compatible: Currently supported value is (note the absence of the
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AMBA markee):
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- "arm,coresight-replicator"
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- Coresight Non-configurable Replicator:
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"arm,coresight-static-replicator";
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"arm,coresight-replicator"; (OBSOLETE. For backward
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compatibility and will be removed)
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- Coresight Non-configurable Funnel:
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"arm,coresight-static-funnel";
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* port or ports: see "Graph bindings for Coresight" below.
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@ -169,7 +178,7 @@ Example:
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/* non-configurable replicators don't show up on the
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* AMBA bus. As such no need to add "arm,primecell".
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*/
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compatible = "arm,coresight-replicator";
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compatible = "arm,coresight-static-replicator";
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out-ports {
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#address-cells = <1>;
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@ -200,8 +209,45 @@ Example:
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};
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};
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funnel {
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/*
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* non-configurable funnel don't show up on the AMBA
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* bus. As such no need to add "arm,primecell".
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*/
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compatible = "arm,coresight-static-funnel";
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clocks = <&crg_ctrl HI3660_PCLK>;
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clock-names = "apb_pclk";
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out-ports {
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port {
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combo_funnel_out: endpoint {
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remote-endpoint = <&top_funnel_in>;
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};
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};
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};
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in-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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combo_funnel_in0: endpoint {
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remote-endpoint = <&cluster0_etf_out>;
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};
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};
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port@1 {
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reg = <1>;
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combo_funnel_in1: endpoint {
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remote-endpoint = <&cluster1_etf_out>;
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};
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};
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};
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};
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funnel@20040000 {
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compatible = "arm,coresight-funnel", "arm,primecell";
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compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
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reg = <0 0x20040000 0 0x1000>;
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clocks = <&oscclk6a>;
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@ -118,7 +118,7 @@ cpus {
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};
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A57_0: cpu@0 {
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compatible = "arm,cortex-a57","arm,armv8";
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compatible = "arm,cortex-a57";
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reg = <0x0 0x0>;
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device_type = "cpu";
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enable-method = "psci";
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@ -129,7 +129,7 @@ cpus {
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};
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A57_1: cpu@1 {
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compatible = "arm,cortex-a57","arm,armv8";
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compatible = "arm,cortex-a57";
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reg = <0x0 0x1>;
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device_type = "cpu";
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enable-method = "psci";
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@ -140,7 +140,7 @@ cpus {
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};
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A53_0: cpu@100 {
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compatible = "arm,cortex-a53","arm,armv8";
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compatible = "arm,cortex-a53";
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reg = <0x0 0x100>;
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device_type = "cpu";
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enable-method = "psci";
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@ -151,7 +151,7 @@ cpus {
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};
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A53_1: cpu@101 {
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compatible = "arm,cortex-a53","arm,armv8";
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compatible = "arm,cortex-a53";
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reg = <0x0 0x101>;
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device_type = "cpu";
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enable-method = "psci";
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@ -162,7 +162,7 @@ cpus {
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};
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A53_2: cpu@102 {
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compatible = "arm,cortex-a53","arm,armv8";
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compatible = "arm,cortex-a53";
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reg = <0x0 0x102>;
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device_type = "cpu";
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enable-method = "psci";
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@ -173,7 +173,7 @@ cpus {
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};
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A53_3: cpu@103 {
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compatible = "arm,cortex-a53","arm,armv8";
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compatible = "arm,cortex-a53";
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reg = <0x0 0x103>;
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device_type = "cpu";
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enable-method = "psci";
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@ -67,6 +67,7 @@ properties:
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patternProperties:
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'^cpu@[0-9a-f]+$':
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type: object
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properties:
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device_type:
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const: cpu
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@ -22,9 +22,11 @@ Required properties:
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-------------------
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- compatible: should be "fsl,imx-scu".
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- mbox-names: should include "tx0", "tx1", "tx2", "tx3",
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"rx0", "rx1", "rx2", "rx3".
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- mboxes: List of phandle of 4 MU channels for tx and 4 MU channels
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for rx. All 8 MU channels must be in the same MU instance.
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"rx0", "rx1", "rx2", "rx3";
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include "gip3" if want to support general MU interrupt.
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- mboxes: List of phandle of 4 MU channels for tx, 4 MU channels for
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rx, and 1 optional MU channel for general interrupt.
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All MU channels must be in the same MU instance.
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Cross instances are not allowed. The MU instance can only
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be one of LSIO MU0~M4 for imx8qxp and imx8qm. Users need
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to make sure use the one which is not conflict with other
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@ -34,6 +36,7 @@ Required properties:
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Channel 1 must be "tx1" or "rx1".
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Channel 2 must be "tx2" or "rx2".
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Channel 3 must be "tx3" or "rx3".
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General interrupt rx channel must be "gip3".
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e.g.
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mboxes = <&lsio_mu1 0 0
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&lsio_mu1 0 1
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@ -42,10 +45,18 @@ Required properties:
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&lsio_mu1 1 0
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&lsio_mu1 1 1
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&lsio_mu1 1 2
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&lsio_mu1 1 3>;
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&lsio_mu1 1 3
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&lsio_mu1 3 3>;
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See Documentation/devicetree/bindings/mailbox/fsl,mu.txt
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for detailed mailbox binding.
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Note: Each mu which supports general interrupt should have an alias correctly
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numbered in "aliases" node.
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e.g.
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aliases {
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mu1 = &lsio_mu1;
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};
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i.MX SCU Client Device Node:
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============================================================
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@ -124,6 +135,10 @@ Required properties:
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Example (imx8qxp):
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-------------
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aliases {
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mu1 = &lsio_mu1;
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};
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lsio_mu1: mailbox@5d1c0000 {
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...
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#mbox-cells = <2>;
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@ -133,7 +148,8 @@ firmware {
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scu {
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compatible = "fsl,imx-scu";
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mbox-names = "tx0", "tx1", "tx2", "tx3",
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"rx0", "rx1", "rx2", "rx3";
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"rx0", "rx1", "rx2", "rx3",
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"gip3";
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mboxes = <&lsio_mu1 0 0
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&lsio_mu1 0 1
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&lsio_mu1 0 2
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@ -141,7 +157,8 @@ firmware {
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&lsio_mu1 1 0
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&lsio_mu1 1 1
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&lsio_mu1 1 2
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&lsio_mu1 1 3>;
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&lsio_mu1 1 3
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&lsio_mu1 3 3>;
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clk: clk {
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compatible = "fsl,imx8qxp-clk", "fsl,scu-clk";
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@ -51,6 +51,13 @@ properties:
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- const: i2se,duckbill-2
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- const: fsl,imx28
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- description: i.MX50 based Boards
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items:
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- enum:
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- fsl,imx50-evk
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- kobo,aura
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- const: fsl,imx50
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- description: i.MX51 Babbage Board
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items:
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- enum:
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@ -67,6 +74,7 @@ properties:
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- fsl,imx53-evk
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- fsl,imx53-qsb
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- fsl,imx53-smd
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- menlo,m53menlo
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- const: fsl,imx53
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- description: i.MX6Q based Boards
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@ -90,6 +98,7 @@ properties:
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- description: i.MX6DL based Boards
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items:
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- enum:
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- eckelmann,imx6dl-ci4x10
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- fsl,imx6dl-sabreauto # i.MX6 DualLite/Solo SABRE Automotive Board
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- fsl,imx6dl-sabresd # i.MX6 DualLite SABRE Smart Device Board
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- technologic,imx6dl-ts4900
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@ -137,10 +146,18 @@ properties:
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- const: fsl,imx6ull # This seems odd. Should be last?
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- const: fsl,imx6ulz
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- description: i.MX7S based Boards
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items:
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- enum:
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- tq,imx7s-mba7 # i.MX7S TQ MBa7 with TQMa7S SoM
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- const: fsl,imx7s
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- description: i.MX7D based Boards
|
||||
items:
|
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- enum:
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- fsl,imx7d-sdb # i.MX7 SabreSD Board
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- tq,imx7d-mba7 # i.MX7D TQ MBa7 with TQMa7D SoM
|
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- zii,imx7d-rpu2 # ZII RPU2 Board
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- const: fsl,imx7d
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||||
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||||
- description:
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||||
@ -154,6 +171,12 @@ properties:
|
||||
- const: compulab,cl-som-imx7
|
||||
- const: fsl,imx7d
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||||
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||||
- description: i.MX8MM based Boards
|
||||
items:
|
||||
- enum:
|
||||
- fsl,imx8mm-evk # i.MX8MM EVK Board
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||||
- const: fsl,imx8mm
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||||
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||||
- description: i.MX8QXP based Boards
|
||||
items:
|
||||
- enum:
|
||||
@ -176,6 +199,19 @@ properties:
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||||
- fsl,vf610
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||||
- fsl,vf610m4
|
||||
|
||||
- description: ZII's VF610 based Boards
|
||||
items:
|
||||
- enum:
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||||
- zii,vf610cfu1 # ZII VF610 CFU1 Board
|
||||
- zii,vf610dev-c # ZII VF610 Development Board, Rev C
|
||||
- zii,vf610dev-b # ZII VF610 Development Board, Rev B
|
||||
- zii,vf610scu4-aib # ZII VF610 SCU4 AIB
|
||||
- zii,vf610dtu # ZII VF610 SSMB DTU Board
|
||||
- zii,vf610spu3 # ZII VF610 SSMB SPU3 Board
|
||||
- zii,vf610spb4 # ZII VF610 SPB4 Board
|
||||
- const: zii,vf610dev
|
||||
- const: fsl,vf610
|
||||
|
||||
- description: LS1012A based Boards
|
||||
items:
|
||||
- enum:
|
||||
|
22
Bindings/arm/intel-ixp4xx.yaml
Normal file
22
Bindings/arm/intel-ixp4xx.yaml
Normal file
@ -0,0 +1,22 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/intel-ixp4xx.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Intel IXP4xx Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- Linus Walleij <linus.walleij@linaro.org>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- enum:
|
||||
- linksys,nslu2
|
||||
- const: intel,ixp42x
|
||||
- items:
|
||||
- enum:
|
||||
- gateworks,gw2358
|
||||
- const: intel,ixp43x
|
@ -24,7 +24,8 @@ relationship between the TI-SCI parent node to the child node.
|
||||
|
||||
Required properties:
|
||||
-------------------
|
||||
- compatible: should be "ti,k2g-sci"
|
||||
- compatible: should be "ti,k2g-sci" for TI 66AK2G SoC
|
||||
should be "ti,am654-sci" for for TI AM654 SoC
|
||||
- mbox-names:
|
||||
"rx" - Mailbox corresponding to receive path
|
||||
"tx" - Mailbox corresponding to transmit path
|
||||
|
@ -14,6 +14,8 @@ Required Properties:
|
||||
- "mediatek,mt7629-apmixedsys"
|
||||
- "mediatek,mt8135-apmixedsys"
|
||||
- "mediatek,mt8173-apmixedsys"
|
||||
- "mediatek,mt8183-apmixedsys", "syscon"
|
||||
- "mediatek,mt8516-apmixedsys"
|
||||
- #clock-cells: Must be 1
|
||||
|
||||
The apmixedsys controller uses the common clk binding from
|
||||
|
@ -9,6 +9,7 @@ Required Properties:
|
||||
- "mediatek,mt2701-audsys", "syscon"
|
||||
- "mediatek,mt7622-audsys", "syscon"
|
||||
- "mediatek,mt7623-audsys", "mediatek,mt2701-audsys", "syscon"
|
||||
- "mediatek,mt8183-audiosys", "syscon"
|
||||
- #clock-cells: Must be 1
|
||||
|
||||
The AUDSYS controller uses the common clk binding from
|
||||
|
22
Bindings/arm/mediatek/mediatek,camsys.txt
Normal file
22
Bindings/arm/mediatek/mediatek,camsys.txt
Normal file
@ -0,0 +1,22 @@
|
||||
MediaTek CAMSYS controller
|
||||
============================
|
||||
|
||||
The MediaTek camsys controller provides various clocks to the system.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: Should be one of:
|
||||
- "mediatek,mt8183-camsys", "syscon"
|
||||
- #clock-cells: Must be 1
|
||||
|
||||
The camsys controller uses the common clk binding from
|
||||
Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
The available clocks are defined in dt-bindings/clock/mt*-clk.h.
|
||||
|
||||
Example:
|
||||
|
||||
camsys: camsys@1a000000 {
|
||||
compatible = "mediatek,mt8183-camsys", "syscon";
|
||||
reg = <0 0x1a000000 0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
@ -11,6 +11,7 @@ Required Properties:
|
||||
- "mediatek,mt6797-imgsys", "syscon"
|
||||
- "mediatek,mt7623-imgsys", "mediatek,mt2701-imgsys", "syscon"
|
||||
- "mediatek,mt8173-imgsys", "syscon"
|
||||
- "mediatek,mt8183-imgsys", "syscon"
|
||||
- #clock-cells: Must be 1
|
||||
|
||||
The imgsys controller uses the common clk binding from
|
||||
|
@ -15,6 +15,8 @@ Required Properties:
|
||||
- "mediatek,mt7629-infracfg", "syscon"
|
||||
- "mediatek,mt8135-infracfg", "syscon"
|
||||
- "mediatek,mt8173-infracfg", "syscon"
|
||||
- "mediatek,mt8183-infracfg", "syscon"
|
||||
- "mediatek,mt8516-infracfg", "syscon"
|
||||
- #clock-cells: Must be 1
|
||||
- #reset-cells: Must be 1
|
||||
|
||||
|
43
Bindings/arm/mediatek/mediatek,ipu.txt
Normal file
43
Bindings/arm/mediatek/mediatek,ipu.txt
Normal file
@ -0,0 +1,43 @@
|
||||
Mediatek IPU controller
|
||||
============================
|
||||
|
||||
The Mediatek ipu controller provides various clocks to the system.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: Should be one of:
|
||||
- "mediatek,mt8183-ipu_conn", "syscon"
|
||||
- "mediatek,mt8183-ipu_adl", "syscon"
|
||||
- "mediatek,mt8183-ipu_core0", "syscon"
|
||||
- "mediatek,mt8183-ipu_core1", "syscon"
|
||||
- #clock-cells: Must be 1
|
||||
|
||||
The ipu controller uses the common clk binding from
|
||||
Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
The available clocks are defined in dt-bindings/clock/mt*-clk.h.
|
||||
|
||||
Example:
|
||||
|
||||
ipu_conn: syscon@19000000 {
|
||||
compatible = "mediatek,mt8183-ipu_conn", "syscon";
|
||||
reg = <0 0x19000000 0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
ipu_adl: syscon@19010000 {
|
||||
compatible = "mediatek,mt8183-ipu_adl", "syscon";
|
||||
reg = <0 0x19010000 0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
ipu_core0: syscon@19180000 {
|
||||
compatible = "mediatek,mt8183-ipu_core0", "syscon";
|
||||
reg = <0 0x19180000 0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
ipu_core1: syscon@19280000 {
|
||||
compatible = "mediatek,mt8183-ipu_core1", "syscon";
|
||||
reg = <0 0x19280000 0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
@ -7,6 +7,7 @@ Required Properties:
|
||||
|
||||
- compatible: Should be one of:
|
||||
- "mediatek,mt2712-mcucfg", "syscon"
|
||||
- "mediatek,mt8183-mcucfg", "syscon"
|
||||
- #clock-cells: Must be 1
|
||||
|
||||
The mcucfg controller uses the common clk binding from
|
||||
|
@ -7,6 +7,7 @@ Required Properties:
|
||||
|
||||
- compatible: Should be one of:
|
||||
- "mediatek,mt2712-mfgcfg", "syscon"
|
||||
- "mediatek,mt8183-mfgcfg", "syscon"
|
||||
- #clock-cells: Must be 1
|
||||
|
||||
The mfgcfg controller uses the common clk binding from
|
||||
|
@ -11,6 +11,7 @@ Required Properties:
|
||||
- "mediatek,mt6797-mmsys", "syscon"
|
||||
- "mediatek,mt7623-mmsys", "mediatek,mt2701-mmsys", "syscon"
|
||||
- "mediatek,mt8173-mmsys", "syscon"
|
||||
- "mediatek,mt8183-mmsys", "syscon"
|
||||
- #clock-cells: Must be 1
|
||||
|
||||
The mmsys controller uses the common clk binding from
|
||||
|
@ -14,6 +14,8 @@ Required Properties:
|
||||
- "mediatek,mt7629-topckgen"
|
||||
- "mediatek,mt8135-topckgen"
|
||||
- "mediatek,mt8173-topckgen"
|
||||
- "mediatek,mt8183-topckgen", "syscon"
|
||||
- "mediatek,mt8516-topckgen"
|
||||
- #clock-cells: Must be 1
|
||||
|
||||
The topckgen controller uses the common clk binding from
|
||||
|
@ -11,6 +11,7 @@ Required Properties:
|
||||
- "mediatek,mt6797-vdecsys", "syscon"
|
||||
- "mediatek,mt7623-vdecsys", "mediatek,mt2701-vdecsys", "syscon"
|
||||
- "mediatek,mt8173-vdecsys", "syscon"
|
||||
- "mediatek,mt8183-vdecsys", "syscon"
|
||||
- #clock-cells: Must be 1
|
||||
|
||||
The vdecsys controller uses the common clk binding from
|
||||
|
@ -9,6 +9,7 @@ Required Properties:
|
||||
- "mediatek,mt2712-vencsys", "syscon"
|
||||
- "mediatek,mt6797-vencsys", "syscon"
|
||||
- "mediatek,mt8173-vencsys", "syscon"
|
||||
- "mediatek,mt8183-vencsys", "syscon"
|
||||
- #clock-cells: Must be 1
|
||||
|
||||
The vencsys controller uses the common clk binding from
|
||||
|
@ -41,7 +41,7 @@ Examples:
|
||||
Consumer:
|
||||
========
|
||||
See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt and
|
||||
Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt for
|
||||
Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml for
|
||||
further details.
|
||||
|
||||
An interrupt consumer on an SoC using crossbar will use:
|
||||
|
@ -92,6 +92,9 @@ SoCs:
|
||||
- DRA718
|
||||
compatible = "ti,dra718", "ti,dra722", "ti,dra72", "ti,dra7"
|
||||
|
||||
- AM5748
|
||||
compatible = "ti,am5748", "ti,dra762", "ti,dra7"
|
||||
|
||||
- AM5728
|
||||
compatible = "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7"
|
||||
|
||||
@ -184,6 +187,9 @@ Boards:
|
||||
- AM57XX SBC-AM57x
|
||||
compatible = "compulab,sbc-am57x", "compulab,cl-som-am57x", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7"
|
||||
|
||||
- AM5748 IDK
|
||||
compatible = "ti,am5748-idk", "ti,am5748", "ti,dra762", "ti,dra7";
|
||||
|
||||
- AM5728 IDK
|
||||
compatible = "ti,am5728-idk", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7"
|
||||
|
||||
|
@ -97,6 +97,7 @@ properties:
|
||||
- enum:
|
||||
- friendlyarm,nanopc-t4
|
||||
- friendlyarm,nanopi-m4
|
||||
- friendlyarm,nanopi-neo4
|
||||
- const: rockchip,rk3399
|
||||
|
||||
- description: GeekBuying GeekBox
|
||||
@ -146,7 +147,7 @@ properties:
|
||||
- const: google,gru
|
||||
- const: rockchip,rk3399
|
||||
|
||||
- description: Google Jaq (Haier Chromebook 11 and more)
|
||||
- description: Google Jaq (Haier Chromebook 11 and more w/ uSD)
|
||||
items:
|
||||
- const: google,veyron-jaq-rev5
|
||||
- const: google,veyron-jaq-rev4
|
||||
@ -159,6 +160,12 @@ properties:
|
||||
|
||||
- description: Google Jerry (Hisense Chromebook C11 and more)
|
||||
items:
|
||||
- const: google,veyron-jerry-rev15
|
||||
- const: google,veyron-jerry-rev14
|
||||
- const: google,veyron-jerry-rev13
|
||||
- const: google,veyron-jerry-rev12
|
||||
- const: google,veyron-jerry-rev11
|
||||
- const: google,veyron-jerry-rev10
|
||||
- const: google,veyron-jerry-rev7
|
||||
- const: google,veyron-jerry-rev6
|
||||
- const: google,veyron-jerry-rev5
|
||||
@ -199,6 +206,17 @@ properties:
|
||||
- const: google,veyron
|
||||
- const: rockchip,rk3288
|
||||
|
||||
- description: Google Mighty (Haier Chromebook 11 and more w/ SD)
|
||||
items:
|
||||
- const: google,veyron-mighty-rev5
|
||||
- const: google,veyron-mighty-rev4
|
||||
- const: google,veyron-mighty-rev3
|
||||
- const: google,veyron-mighty-rev2
|
||||
- const: google,veyron-mighty-rev1
|
||||
- const: google,veyron-mighty
|
||||
- const: google,veyron
|
||||
- const: rockchip,rk3288
|
||||
|
||||
- description: Google Minnie (Asus Chromebook Flip C100P)
|
||||
items:
|
||||
- const: google,veyron-minnie-rev4
|
||||
@ -308,6 +326,11 @@ properties:
|
||||
- const: netxeon,r89
|
||||
- const: rockchip,rk3288
|
||||
|
||||
- description: Orange Pi RK3399 board
|
||||
items:
|
||||
- const: rockchip,rk3399-orangepi
|
||||
- const: rockchip,rk3399
|
||||
|
||||
- description: Phytec phyCORE-RK3288 Rapid Development Kit
|
||||
items:
|
||||
- const: phytec,rk3288-pcm-947
|
||||
|
@ -5,10 +5,12 @@ Properties:
|
||||
- " st,stm32mp157-syscfg " - for stm32mp157 based SoCs,
|
||||
second value must be always "syscon".
|
||||
- reg : offset and length of the register set.
|
||||
- clocks: phandle to the syscfg clock
|
||||
|
||||
Example:
|
||||
syscfg: syscon@50020000 {
|
||||
compatible = "st,stm32mp157-syscfg", "syscon";
|
||||
reg = <0x50020000 0x400>;
|
||||
clocks = <&rcc SYSCFG>;
|
||||
};
|
||||
|
||||
|
@ -1,23 +0,0 @@
|
||||
Allwinner sunXi Platforms Device Tree Bindings
|
||||
|
||||
Each device tree must specify which Allwinner SoC it uses,
|
||||
using one of the following compatible strings:
|
||||
|
||||
allwinner,sun4i-a10
|
||||
allwinner,sun5i-a10s
|
||||
allwinner,sun5i-a13
|
||||
allwinner,sun5i-r8
|
||||
allwinner,sun6i-a31
|
||||
allwinner,sun7i-a20
|
||||
allwinner,sun8i-a23
|
||||
allwinner,sun8i-a33
|
||||
allwinner,sun8i-a83t
|
||||
allwinner,sun8i-h2-plus
|
||||
allwinner,sun8i-h3
|
||||
allwinner,sun8i-r40
|
||||
allwinner,sun8i-t3
|
||||
allwinner,sun8i-v3s
|
||||
allwinner,sun9i-a80
|
||||
allwinner,sun50i-a64
|
||||
allwinner,suniv-f1c100s
|
||||
nextthing,gr8
|
807
Bindings/arm/sunxi.yaml
Normal file
807
Bindings/arm/sunxi.yaml
Normal file
@ -0,0 +1,807 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0+ OR X11)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/sunxi.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Allwinner platforms device tree bindings
|
||||
|
||||
maintainers:
|
||||
- Chen-Yu Tsai <wens@csie.org>
|
||||
- Maxime Ripard <maxime.ripard@bootlin.com>
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
const: '/'
|
||||
compatible:
|
||||
oneOf:
|
||||
|
||||
- description: Allwinner A23 Evaluation Board
|
||||
items:
|
||||
- const: allwinner,sun8i-a23-evb
|
||||
- const: allwinner,sun8i-a23
|
||||
|
||||
- description: Allwinner A31 APP4 Evaluation Board
|
||||
items:
|
||||
- const: allwinner,app4-evb1
|
||||
- const: allwinner,sun6i-a31
|
||||
|
||||
- description: Allwinner A83t Homlet Evaluation Board v2
|
||||
items:
|
||||
- const: allwinner,h8homlet-v2
|
||||
- const: allwinner,sun8i-a83t
|
||||
|
||||
- description: Allwinner GA10H Quad Core Tablet v1.1
|
||||
items:
|
||||
- const: allwinner,ga10h-v1.1
|
||||
- const: allwinner,sun8i-a33
|
||||
|
||||
- description: Allwinner GT90H Tablet v4
|
||||
items:
|
||||
- const: allwinner,gt90h-v4
|
||||
- const: allwinner,sun8i-a23
|
||||
|
||||
- description: Allwinner R16 EVB (Parrot)
|
||||
items:
|
||||
- const: allwinner,parrot
|
||||
- const: allwinner,sun8i-a33
|
||||
|
||||
- description: Amarula A64 Relic
|
||||
items:
|
||||
- const: amarula,a64-relic
|
||||
- const: allwinner,sun50i-a64
|
||||
|
||||
- description: Auxtek T003 A10s HDMI TV Stick
|
||||
items:
|
||||
- const: allwinner,auxtek-t003
|
||||
- const: allwinner,sun5i-a10s
|
||||
|
||||
- description: Auxtek T004 A10s HDMI TV Stick
|
||||
items:
|
||||
- const: allwinner,auxtek-t004
|
||||
- const: allwinner,sun5i-a10s
|
||||
|
||||
- description: BA10 TV Box
|
||||
items:
|
||||
- const: allwinner,ba10-tvbox
|
||||
- const: allwinner,sun4i-a10
|
||||
|
||||
- description: BananaPi
|
||||
items:
|
||||
- const: lemaker,bananapi
|
||||
- const: allwinner,sun7i-a20
|
||||
|
||||
- description: BananaPi M1 Plus
|
||||
items:
|
||||
- const: sinovoip,bpi-m1-plus
|
||||
- const: allwinner,sun7i-a20
|
||||
|
||||
- description: BananaPi M2
|
||||
items:
|
||||
- const: sinovoip,bpi-m2
|
||||
- const: allwinner,sun6i-a31s
|
||||
|
||||
- description: BananaPi M2 Berry
|
||||
items:
|
||||
- const: sinovoip,bpi-m2-berry
|
||||
- const: allwinner,sun8i-r40
|
||||
|
||||
- description: BananaPi M2 Plus
|
||||
items:
|
||||
- const: sinovoip,bpi-m2-plus
|
||||
- const: allwinner,sun8i-h3
|
||||
|
||||
- description: BananaPi M2 Plus
|
||||
items:
|
||||
- const: sinovoip,bpi-m2-plus
|
||||
- const: allwinner,sun50i-h5
|
||||
|
||||
- description: BananaPi M2 Plus v1.2
|
||||
items:
|
||||
- const: bananapi,bpi-m2-plus-v1.2
|
||||
- const: allwinner,sun8i-h3
|
||||
|
||||
- description: BananaPi M2 Plus v1.2
|
||||
items:
|
||||
- const: bananapi,bpi-m2-plus-v1.2
|
||||
- const: allwinner,sun50i-h5
|
||||
|
||||
- description: BananaPi M2 Magic
|
||||
items:
|
||||
- const: sinovoip,bananapi-m2m
|
||||
- const: allwinner,sun8i-a33
|
||||
|
||||
- description: BananaPi M2 Ultra
|
||||
items:
|
||||
- const: sinovoip,bpi-m2-ultra
|
||||
- const: allwinner,sun8i-r40
|
||||
|
||||
- description: BananaPi M2 Zero
|
||||
items:
|
||||
- const: sinovoip,bpi-m2-zero
|
||||
- const: allwinner,sun8i-h2-plus
|
||||
|
||||
- description: BananaPi M3
|
||||
items:
|
||||
- const: sinovoip,bpi-m3
|
||||
- const: allwinner,sun8i-a83t
|
||||
|
||||
- description: BananaPi M64
|
||||
items:
|
||||
- const: sinovoip,bananapi-m64
|
||||
- const: allwinner,sun50i-a64
|
||||
|
||||
- description: BananaPro
|
||||
items:
|
||||
- const: lemaker,bananapro
|
||||
- const: allwinner,sun7i-a20
|
||||
|
||||
- description: Beelink GS1
|
||||
items:
|
||||
- const: azw,beelink-gs1
|
||||
- const: allwinner,sun50i-h6
|
||||
|
||||
- description: Beelink X2
|
||||
items:
|
||||
- const: roofull,beelink-x2
|
||||
- const: allwinner,sun8i-h3
|
||||
|
||||
- description: Chuwi V7 CW0825
|
||||
items:
|
||||
- const: chuwi,v7-cw0825
|
||||
- const: allwinner,sun4i-a10
|
||||
|
||||
- description: Colorfly E708 Q1 Tablet
|
||||
items:
|
||||
- const: colorfly,e708-q1
|
||||
- const: allwinner,sun6i-a31s
|
||||
|
||||
- description: CSQ CS908 Set Top Box
|
||||
items:
|
||||
- const: csq,cs908
|
||||
- const: allwinner,sun6i-a31s
|
||||
|
||||
- description: Cubietech Cubieboard
|
||||
items:
|
||||
- const: cubietech,a10-cubieboard
|
||||
- const: allwinner,sun4i-a10
|
||||
|
||||
- description: Cubietech Cubieboard2
|
||||
items:
|
||||
- const: cubietech,cubieboard2
|
||||
- const: allwinner,sun7i-a20
|
||||
|
||||
- description: Cubietech Cubieboard4
|
||||
items:
|
||||
- const: cubietech,a80-cubieboard4
|
||||
- const: allwinner,sun9i-a80
|
||||
|
||||
- description: Cubietech Cubietruck
|
||||
items:
|
||||
- const: cubietech,cubietruck
|
||||
- const: allwinner,sun7i-a20
|
||||
|
||||
- description: Cubietech Cubietruck Plus
|
||||
items:
|
||||
- const: cubietech,cubietruck-plus
|
||||
- const: allwinner,sun8i-a83t
|
||||
|
||||
- description: Difrnce DIT4350
|
||||
items:
|
||||
- const: difrnce,dit4350
|
||||
- const: allwinner,sun5i-a13
|
||||
|
||||
- description: Dserve DSRV9703C
|
||||
items:
|
||||
- const: dserve,dsrv9703c
|
||||
- const: allwinner,sun4i-a10
|
||||
|
||||
- description: Empire Electronix D709 Tablet
|
||||
items:
|
||||
- const: empire-electronix,d709
|
||||
- const: allwinner,sun5i-a13
|
||||
|
||||
- description: Empire Electronix M712 Tablet
|
||||
items:
|
||||
- const: empire-electronix,m712
|
||||
- const: allwinner,sun5i-a13
|
||||
|
||||
- description: FriendlyARM NanoPi A64
|
||||
items:
|
||||
- const: friendlyarm,nanopi-a64
|
||||
- const: allwinner,sun50i-a64
|
||||
|
||||
- description: FriendlyARM NanoPi M1
|
||||
items:
|
||||
- const: friendlyarm,nanopi-m1
|
||||
- const: allwinner,sun8i-h3
|
||||
|
||||
- description: FriendlyARM NanoPi M1 Plus
|
||||
items:
|
||||
- const: friendlyarm,nanopi-m1-plus
|
||||
- const: allwinner,sun8i-h3
|
||||
|
||||
- description: FriendlyARM NanoPi Neo
|
||||
items:
|
||||
- const: friendlyarm,nanopi-neo
|
||||
- const: allwinner,sun8i-h3
|
||||
|
||||
- description: FriendlyARM NanoPi Neo 2
|
||||
items:
|
||||
- const: friendlyarm,nanopi-neo2
|
||||
- const: allwinner,sun50i-h5
|
||||
|
||||
- description: FriendlyARM NanoPi Neo Air
|
||||
items:
|
||||
- const: friendlyarm,nanopi-neo-air
|
||||
- const: allwinner,sun8i-h3
|
||||
|
||||
- description: FriendlyARM NanoPi Neo Plus2
|
||||
items:
|
||||
- const: friendlyarm,nanopi-neo-plus2
|
||||
- const: allwinner,sun50i-h5
|
||||
|
||||
- description: Gemei G9 Tablet
|
||||
items:
|
||||
- const: gemei,g9
|
||||
- const: allwinner,sun4i-a10
|
||||
|
||||
- description: Hyundai A7HD
|
||||
items:
|
||||
- const: hyundai,a7hd
|
||||
- const: allwinner,sun4i-a10
|
||||
|
||||
- description: HSG H702
|
||||
items:
|
||||
- const: hsg,h702
|
||||
- const: allwinner,sun5i-a13
|
||||
|
||||
- description: I12 TV Box
|
||||
items:
|
||||
- const: allwinner,i12-tvbox
|
||||
- const: allwinner,sun7i-a20
|
||||
|
||||
- description: ICNova A20 SWAC
|
||||
items:
|
||||
- const: swac,icnova-a20-swac
|
||||
- const: incircuit,icnova-a20
|
||||
- const: allwinner,sun7i-a20
|
||||
|
||||
- description: INet-1
|
||||
items:
|
||||
- const: inet-tek,inet1
|
||||
- const: allwinner,sun4i-a10
|
||||
|
||||
- description: iNet-86DZ Rev 01
|
||||
items:
|
||||
- const: primux,inet86dz
|
||||
- const: allwinner,sun8i-a23
|
||||
|
||||
- description: iNet-9F Rev 03
|
||||
items:
|
||||
- const: inet-tek,inet9f-rev03
|
||||
- const: allwinner,sun4i-a10
|
||||
|
||||
- description: iNet-97F Rev 02
|
||||
items:
|
||||
- const: primux,inet97fv2
|
||||
- const: allwinner,sun4i-a10
|
||||
|
||||
- description: iNet-98V Rev 02
|
||||
items:
|
||||
- const: primux,inet98v-rev2
|
||||
- const: allwinner,sun5i-a13
|
||||
|
||||
- description: iNet D978 Rev 02 Tablet
|
||||
items:
|
||||
- const: primux,inet-d978-rev2
|
||||
- const: allwinner,sun8i-a33
|
||||
|
||||
- description: iNet Q972 Tablet
|
||||
items:
|
||||
- const: inet-tek,inet-q972
|
||||
- const: allwinner,sun6i-a31s
|
||||
|
||||
- description: Itead Ibox A20
|
||||
items:
|
||||
- const: itead,itead-ibox-a20
|
||||
- const: allwinner,sun7i-a20
|
||||
|
||||
- description: Itead Iteaduino Plus A10
|
||||
items:
|
||||
- const: itead,iteaduino-plus-a10
|
||||
- const: allwinner,sun4i-a10
|
||||
|
||||
- description: Jesurun Q5
|
||||
items:
|
||||
- const: jesurun,q5
|
||||
- const: allwinner,sun4i-a10
|
||||
|
||||
- description: Lamobo R1
|
||||
items:
|
||||
- const: lamobo,lamobo-r1
|
||||
- const: allwinner,sun7i-a20
|
||||
|
||||
- description: Libre Computer Board ALL-H3-CC H2+
|
||||
items:
|
||||
- const: libretech,all-h3-cc-h2-plus
|
||||
- const: allwinner,sun8i-h2-plus
|
||||
|
||||
- description: Libre Computer Board ALL-H3-CC H3
|
||||
items:
|
||||
- const: libretech,all-h3-cc-h3
|
||||
- const: allwinner,sun8i-h3
|
||||
|
||||
- description: Libre Computer Board ALL-H3-CC H5
|
||||
items:
|
||||
- const: libretech,all-h3-cc-h5
|
||||
- const: allwinner,sun50i-h5
|
||||
|
||||
- description: Lichee Pi One
|
||||
items:
|
||||
- const: licheepi,licheepi-one
|
||||
- const: allwinner,sun5i-a13
|
||||
|
||||
- description: Lichee Pi Zero
|
||||
items:
|
||||
- const: licheepi,licheepi-zero
|
||||
- const: allwinner,sun8i-v3s
|
||||
|
||||
- description: Lichee Pi Zero (with Dock)
|
||||
items:
|
||||
- const: licheepi,licheepi-zero-dock
|
||||
- const: licheepi,licheepi-zero
|
||||
- const: allwinner,sun8i-v3s
|
||||
|
||||
- description: Linksprite PCDuino
|
||||
items:
|
||||
- const: linksprite,a10-pcduino
|
||||
- const: allwinner,sun4i-a10
|
||||
|
||||
- description: Linksprite PCDuino2
|
||||
items:
|
||||
- const: linksprite,a10-pcduino2
|
||||
- const: allwinner,sun4i-a10
|
||||
|
||||
- description: Linksprite PCDuino3
|
||||
items:
|
||||
- const: linksprite,pcduino3
|
||||
- const: allwinner,sun7i-a20
|
||||
|
||||
- description: Linksprite PCDuino3 Nano
|
||||
items:
|
||||
- const: linksprite,pcduino3-nano
|
||||
- const: allwinner,sun7i-a20
|
||||
|
||||
- description: HAOYU Electronics Marsboard A10
|
||||
items:
|
||||
- const: haoyu,a10-marsboard
|
||||
- const: allwinner,sun4i-a10
|
||||
|
||||
- description: MapleBoard MP130
|
||||
items:
|
||||
- const: mapleboard,mp130
|
||||
- const: allwinner,sun8i-h3
|
||||
|
||||
- description: Mele A1000
|
||||
items:
|
||||
- const: mele,a1000
|
||||
- const: allwinner,sun4i-a10
|
||||
|
||||
- description: Mele A1000G Quad Set Top Box
|
||||
items:
|
||||
- const: mele,a1000g-quad
|
||||
- const: allwinner,sun6i-a31
|
||||
|
||||
- description: Mele I7 Quad Set Top Box
|
||||
items:
|
||||
- const: mele,i7
|
||||
- const: allwinner,sun6i-a31
|
||||
|
||||
- description: Mele M3
|
||||
items:
|
||||
- const: mele,m3
|
||||
- const: allwinner,sun7i-a20
|
||||
|
||||
- description: Mele M9 Set Top Box
|
||||
items:
|
||||
- const: mele,m9
|
||||
- const: allwinner,sun6i-a31
|
||||
|
||||
- description: Merrii A20 Hummingboard
|
||||
items:
|
||||
- const: merrii,a20-hummingbird
|
||||
- const: allwinner,sun7i-a20
|
||||
|
||||
- description: Merrii A31 Hummingboard
|
||||
items:
|
||||
- const: merrii,a31-hummingbird
|
||||
- const: allwinner,sun6i-a31
|
||||
|
||||
- description: Merrii A80 Optimus
|
||||
items:
|
||||
- const: merrii,a80-optimus
|
||||
- const: allwinner,sun9i-a80
|
||||
|
||||
- description: Miniand Hackberry
|
||||
items:
|
||||
- const: miniand,hackberry
|
||||
- const: allwinner,sun4i-a10
|
||||
|
||||
- description: MK802
|
||||
items:
|
||||
- const: allwinner,mk802
|
||||
- const: allwinner,sun4i-a10
|
||||
|
||||
- description: MK802-A10s
|
||||
items:
|
||||
- const: allwinner,a10s-mk802
|
||||
- const: allwinner,sun5i-a10s
|
||||
|
||||
- description: MK802-II
|
||||
items:
|
||||
- const: allwinner,mk802ii
|
||||
- const: allwinner,sun4i-a10
|
||||
|
||||
- description: MK808c
|
||||
items:
|
||||
- const: allwinner,mk808c
|
||||
- const: allwinner,sun7i-a20
|
||||
|
||||
- description: MSI Primo81 Tablet
|
||||
items:
|
||||
- const: msi,primo81
|
||||
- const: allwinner,sun6i-a31s
|
||||
|
||||
- description: Emlid Neutis N5 Developper Board
|
||||
items:
|
||||
- const: emlid,neutis-n5-devboard
|
||||
- const: emlid,neutis-n5
|
||||
- const: allwinner,sun50i-h5
|
||||
|
||||
- description: NextThing Co. CHIP
|
||||
items:
|
||||
- const: nextthing,chip
|
||||
- const: allwinner,sun5i-r8
|
||||
- const: allwinner,sun5i-a13
|
||||
|
||||
- description: NextThing Co. CHIP Pro
|
||||
items:
|
||||
- const: nextthing,chip-pro
|
||||
- const: nextthing,gr8
|
||||
|
||||
- description: NextThing Co. GR8 Evaluation Board
|
||||
items:
|
||||
- const: nextthing,gr8-evb
|
||||
- const: nextthing,gr8
|
||||
|
||||
- description: Nintendo NES Classic
|
||||
items:
|
||||
- const: nintendo,nes-classic
|
||||
- const: allwinner,sun8i-r16
|
||||
- const: allwinner,sun8i-a33
|
||||
|
||||
- description: Nintendo Super NES Classic
|
||||
items:
|
||||
- const: nintendo,super-nes-classic
|
||||
- const: nintendo,nes-classic
|
||||
- const: allwinner,sun8i-r16
|
||||
- const: allwinner,sun8i-a33
|
||||
|
||||
- description: Oceanic 5inMFD (5205)
|
||||
items:
|
||||
- const: oceanic,5205-5inmfd
|
||||
- const: allwinner,sun50i-a64
|
||||
|
||||
- description: Olimex A10-OlinuXino LIME
|
||||
items:
|
||||
- const: olimex,a10-olinuxino-lime
|
||||
- const: allwinner,sun4i-a10
|
||||
|
||||
- description: Olimex A10s-OlinuXino Micro
|
||||
items:
|
||||
- const: olimex,a10s-olinuxino-micro
|
||||
- const: allwinner,sun5i-a10s
|
||||
|
||||
- description: Olimex A13-OlinuXino
|
||||
items:
|
||||
- const: olimex,a13-olinuxino
|
||||
- const: allwinner,sun5i-a13
|
||||
|
||||
- description: Olimex A13-OlinuXino Micro
|
||||
items:
|
||||
- const: olimex,a13-olinuxino-micro
|
||||
- const: allwinner,sun5i-a13
|
||||
|
||||
- description: Olimex A20-Olimex SOM Evaluation Board
|
||||
items:
|
||||
- const: olimex,a20-olimex-som-evb
|
||||
- const: allwinner,sun7i-a20
|
||||
|
||||
- description: Olimex A20-Olimex SOM Evaluation Board (with eMMC)
|
||||
items:
|
||||
- const: olimex,a20-olimex-som-evb-emmc
|
||||
- const: allwinner,sun7i-a20
|
||||
|
||||
- description: Olimex A20-OlinuXino LIME
|
||||
items:
|
||||
- const: olimex,a20-olinuxino-lime
|
||||
- const: allwinner,sun7i-a20
|
||||
|
||||
- description: Olimex A20-OlinuXino LIME2
|
||||
items:
|
||||
- const: olimex,a20-olinuxino-lime2
|
||||
- const: allwinner,sun7i-a20
|
||||
|
||||
- description: Olimex A20-OlinuXino LIME2 (with eMMC)
|
||||
items:
|
||||
- const: olimex,a20-olinuxino-lime2-emmc
|
||||
- const: allwinner,sun7i-a20
|
||||
|
||||
- description: Olimex A20-OlinuXino Micro
|
||||
items:
|
||||
- const: olimex,a20-olinuxino-micro
|
||||
- const: allwinner,sun7i-a20
|
||||
|
||||
- description: Olimex A20-OlinuXino Micro (with eMMC)
|
||||
items:
|
||||
- const: olimex,a20-olinuxino-micro-emmc
|
||||
- const: allwinner,sun7i-a20
|
||||
|
||||
- description: Olimex A20-SOM204 Evaluation Board
|
||||
items:
|
||||
- const: olimex,a20-olimex-som204-evb
|
||||
- const: allwinner,sun7i-a20
|
||||
|
||||
- description: Olimex A20-SOM204 Evaluation Board (with eMMC)
|
||||
items:
|
||||
- const: olimex,a20-olimex-som204-evb-emmc
|
||||
- const: allwinner,sun7i-a20
|
||||
|
||||
- description: Olimex A33-OlinuXino
|
||||
items:
|
||||
- const: olimex,a33-olinuxino
|
||||
- const: allwinner,sun8i-a33
|
||||
|
||||
- description: Olimex A64-OlinuXino
|
||||
items:
|
||||
- const: olimex,a64-olinuxino
|
||||
- const: allwinner,sun50i-a64
|
||||
|
||||
- description: Olimex A64 Teres-I
|
||||
items:
|
||||
- const: olimex,a64-teres-i
|
||||
- const: allwinner,sun50i-a64
|
||||
|
||||
- description: Pine64
|
||||
items:
|
||||
- const: pine64,pine64
|
||||
- const: allwinner,sun50i-a64
|
||||
|
||||
- description: Pine64+
|
||||
items:
|
||||
- const: pine64,pine64-plus
|
||||
- const: allwinner,sun50i-a64
|
||||
|
||||
- description: Pine64 PineH64
|
||||
items:
|
||||
- const: pine64,pine-h64
|
||||
- const: allwinner,sun50i-h6
|
||||
|
||||
- description: Pine64 LTS
|
||||
items:
|
||||
- const: pine64,pine64-lts
|
||||
- const: allwinner,sun50i-r18
|
||||
- const: allwinner,sun50i-a64
|
||||
|
||||
- description: Pine64 Pinebook
|
||||
items:
|
||||
- const: pine64,pinebook
|
||||
- const: allwinner,sun50i-a64
|
||||
|
||||
- description: Pine64 SoPine Baseboard
|
||||
items:
|
||||
- const: pine64,sopine-baseboard
|
||||
- const: pine64,sopine
|
||||
- const: allwinner,sun50i-a64
|
||||
|
||||
- description: PineRiver Mini X-Plus
|
||||
items:
|
||||
- const: pineriver,mini-xplus
|
||||
- const: allwinner,sun4i-a10
|
||||
|
||||
- description: Point of View Protab2-IPS9
|
||||
items:
|
||||
- const: pov,protab2-ips9
|
||||
- const: allwinner,sun4i-a10
|
||||
|
||||
- description: Polaroid MID2407PXE03 Tablet
|
||||
items:
|
||||
- const: polaroid,mid2407pxe03
|
||||
- const: allwinner,sun8i-a23
|
||||
|
||||
- description: Polaroid MID2809PXE04 Tablet
|
||||
items:
|
||||
- const: polaroid,mid2809pxe04
|
||||
- const: allwinner,sun8i-a23
|
||||
|
||||
- description: Q8 A13 Tablet
|
||||
items:
|
||||
- const: allwinner,q8-a13
|
||||
- const: allwinner,sun5i-a13
|
||||
|
||||
- description: Q8 A23 Tablet
|
||||
items:
|
||||
- const: allwinner,q8-a23
|
||||
- const: allwinner,sun8i-a23
|
||||
|
||||
- description: Q8 A33 Tablet
|
||||
items:
|
||||
- const: allwinner,q8-a33
|
||||
- const: allwinner,sun8i-a33
|
||||
|
||||
- description: Qihua CQA3T BV3
|
||||
items:
|
||||
- const: qihua,t3-cqa3t-bv3
|
||||
- const: allwinner,sun8i-t3
|
||||
- const: allwinner,sun8i-r40
|
||||
|
||||
- description: R7 A10s HDMI TV Stick
|
||||
items:
|
||||
- const: allwinner,r7-tv-dongle
|
||||
- const: allwinner,sun5i-a10s
|
||||
|
||||
- description: RerVision H3-DVK
|
||||
items:
|
||||
- const: rervision,h3-dvk
|
||||
- const: allwinner,sun8i-h3
|
||||
|
||||
- description: Sinlinx SinA31s Core Board
|
||||
items:
|
||||
- const: sinlinx,sina31s
|
||||
- const: allwinner,sun6i-a31s
|
||||
|
||||
- description: Sinlinx SinA31s Development Board
|
||||
items:
|
||||
- const: sinlinx,sina31s-sdk
|
||||
- const: allwinner,sun6i-a31s
|
||||
|
||||
- description: Sinlinx SinA33
|
||||
items:
|
||||
- const: sinlinx,sina33
|
||||
- const: allwinner,sun8i-a33
|
||||
|
||||
- description: TBS A711 Tablet
|
||||
items:
|
||||
- const: tbs-biometrics,a711
|
||||
- const: allwinner,sun8i-a83t
|
||||
|
||||
- description: Utoo P66
|
||||
items:
|
||||
- const: utoo,p66
|
||||
- const: allwinner,sun5i-a13
|
||||
|
||||
- description: Wexler TAB7200
|
||||
items:
|
||||
- const: wexler,tab7200
|
||||
- const: allwinner,sun7i-a20
|
||||
|
||||
- description: WITS A31 Colombus Evaluation Board
|
||||
items:
|
||||
- const: wits,colombus
|
||||
- const: allwinner,sun6i-a31
|
||||
|
||||
- description: WITS Pro A20 DKT
|
||||
items:
|
||||
- const: wits,pro-a20-dkt
|
||||
- const: allwinner,sun7i-a20
|
||||
|
||||
- description: Wobo i5
|
||||
items:
|
||||
- const: wobo,a10s-wobo-i5
|
||||
- const: allwinner,sun5i-a10s
|
||||
|
||||
- description: Yones TopTech BS1078 v2 Tablet
|
||||
items:
|
||||
- const: yones-toptech,bs1078-v2
|
||||
- const: allwinner,sun6i-a31s
|
||||
|
||||
- description: Xunlong OrangePi
|
||||
items:
|
||||
- const: xunlong,orangepi
|
||||
- const: allwinner,sun7i-a20
|
||||
|
||||
- description: Xunlong OrangePi 2
|
||||
items:
|
||||
- const: xunlong,orangepi-2
|
||||
- const: allwinner,sun8i-h3
|
||||
|
||||
- description: Xunlong OrangePi 3
|
||||
items:
|
||||
- const: xunlong,orangepi-3
|
||||
- const: allwinner,sun50i-h6
|
||||
|
||||
- description: Xunlong OrangePi Lite
|
||||
items:
|
||||
- const: xunlong,orangepi-lite
|
||||
- const: allwinner,sun8i-h3
|
||||
|
||||
- description: Xunlong OrangePi Lite2
|
||||
items:
|
||||
- const: xunlong,orangepi-lite2
|
||||
- const: allwinner,sun50i-h6
|
||||
|
||||
- description: Xunlong OrangePi Mini
|
||||
items:
|
||||
- const: xunlong,orangepi-mini
|
||||
- const: allwinner,sun7i-a20
|
||||
|
||||
- description: Xunlong OrangePi One
|
||||
items:
|
||||
- const: xunlong,orangepi-one
|
||||
- const: allwinner,sun8i-h3
|
||||
|
||||
- description: Xunlong OrangePi One Plus
|
||||
items:
|
||||
- const: xunlong,orangepi-one-plus
|
||||
- const: allwinner,sun50i-h6
|
||||
|
||||
- description: Xunlong OrangePi PC
|
||||
items:
|
||||
- const: xunlong,orangepi-pc
|
||||
- const: allwinner,sun8i-h3
|
||||
|
||||
- description: Xunlong OrangePi PC 2
|
||||
items:
|
||||
- const: xunlong,orangepi-pc2
|
||||
- const: allwinner,sun50i-h5
|
||||
|
||||
- description: Xunlong OrangePi PC Plus
|
||||
items:
|
||||
- const: xunlong,orangepi-pc-plus
|
||||
- const: allwinner,sun8i-h3
|
||||
|
||||
- description: Xunlong OrangePi Plus
|
||||
items:
|
||||
- const: xunlong,orangepi-plus
|
||||
- const: allwinner,sun8i-h3
|
||||
|
||||
- description: Xunlong OrangePi Plus 2E
|
||||
items:
|
||||
- const: xunlong,orangepi-plus2e
|
||||
- const: allwinner,sun8i-h3
|
||||
|
||||
- description: Xunlong OrangePi Prime
|
||||
items:
|
||||
- const: xunlong,orangepi-prime
|
||||
- const: allwinner,sun50i-h5
|
||||
|
||||
- description: Xunlong OrangePi R1
|
||||
items:
|
||||
- const: xunlong,orangepi-r1
|
||||
- const: allwinner,sun8i-h2-plus
|
||||
|
||||
- description: Xunlong OrangePi Win
|
||||
items:
|
||||
- const: xunlong,orangepi-win
|
||||
- const: allwinner,sun50i-a64
|
||||
|
||||
- description: Xunlong OrangePi Zero
|
||||
items:
|
||||
- const: xunlong,orangepi-zero
|
||||
- const: allwinner,sun8i-h2-plus
|
||||
|
||||
- description: Xunlong OrangePi Zero Plus
|
||||
items:
|
||||
- const: xunlong,orangepi-zero-plus
|
||||
- const: allwinner,sun50i-h5
|
||||
|
||||
- description: Xunlong OrangePi Zero Plus2
|
||||
items:
|
||||
- const: xunlong,orangepi-zero-plus2
|
||||
- const: allwinner,sun50i-h5
|
||||
|
||||
- description: Xunlong OrangePi Zero Plus2
|
||||
items:
|
||||
- const: xunlong,orangepi-zero-plus2-h3
|
||||
- const: allwinner,sun8i-h3
|
36
Bindings/arm/sunxi/sunxi-mbus.txt
Normal file
36
Bindings/arm/sunxi/sunxi-mbus.txt
Normal file
@ -0,0 +1,36 @@
|
||||
Allwinner Memory Bus (MBUS) controller
|
||||
|
||||
The MBUS controller drives the MBUS that other devices in the SoC will
|
||||
use to perform DMA. It also has a register interface that allows to
|
||||
monitor and control the bandwidth and priorities for masters on that
|
||||
bus.
|
||||
|
||||
Required properties:
|
||||
- compatible: Must be one of:
|
||||
- allwinner,sun5i-a13-mbus
|
||||
- reg: Offset and length of the register set for the controller
|
||||
- clocks: phandle to the clock driving the controller
|
||||
- dma-ranges: See section 2.3.9 of the DeviceTree Specification
|
||||
- #interconnect-cells: Must be one, with the argument being the MBUS
|
||||
port ID
|
||||
|
||||
Each device having to perform their DMA through the MBUS must have the
|
||||
interconnects and interconnect-names properties set to the MBUS
|
||||
controller and with "dma-mem" as the interconnect name.
|
||||
|
||||
Example:
|
||||
|
||||
mbus: dram-controller@1c01000 {
|
||||
compatible = "allwinner,sun5i-a13-mbus";
|
||||
reg = <0x01c01000 0x1000>;
|
||||
clocks = <&ccu CLK_MBUS>;
|
||||
dma-ranges = <0x00000000 0x40000000 0x20000000>;
|
||||
#interconnect-cells = <1>;
|
||||
};
|
||||
|
||||
fe0: display-frontend@1e00000 {
|
||||
compatible = "allwinner,sun5i-a13-display-frontend";
|
||||
...
|
||||
interconnects = <&mbus 19>;
|
||||
interconnect-names = "dma-mem";
|
||||
};
|
@ -94,6 +94,8 @@ Optional properties:
|
||||
|
||||
- ti,no-idle-on-init interconnect target module should not be idled at init
|
||||
|
||||
- ti,no-idle interconnect target module should not be idled
|
||||
|
||||
Example: Single instance of MUSB controller on omap4 using interconnect ranges
|
||||
using offsets from l4_cfg second segment (0x4a000000 + 0x80000 = 0x4a0ab000):
|
||||
|
||||
@ -131,6 +133,6 @@ using offsets from l4_cfg second segment (0x4a000000 + 0x80000 = 0x4a0ab000):
|
||||
};
|
||||
};
|
||||
|
||||
Note that other SoCs, such as am335x can have multipe child devices. On am335x
|
||||
Note that other SoCs, such as am335x can have multiple child devices. On am335x
|
||||
there are two MUSB instances, two USB PHY instances, and a single CPPI41 DMA
|
||||
instance as children of a single interconnet target module.
|
||||
instance as children of a single interconnect target module.
|
||||
|
@ -6,7 +6,8 @@ devices.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible : should be "amlogic,axg-audio-clkc" for the A113X and A113D
|
||||
- compatible : should be "amlogic,axg-audio-clkc" for the A113X and A113D,
|
||||
"amlogic,g12a-audio-clkc" for G12A.
|
||||
- reg : physical base address of the clock controller and length of
|
||||
memory mapped region.
|
||||
- clocks : a list of phandle + clock-specifier pairs for the clocks listed
|
||||
|
@ -8,35 +8,30 @@ Slow Clock controller:
|
||||
|
||||
Required properties:
|
||||
- compatible : shall be one of the following:
|
||||
"atmel,at91sam9x5-sckc" or
|
||||
"atmel,at91sam9x5-sckc",
|
||||
"atmel,sama5d3-sckc" or
|
||||
"atmel,sama5d4-sckc":
|
||||
at91 SCKC (Slow Clock Controller)
|
||||
This node contains the slow clock definitions.
|
||||
|
||||
"atmel,at91sam9x5-clk-slow-osc":
|
||||
at91 slow oscillator
|
||||
|
||||
"atmel,at91sam9x5-clk-slow-rc-osc":
|
||||
at91 internal slow RC oscillator
|
||||
- reg : defines the IO memory reserved for the SCKC.
|
||||
- #size-cells : shall be 0 (reg is used to encode clk id).
|
||||
- #address-cells : shall be 1 (reg is used to encode clk id).
|
||||
- #clock-cells : shall be 0.
|
||||
- clocks : shall be the input parent clock phandle for the clock.
|
||||
|
||||
Optional properties:
|
||||
- atmel,osc-bypass : boolean property. Set this when a clock signal is directly
|
||||
provided on XIN.
|
||||
|
||||
For example:
|
||||
sckc: sckc@fffffe50 {
|
||||
compatible = "atmel,sama5d3-pmc";
|
||||
reg = <0xfffffe50 0x4>
|
||||
#size-cells = <0>;
|
||||
#address-cells = <1>;
|
||||
|
||||
/* put at91 slow clocks here */
|
||||
sckc@fffffe50 {
|
||||
compatible = "atmel,at91sam9x5-sckc";
|
||||
reg = <0xfffffe50 0x4>;
|
||||
clocks = <&slow_xtal>;
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
Power Management Controller (PMC):
|
||||
|
||||
Required properties:
|
||||
- compatible : shall be "atmel,<chip>-pmc", "syscon":
|
||||
- compatible : shall be "atmel,<chip>-pmc", "syscon" or
|
||||
"microchip,sam9x60-pmc"
|
||||
<chip> can be: at91rm9200, at91sam9260, at91sam9261,
|
||||
at91sam9263, at91sam9g45, at91sam9n12, at91sam9rl, at91sam9g15,
|
||||
at91sam9g25, at91sam9g35, at91sam9x25, at91sam9x35, at91sam9x5,
|
||||
|
93
Bindings/clock/cirrus,lochnagar.txt
Normal file
93
Bindings/clock/cirrus,lochnagar.txt
Normal file
@ -0,0 +1,93 @@
|
||||
Cirrus Logic Lochnagar Audio Development Board
|
||||
|
||||
Lochnagar is an evaluation and development board for Cirrus Logic
|
||||
Smart CODEC and Amp devices. It allows the connection of most Cirrus
|
||||
Logic devices on mini-cards, as well as allowing connection of
|
||||
various application processor systems to provide a full evaluation
|
||||
platform. Audio system topology, clocking and power can all be
|
||||
controlled through the Lochnagar, allowing the device under test
|
||||
to be used in a variety of possible use cases.
|
||||
|
||||
This binding document describes the binding for the clock portion of
|
||||
the driver.
|
||||
|
||||
Also see these documents for generic binding information:
|
||||
[1] Clock : ../clock/clock-bindings.txt
|
||||
|
||||
And these for relevant defines:
|
||||
[2] include/dt-bindings/clock/lochnagar.h
|
||||
|
||||
This binding must be part of the Lochnagar MFD binding:
|
||||
[3] ../mfd/cirrus,lochnagar.txt
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : One of the following strings:
|
||||
"cirrus,lochnagar1-clk"
|
||||
"cirrus,lochnagar2-clk"
|
||||
|
||||
- #clock-cells : Must be 1. The first cell indicates the clock
|
||||
number, see [2] for available clocks and [1].
|
||||
|
||||
Optional properties:
|
||||
|
||||
- clocks : Must contain an entry for each clock in clock-names.
|
||||
- clock-names : May contain entries for each of the following
|
||||
clocks:
|
||||
- ln-cdc-clkout : Output clock from CODEC card.
|
||||
- ln-dsp-clkout : Output clock from DSP card.
|
||||
- ln-gf-mclk1,ln-gf-mclk2,ln-gf-mclk3,ln-gf-mclk4 : Optional
|
||||
input audio clocks from host system.
|
||||
- ln-psia1-mclk, ln-psia2-mclk : Optional input audio clocks from
|
||||
external connector.
|
||||
- ln-spdif-clkout : Optional input audio clock from SPDIF.
|
||||
- ln-adat-mclk : Optional input audio clock from ADAT.
|
||||
- ln-pmic-32k : On board fixed clock.
|
||||
- ln-clk-12m : On board fixed clock.
|
||||
- ln-clk-11m : On board fixed clock.
|
||||
- ln-clk-24m : On board fixed clock.
|
||||
- ln-clk-22m : On board fixed clock.
|
||||
- ln-clk-8m : On board fixed clock.
|
||||
- ln-usb-clk-24m : On board fixed clock.
|
||||
- ln-usb-clk-12m : On board fixed clock.
|
||||
|
||||
- assigned-clocks : A list of Lochnagar clocks to be reparented, see
|
||||
[2] for available clocks.
|
||||
- assigned-clock-parents : Parents to be assigned to the clocks
|
||||
listed in "assigned-clocks".
|
||||
|
||||
Optional nodes:
|
||||
|
||||
- fixed-clock nodes may be registered for the following on board clocks:
|
||||
- ln-pmic-32k : 32768 Hz
|
||||
- ln-clk-12m : 12288000 Hz
|
||||
- ln-clk-11m : 11298600 Hz
|
||||
- ln-clk-24m : 24576000 Hz
|
||||
- ln-clk-22m : 22579200 Hz
|
||||
- ln-clk-8m : 8192000 Hz
|
||||
- ln-usb-clk-24m : 24576000 Hz
|
||||
- ln-usb-clk-12m : 12288000 Hz
|
||||
|
||||
Example:
|
||||
|
||||
lochnagar {
|
||||
lochnagar-clk {
|
||||
compatible = "cirrus,lochnagar2-clk";
|
||||
|
||||
#clock-cells = <1>;
|
||||
|
||||
clocks = <&clk-audio>, <&clk_pmic>;
|
||||
clock-names = "ln-gf-mclk2", "ln-pmic-32k";
|
||||
|
||||
assigned-clocks = <&lochnagar-clk LOCHNAGAR_CDC_MCLK1>,
|
||||
<&lochnagar-clk LOCHNAGAR_CDC_MCLK2>;
|
||||
assigned-clock-parents = <&clk-audio>,
|
||||
<&clk-pmic>;
|
||||
};
|
||||
|
||||
clk-pmic: clk-pmic {
|
||||
compatible = "fixed-clock";
|
||||
clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
};
|
73
Bindings/clock/milbeaut-clock.yaml
Normal file
73
Bindings/clock/milbeaut-clock.yaml
Normal file
@ -0,0 +1,73 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/bindings/clock/milbeaut-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Milbeaut SoCs Clock Controller Binding
|
||||
|
||||
maintainers:
|
||||
- Taichi Sugaya <sugaya.taichi@socionext.com>
|
||||
|
||||
description: |
|
||||
Milbeaut SoCs Clock controller is an integrated clock controller, which
|
||||
generates and supplies to all modules.
|
||||
|
||||
This binding uses common clock bindings
|
||||
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- enum:
|
||||
- socionext,milbeaut-m10v-ccu
|
||||
clocks:
|
||||
maxItems: 1
|
||||
description: external clock
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- '#clock-cells'
|
||||
|
||||
examples:
|
||||
# Clock controller node:
|
||||
- |
|
||||
m10v-clk-ctrl@1d021000 {
|
||||
compatible = "socionext,milbeaut-m10v-clk-ccu";
|
||||
reg = <0x1d021000 0x4000>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&clki40mhz>;
|
||||
};
|
||||
|
||||
# Required an external clock for Clock controller node:
|
||||
- |
|
||||
clocks {
|
||||
clki40mhz: clki40mhz {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <40000000>;
|
||||
};
|
||||
/* other clocks */
|
||||
};
|
||||
|
||||
# The clock consumer shall specify the desired clock-output of the clock
|
||||
# controller as below by specifying output-id in its "clk" phandle cell.
|
||||
# 2: uart
|
||||
# 4: 32-bit timer
|
||||
# 7: UHS-I/II
|
||||
- |
|
||||
serial@1e700010 {
|
||||
compatible = "socionext,milbeaut-usio-uart";
|
||||
reg = <0x1e700010 0x10>;
|
||||
interrupts = <0 141 0x4>, <0 149 0x4>;
|
||||
interrupt-names = "rx", "tx";
|
||||
clocks = <&clk 2>;
|
||||
};
|
||||
|
||||
...
|
19
Bindings/clock/qcom,turingcc.txt
Normal file
19
Bindings/clock/qcom,turingcc.txt
Normal file
@ -0,0 +1,19 @@
|
||||
Qualcomm Turing Clock & Reset Controller Binding
|
||||
------------------------------------------------
|
||||
|
||||
Required properties :
|
||||
- compatible: shall contain "qcom,qcs404-turingcc".
|
||||
- reg: shall contain base register location and length.
|
||||
- clocks: ahb clock for the TuringCC
|
||||
- #clock-cells: from common clock binding, shall contain 1.
|
||||
- #reset-cells: from common reset binding, shall contain 1.
|
||||
|
||||
Example:
|
||||
turingcc: clock-controller@800000 {
|
||||
compatible = "qcom,qcs404-turingcc";
|
||||
reg = <0x00800000 0x30000>;
|
||||
clocks = <&gcc GCC_CDSP_CFG_AHB_CLK>;
|
||||
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
@ -39,6 +39,7 @@ Required properties:
|
||||
* "fsl,b4860-clockgen"
|
||||
* "fsl,ls1012a-clockgen"
|
||||
* "fsl,ls1021a-clockgen"
|
||||
* "fsl,ls1028a-clockgen"
|
||||
* "fsl,ls1043a-clockgen"
|
||||
* "fsl,ls1046a-clockgen"
|
||||
* "fsl,ls1088a-clockgen"
|
||||
@ -83,8 +84,8 @@ second cell is the clock index for the specified type.
|
||||
1 cmux index (n in CLKCnCSR)
|
||||
2 hwaccel index (n in CLKCGnHWACSR)
|
||||
3 fman 0 for fm1, 1 for fm2
|
||||
4 platform pll 0=pll, 1=pll/2, 2=pll/3, 3=pll/4
|
||||
4=pll/5, 5=pll/6, 6=pll/7, 7=pll/8
|
||||
4 platform pll n=pll/(n+1). For example, when n=1,
|
||||
that means output_freq=PLL_freq/2.
|
||||
5 coreclk must be 0
|
||||
|
||||
3. Example
|
||||
|
@ -35,7 +35,7 @@ board device tree, including the system base clock, as selected by XOM[0]
|
||||
pin of the SoC. Refer to generic fixed rate clock bindings
|
||||
documentation[1] for more information how to specify these clocks.
|
||||
|
||||
[1] Documentation/devicetree/bindings/clock/fixed-clock.txt
|
||||
[1] Documentation/devicetree/bindings/clock/fixed-clock.yaml
|
||||
|
||||
Example: Clock controller node:
|
||||
|
||||
|
46
Bindings/clock/sifive/fu540-prci.txt
Normal file
46
Bindings/clock/sifive/fu540-prci.txt
Normal file
@ -0,0 +1,46 @@
|
||||
SiFive FU540 PRCI bindings
|
||||
|
||||
On the FU540 family of SoCs, most system-wide clock and reset integration
|
||||
is via the PRCI IP block.
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "sifive,<chip>-prci". Only one value is
|
||||
supported: "sifive,fu540-c000-prci"
|
||||
- reg: Should describe the PRCI's register target physical address region
|
||||
- clocks: Should point to the hfclk device tree node and the rtcclk
|
||||
device tree node. The RTC clock here is not a time-of-day clock,
|
||||
but is instead a high-stability clock source for system timers
|
||||
and cycle counters.
|
||||
- #clock-cells: Should be <1>
|
||||
|
||||
The clock consumer should specify the desired clock via the clock ID
|
||||
macros defined in include/dt-bindings/clock/sifive-fu540-prci.h.
|
||||
These macros begin with PRCI_CLK_.
|
||||
|
||||
The hfclk and rtcclk nodes are required, and represent physical
|
||||
crystals or resonators located on the PCB. These nodes should be present
|
||||
underneath /, rather than /soc.
|
||||
|
||||
Examples:
|
||||
|
||||
/* under /, in PCB-specific DT data */
|
||||
hfclk: hfclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <33333333>;
|
||||
clock-output-names = "hfclk";
|
||||
};
|
||||
rtcclk: rtcclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <1000000>;
|
||||
clock-output-names = "rtcclk";
|
||||
};
|
||||
|
||||
/* under /soc, in SoC-specific DT data */
|
||||
prci: clock-controller@10000000 {
|
||||
compatible = "sifive,fu540-c000-prci";
|
||||
reg = <0x0 0x10000000 0x0 0x1000>;
|
||||
clocks = <&hfclk>, <&rtcclk>;
|
||||
#clock-cells = <1>;
|
||||
};
|
@ -11,6 +11,8 @@ Required properties:
|
||||
"st,stm32f42xx-rcc"
|
||||
"st,stm32f469-rcc"
|
||||
"st,stm32f746-rcc"
|
||||
"st,stm32f769-rcc"
|
||||
|
||||
- reg: should be register base and length as documented in the
|
||||
datasheet
|
||||
- #reset-cells: 1, see below
|
||||
@ -102,6 +104,10 @@ The secondary index is bound with the following magic numbers:
|
||||
28 CLK_I2C3
|
||||
29 CLK_I2C4
|
||||
30 CLK_LPTIMER (LPTimer1 clock)
|
||||
31 CLK_PLL_SRC
|
||||
32 CLK_DFSDM1
|
||||
33 CLK_ADFSDM1
|
||||
34 CLK_F769_DSI
|
||||
)
|
||||
|
||||
Example:
|
||||
|
63
Bindings/clock/xlnx,zynqmp-clk.txt
Normal file
63
Bindings/clock/xlnx,zynqmp-clk.txt
Normal file
@ -0,0 +1,63 @@
|
||||
--------------------------------------------------------------------------
|
||||
Device Tree Clock bindings for the Zynq Ultrascale+ MPSoC controlled using
|
||||
Zynq MPSoC firmware interface
|
||||
--------------------------------------------------------------------------
|
||||
The clock controller is a h/w block of Zynq Ultrascale+ MPSoC clock
|
||||
tree. It reads required input clock frequencies from the devicetree and acts
|
||||
as clock provider for all clock consumers of PS clocks.
|
||||
|
||||
See clock_bindings.txt for more information on the generic clock bindings.
|
||||
|
||||
Required properties:
|
||||
- #clock-cells: Must be 1
|
||||
- compatible: Must contain: "xlnx,zynqmp-clk"
|
||||
- clocks: List of clock specifiers which are external input
|
||||
clocks to the given clock controller. Please refer
|
||||
the next section to find the input clocks for a
|
||||
given controller.
|
||||
- clock-names: List of clock names which are exteral input clocks
|
||||
to the given clock controller. Please refer to the
|
||||
clock bindings for more details.
|
||||
|
||||
Input clocks for zynqmp Ultrascale+ clock controller:
|
||||
|
||||
The Zynq UltraScale+ MPSoC has one primary and four alternative reference clock
|
||||
inputs. These required clock inputs are:
|
||||
- pss_ref_clk (PS reference clock)
|
||||
- video_clk (reference clock for video system )
|
||||
- pss_alt_ref_clk (alternative PS reference clock)
|
||||
- aux_ref_clk
|
||||
- gt_crx_ref_clk (transceiver reference clock)
|
||||
|
||||
The following strings are optional parameters to the 'clock-names' property in
|
||||
order to provide an optional (E)MIO clock source:
|
||||
- swdt0_ext_clk
|
||||
- swdt1_ext_clk
|
||||
- gem0_emio_clk
|
||||
- gem1_emio_clk
|
||||
- gem2_emio_clk
|
||||
- gem3_emio_clk
|
||||
- mio_clk_XX # with XX = 00..77
|
||||
- mio_clk_50_or_51 #for the mux clock to gem tsu from 50 or 51
|
||||
|
||||
|
||||
Output clocks are registered based on clock information received
|
||||
from firmware. Output clocks indexes are mentioned in
|
||||
include/dt-bindings/clock/xlnx-zynqmp-clk.h.
|
||||
|
||||
-------
|
||||
Example
|
||||
-------
|
||||
|
||||
firmware {
|
||||
zynqmp_firmware: zynqmp-firmware {
|
||||
compatible = "xlnx,zynqmp-firmware";
|
||||
method = "smc";
|
||||
zynqmp_clk: clock-controller {
|
||||
#clock-cells = <1>;
|
||||
compatible = "xlnx,zynqmp-clk";
|
||||
clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, <&aux_ref_clk>, <>_crx_ref_clk>;
|
||||
clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk","aux_ref_clk", "gt_crx_ref_clk";
|
||||
};
|
||||
};
|
||||
};
|
@ -47,7 +47,7 @@ Required properties for usb-c-connector with power delivery support:
|
||||
Required nodes:
|
||||
- any data bus to the connector should be modeled using the OF graph bindings
|
||||
specified in bindings/graph.txt, unless the bus is between parent node and
|
||||
the connector. Since single connector can have multpile data buses every bus
|
||||
the connector. Since single connector can have multiple data buses every bus
|
||||
has assigned OF graph port number as follows:
|
||||
0: High Speed (HS), present in all connectors,
|
||||
1: Super Speed (SS), present in SS capable connectors,
|
||||
|
18
Bindings/counter/ftm-quaddec.txt
Normal file
18
Bindings/counter/ftm-quaddec.txt
Normal file
@ -0,0 +1,18 @@
|
||||
FlexTimer Quadrature decoder counter
|
||||
|
||||
This driver exposes a simple counter for the quadrature decoder mode.
|
||||
|
||||
Required properties:
|
||||
- compatible: Must be "fsl,ftm-quaddec".
|
||||
- reg: Must be set to the memory region of the flextimer.
|
||||
|
||||
Optional property:
|
||||
- big-endian: Access the device registers in big-endian mode.
|
||||
|
||||
Example:
|
||||
counter0: counter@29d0000 {
|
||||
compatible = "fsl,ftm-quaddec";
|
||||
reg = <0x0 0x29d0000 0x0 0x10000>;
|
||||
big-endian;
|
||||
status = "disabled";
|
||||
};
|
@ -10,8 +10,9 @@ See ../mfd/stm32-lptimer.txt for details about the parent node.
|
||||
|
||||
Required properties:
|
||||
- compatible: Must be "st,stm32-lptimer-counter".
|
||||
- pinctrl-names: Set to "default".
|
||||
- pinctrl-0: List of phandles pointing to pin configuration nodes,
|
||||
- pinctrl-names: Set to "default". An additional "sleep" state can be
|
||||
defined to set pins in sleep state.
|
||||
- pinctrl-n: List of phandles pointing to pin configuration nodes,
|
||||
to set IN1/IN2 pins in mode of operation for Low-Power
|
||||
Timer input on external pin.
|
||||
|
||||
@ -21,7 +22,8 @@ Example:
|
||||
...
|
||||
counter {
|
||||
compatible = "st,stm32-lptimer-counter";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&lptim1_in_pins>;
|
||||
pinctrl-1 = <&lptim1_sleep_in_pins>;
|
||||
};
|
||||
};
|
31
Bindings/counter/stm32-timer-cnt.txt
Normal file
31
Bindings/counter/stm32-timer-cnt.txt
Normal file
@ -0,0 +1,31 @@
|
||||
STMicroelectronics STM32 Timer quadrature encoder
|
||||
|
||||
STM32 Timer provides quadrature encoder to detect
|
||||
angular position and direction of rotary elements,
|
||||
from IN1 and IN2 input signals.
|
||||
|
||||
Must be a sub-node of an STM32 Timer device tree node.
|
||||
See ../mfd/stm32-timers.txt for details about the parent node.
|
||||
|
||||
Required properties:
|
||||
- compatible: Must be "st,stm32-timer-counter".
|
||||
- pinctrl-names: Set to "default".
|
||||
- pinctrl-0: List of phandles pointing to pin configuration nodes,
|
||||
to set CH1/CH2 pins in mode of operation for STM32
|
||||
Timer input on external pin.
|
||||
|
||||
Example:
|
||||
timers@40010000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40010000 0x400>;
|
||||
clocks = <&rcc 0 160>;
|
||||
clock-names = "int";
|
||||
|
||||
counter {
|
||||
compatible = "st,stm32-timer-counter";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&tim1_in_pins>;
|
||||
};
|
||||
};
|
@ -37,6 +37,7 @@ Required properties:
|
||||
- GXL (S905X, S905D) : "amlogic,meson-gxl-dw-hdmi"
|
||||
- GXM (S912) : "amlogic,meson-gxm-dw-hdmi"
|
||||
followed by the common "amlogic,meson-gx-dw-hdmi"
|
||||
- G12A (S905X2, S905Y2, S905D2) : "amlogic,meson-g12a-dw-hdmi"
|
||||
- reg: Physical base address and length of the controller's registers.
|
||||
- interrupts: The HDMI interrupt number
|
||||
- clocks, clock-names : must have the phandles to the HDMI iahb and isfr clocks,
|
||||
@ -66,6 +67,9 @@ corresponding to each HDMI output and input.
|
||||
S905X (GXL) VENC Input TMDS Output
|
||||
S905D (GXL) VENC Input TMDS Output
|
||||
S912 (GXM) VENC Input TMDS Output
|
||||
S905X2 (G12A) VENC Input TMDS Output
|
||||
S905Y2 (G12A) VENC Input TMDS Output
|
||||
S905D2 (G12A) VENC Input TMDS Output
|
||||
|
||||
Example:
|
||||
|
||||
|
@ -57,18 +57,18 @@ Required properties:
|
||||
- GXL (S905X, S905D) : "amlogic,meson-gxl-vpu"
|
||||
- GXM (S912) : "amlogic,meson-gxm-vpu"
|
||||
followed by the common "amlogic,meson-gx-vpu"
|
||||
- G12A (S905X2, S905Y2, S905D2) : "amlogic,meson-g12a-vpu"
|
||||
- reg: base address and size of he following memory-mapped regions :
|
||||
- vpu
|
||||
- hhi
|
||||
- dmc
|
||||
- reg-names: should contain the names of the previous memory regions
|
||||
- interrupts: should contain the VENC Vsync interrupt number
|
||||
- amlogic,canvas: phandle to canvas provider node as described in the file
|
||||
../soc/amlogic/amlogic,canvas.txt
|
||||
|
||||
Optional properties:
|
||||
- power-domains: Optional phandle to associated power domain as described in
|
||||
the file ../power/power_domain.txt
|
||||
- amlogic,canvas: phandle to canvas provider node as described in the file
|
||||
../soc/amlogic/amlogic,canvas.txt
|
||||
|
||||
Required nodes:
|
||||
|
||||
@ -84,6 +84,9 @@ corresponding to each VPU output.
|
||||
S905X (GXL) CVBS VDAC HDMI-TX
|
||||
S905D (GXL) CVBS VDAC HDMI-TX
|
||||
S912 (GXM) CVBS VDAC HDMI-TX
|
||||
S905X2 (G12A) CVBS VDAC HDMI-TX
|
||||
S905Y2 (G12A) CVBS VDAC HDMI-TX
|
||||
S905D2 (G12A) CVBS VDAC HDMI-TX
|
||||
|
||||
Example:
|
||||
|
||||
|
@ -1,33 +0,0 @@
|
||||
Meson specific Simple Framebuffer bindings
|
||||
|
||||
This binding documents meson specific extensions to the simple-framebuffer
|
||||
bindings. The meson simplefb u-boot code relies on the devicetree containing
|
||||
pre-populated simplefb nodes.
|
||||
|
||||
These extensions are intended so that u-boot can select the right node based
|
||||
on which pipeline is being used. As such they are solely intended for
|
||||
firmware / bootloader use, and the OS should ignore them.
|
||||
|
||||
Required properties:
|
||||
- compatible: "amlogic,simple-framebuffer", "simple-framebuffer"
|
||||
- amlogic,pipeline, one of:
|
||||
"vpu-cvbs"
|
||||
"vpu-hdmi"
|
||||
|
||||
Example:
|
||||
|
||||
chosen {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
simplefb_hdmi: framebuffer-hdmi {
|
||||
compatible = "amlogic,simple-framebuffer",
|
||||
"simple-framebuffer";
|
||||
amlogic,pipeline = "vpu-hdmi";
|
||||
clocks = <&clkc CLKID_HDMI_PCLK>,
|
||||
<&clkc CLKID_CLK81>,
|
||||
<&clkc CLKID_GCLK_VENCI_INT0>;
|
||||
power-domains = <&pwrc_vpu>;
|
||||
};
|
||||
};
|
@ -6,15 +6,32 @@ Required properties:
|
||||
|
||||
Optional properties:
|
||||
- powerdown-gpios: power-down gpio
|
||||
- reg: I2C address. If and only if present the device node
|
||||
should be placed into the i2c controller node where the
|
||||
tfp410 i2c is connected to.
|
||||
- reg: I2C address. If and only if present the device node should be placed
|
||||
into the I2C controller node where the TFP410 I2C is connected to.
|
||||
- ti,deskew: data de-skew in 350ps increments, from -4 to +3, as configured
|
||||
through th DK[3:1] pins. This property shall be present only if the TFP410
|
||||
is not connected through I2C.
|
||||
|
||||
Required nodes:
|
||||
- Video port 0 for DPI input [1].
|
||||
- Video port 1 for DVI output [1].
|
||||
|
||||
[1]: Documentation/devicetree/bindings/media/video-interfaces.txt
|
||||
This device has two video ports. Their connections are modeled using the OF
|
||||
graph bindings specified in [1]. Each port node shall have a single endpoint.
|
||||
|
||||
- Port 0 is the DPI input port. Its endpoint subnode shall contain a
|
||||
pclk-sample and bus-width property and a remote-endpoint property as specified
|
||||
in [1].
|
||||
- If pclk-sample is not defined, pclk-sample = 0 should be assumed for
|
||||
backward compatibility.
|
||||
- If bus-width is not defined then bus-width = 24 should be assumed for
|
||||
backward compatibility.
|
||||
bus-width = 24: 24 data lines are connected and single-edge mode
|
||||
bus-width = 12: 12 data lines are connected and dual-edge mode
|
||||
|
||||
- Port 1 is the DVI output port. Its endpoint subnode shall contain a
|
||||
remote-endpoint property is specified in [1].
|
||||
|
||||
[1] Documentation/devicetree/bindings/media/video-interfaces.txt
|
||||
|
||||
|
||||
Example
|
||||
-------
|
||||
@ -22,6 +39,7 @@ Example
|
||||
tfp410: encoder@0 {
|
||||
compatible = "ti,tfp410";
|
||||
powerdown-gpios = <&twl_gpio 2 GPIO_ACTIVE_LOW>;
|
||||
ti,deskew = <4>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
@ -31,6 +49,8 @@ tfp410: encoder@0 {
|
||||
reg = <0>;
|
||||
|
||||
tfp410_in: endpoint@0 {
|
||||
pclk-sample = <1>;
|
||||
bus-width = <24>;
|
||||
remote-endpoint = <&dpi_out>;
|
||||
};
|
||||
};
|
||||
|
@ -24,7 +24,10 @@ Required properties:
|
||||
* "cxo"
|
||||
* "axi"
|
||||
* "mnoc"
|
||||
- power-domains: should be <&clock_gpucc GPU_CX_GDSC>
|
||||
- power-domains: should be:
|
||||
<&clock_gpucc GPU_CX_GDSC>
|
||||
<&clock_gpucc GPU_GX_GDSC>
|
||||
- power-domain-names: Matching names for the power domains
|
||||
- iommus: phandle to the adreno iommu
|
||||
- operating-points-v2: phandle to the OPP operating points
|
||||
|
||||
@ -51,7 +54,10 @@ Example:
|
||||
<&gcc GCC_GPU_MEMNOC_GFX_CLK>;
|
||||
clock-names = "gmu", "cxo", "axi", "memnoc";
|
||||
|
||||
power-domains = <&gpucc GPU_CX_GDSC>;
|
||||
power-domains = <&gpucc GPU_CX_GDSC>,
|
||||
<&gpucc GPU_GX_GDSC>;
|
||||
power-domain-names = "cx", "gx";
|
||||
|
||||
iommus = <&adreno_smmu 5>;
|
||||
|
||||
operating-points-v2 = <&gmu_opp_table>;
|
||||
|
@ -22,9 +22,14 @@ Required properties:
|
||||
- qcom,adreno-630.2
|
||||
- iommus: optional phandle to an adreno iommu instance
|
||||
- operating-points-v2: optional phandle to the OPP operating points
|
||||
- interconnects: optional phandle to an interconnect provider. See
|
||||
../interconnect/interconnect.txt for details.
|
||||
- qcom,gmu: For GMU attached devices a phandle to the GMU device that will
|
||||
control the power for the GPU. Applicable targets:
|
||||
- qcom,adreno-630.2
|
||||
- zap-shader: For a5xx and a6xx devices this node contains a memory-region that
|
||||
points to reserved memory to store the zap shader that can be used to help
|
||||
bring the GPU out of secure mode.
|
||||
|
||||
Example 3xx/4xx/a5xx:
|
||||
|
||||
@ -70,6 +75,12 @@ Example a6xx (with GMU):
|
||||
|
||||
operating-points-v2 = <&gpu_opp_table>;
|
||||
|
||||
interconnects = <&rsc_hlos MASTER_GFX3D &rsc_hlos SLAVE_EBI1>;
|
||||
|
||||
qcom,gmu = <&gmu>;
|
||||
|
||||
zap-shader {
|
||||
memory-region = <&zap_shader_region>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
20
Bindings/display/panel/feiyang,fy07024di26a30d.txt
Normal file
20
Bindings/display/panel/feiyang,fy07024di26a30d.txt
Normal file
@ -0,0 +1,20 @@
|
||||
Feiyang FY07024DI26A30-D 7" MIPI-DSI LCD Panel
|
||||
|
||||
Required properties:
|
||||
- compatible: must be "feiyang,fy07024di26a30d"
|
||||
- reg: DSI virtual channel used by that screen
|
||||
- avdd-supply: analog regulator dc1 switch
|
||||
- dvdd-supply: 3v3 digital regulator
|
||||
- reset-gpios: a GPIO phandle for the reset pin
|
||||
|
||||
Optional properties:
|
||||
- backlight: phandle for the backlight control.
|
||||
|
||||
panel@0 {
|
||||
compatible = "feiyang,fy07024di26a30d";
|
||||
reg = <0>;
|
||||
avdd-supply = <®_dc1sw>;
|
||||
dvdd-supply = <®_dldo2>;
|
||||
reset-gpios = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* LCD-RST: PD24 */
|
||||
backlight = <&backlight>;
|
||||
};
|
@ -12,7 +12,7 @@ Optional properties:
|
||||
Example:
|
||||
|
||||
&mipi_dsi {
|
||||
panel {
|
||||
panel@0 {
|
||||
compatible = "innolux,p079zca";
|
||||
reg = <0>;
|
||||
power-supply = <...>;
|
||||
|
@ -13,7 +13,7 @@ Optional properties:
|
||||
Example:
|
||||
|
||||
&mipi_dsi {
|
||||
panel {
|
||||
panel@0 {
|
||||
compatible = "innolux,p079zca";
|
||||
reg = <0>;
|
||||
avdd-supply = <...>;
|
||||
|
@ -12,7 +12,7 @@ Optional properties:
|
||||
Example:
|
||||
|
||||
&mipi_dsi {
|
||||
panel {
|
||||
panel@0 {
|
||||
compatible = "kingdisplay,kd097d04";
|
||||
reg = <0>;
|
||||
power-supply = <...>;
|
||||
|
7
Bindings/display/panel/lg,acx467akm-7.txt
Normal file
7
Bindings/display/panel/lg,acx467akm-7.txt
Normal file
@ -0,0 +1,7 @@
|
||||
LG ACX467AKM-7 4.95" 1080×1920 LCD Panel
|
||||
|
||||
Required properties:
|
||||
- compatible: must be "lg,acx467akm-7"
|
||||
|
||||
This binding is compatible with the simple-panel binding, which is specified
|
||||
in simple-panel.txt in this directory.
|
12
Bindings/display/panel/osddisplays,osd070t1718-19ts.txt
Normal file
12
Bindings/display/panel/osddisplays,osd070t1718-19ts.txt
Normal file
@ -0,0 +1,12 @@
|
||||
OSD Displays OSD070T1718-19TS 7" WVGA TFT LCD panel
|
||||
|
||||
Required properties:
|
||||
- compatible: shall be "osddisplays,osd070t1718-19ts"
|
||||
- power-supply: see simple-panel.txt
|
||||
|
||||
Optional properties:
|
||||
- backlight: see simple-panel.txt
|
||||
|
||||
This binding is compatible with the simple-panel binding, which is specified
|
||||
in simple-panel.txt in this directory. No other simple-panel properties than
|
||||
the ones specified herein are valid.
|
18
Bindings/display/panel/rocktech,jh057n00900.txt
Normal file
18
Bindings/display/panel/rocktech,jh057n00900.txt
Normal file
@ -0,0 +1,18 @@
|
||||
Rocktech jh057n00900 5.5" 720x1440 TFT LCD panel
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "rocktech,jh057n00900"
|
||||
- reg: DSI virtual channel of the peripheral
|
||||
- reset-gpios: panel reset gpio
|
||||
- backlight: phandle of the backlight device attached to the panel
|
||||
|
||||
Example:
|
||||
|
||||
&mipi_dsi {
|
||||
panel@0 {
|
||||
compatible = "rocktech,jh057n00900";
|
||||
reg = <0>;
|
||||
backlight = <&backlight>;
|
||||
reset-gpios = <&gpio3 13 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
51
Bindings/display/panel/ronbo,rb070d30.yaml
Normal file
51
Bindings/display/panel/ronbo,rb070d30.yaml
Normal file
@ -0,0 +1,51 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0+ OR X11)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/panel/ronbo,rb070d30.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Ronbo RB070D30 DSI Display Panel
|
||||
|
||||
maintainers:
|
||||
- Maxime Ripard <maxime.ripard@bootlin.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: ronbo,rb070d30
|
||||
|
||||
reg:
|
||||
description: MIPI-DSI virtual channel
|
||||
|
||||
power-gpios:
|
||||
description: GPIO used for the power pin
|
||||
maxItems: 1
|
||||
|
||||
reset-gpios:
|
||||
description: GPIO used for the reset pin
|
||||
maxItems: 1
|
||||
|
||||
shlr-gpios:
|
||||
description: GPIO used for the shlr pin (horizontal flip)
|
||||
maxItems: 1
|
||||
|
||||
updn-gpios:
|
||||
description: GPIO used for the updn pin (vertical flip)
|
||||
maxItems: 1
|
||||
|
||||
vcc-lcd-supply:
|
||||
description: Power regulator
|
||||
|
||||
backlight:
|
||||
description: Backlight used by the panel
|
||||
$ref: "/schemas/types.yaml#/definitions/phandle"
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- power-gpios
|
||||
- reg
|
||||
- reset-gpios
|
||||
- shlr-gpios
|
||||
- updn-gpios
|
||||
- vcc-lcd-supply
|
||||
|
||||
additionalProperties: false
|
@ -6,6 +6,7 @@ Required properties:
|
||||
|
||||
Optional properties:
|
||||
- label: a symbolic name for the panel
|
||||
- backlight: phandle of the backlight device
|
||||
|
||||
Required nodes:
|
||||
- Video port for DPI input
|
||||
@ -21,6 +22,7 @@ lcd-panel: td028ttec1@0 {
|
||||
spi-cpha;
|
||||
|
||||
label = "lcd";
|
||||
backlight = <&backlight>;
|
||||
port {
|
||||
lcd_in: endpoint {
|
||||
remote-endpoint = <&dpi_out>;
|
||||
|
72
Bindings/display/rockchip/rockchip,rk3066-hdmi.txt
Normal file
72
Bindings/display/rockchip/rockchip,rk3066-hdmi.txt
Normal file
@ -0,0 +1,72 @@
|
||||
Rockchip specific extensions for rk3066 HDMI
|
||||
============================================
|
||||
|
||||
Required properties:
|
||||
- compatible:
|
||||
"rockchip,rk3066-hdmi";
|
||||
- reg:
|
||||
Physical base address and length of the controller's registers.
|
||||
- clocks, clock-names:
|
||||
Phandle to HDMI controller clock, name should be "hclk".
|
||||
- interrupts:
|
||||
HDMI interrupt number.
|
||||
- power-domains:
|
||||
Phandle to the RK3066_PD_VIO power domain.
|
||||
- rockchip,grf:
|
||||
This soc uses GRF regs to switch the HDMI TX input between vop0 and vop1.
|
||||
- ports:
|
||||
Contains one port node with two endpoints, numbered 0 and 1,
|
||||
connected respectively to vop0 and vop1.
|
||||
Contains one port node with one endpoint
|
||||
connected to a hdmi-connector node.
|
||||
- pinctrl-0, pinctrl-name:
|
||||
Switch the iomux for the HPD/I2C pins to HDMI function.
|
||||
|
||||
Example:
|
||||
hdmi: hdmi@10116000 {
|
||||
compatible = "rockchip,rk3066-hdmi";
|
||||
reg = <0x10116000 0x2000>;
|
||||
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru HCLK_HDMI>;
|
||||
clock-names = "hclk";
|
||||
power-domains = <&power RK3066_PD_VIO>;
|
||||
rockchip,grf = <&grf>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&hdmii2c_xfer>, <&hdmi_hpd>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
hdmi_in: port@0 {
|
||||
reg = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
hdmi_in_vop0: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&vop0_out_hdmi>;
|
||||
};
|
||||
hdmi_in_vop1: endpoint@1 {
|
||||
reg = <1>;
|
||||
remote-endpoint = <&vop1_out_hdmi>;
|
||||
};
|
||||
};
|
||||
hdmi_out: port@1 {
|
||||
reg = <1>;
|
||||
hdmi_out_con: endpoint {
|
||||
remote-endpoint = <&hdmi_con_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
hdmi {
|
||||
hdmi_hpd: hdmi-hpd {
|
||||
rockchip,pins = <0 RK_PA0 1 &pcfg_pull_default>;
|
||||
};
|
||||
hdmii2c_xfer: hdmii2c-xfer {
|
||||
rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>,
|
||||
<0 RK_PA2 1 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
};
|
@ -1,36 +0,0 @@
|
||||
Sunxi specific Simple Framebuffer bindings
|
||||
|
||||
This binding documents sunxi specific extensions to the simple-framebuffer
|
||||
bindings. The sunxi simplefb u-boot code relies on the devicetree containing
|
||||
pre-populated simplefb nodes.
|
||||
|
||||
These extensions are intended so that u-boot can select the right node based
|
||||
on which pipeline is being used. As such they are solely intended for
|
||||
firmware / bootloader use, and the OS should ignore them.
|
||||
|
||||
Required properties:
|
||||
- compatible: "allwinner,simple-framebuffer"
|
||||
- allwinner,pipeline, one of:
|
||||
"de_be0-lcd0"
|
||||
"de_be1-lcd1"
|
||||
"de_be0-lcd0-hdmi"
|
||||
"de_be1-lcd1-hdmi"
|
||||
"mixer0-lcd0"
|
||||
"mixer0-lcd0-hdmi"
|
||||
"mixer1-lcd1-hdmi"
|
||||
"mixer1-lcd1-tve"
|
||||
|
||||
Example:
|
||||
|
||||
chosen {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
framebuffer@0 {
|
||||
compatible = "allwinner,simple-framebuffer", "simple-framebuffer";
|
||||
allwinner,pipeline = "de_be0-lcd0-hdmi";
|
||||
clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
|
||||
<&ahb_gates 44>;
|
||||
};
|
||||
};
|
@ -1,91 +0,0 @@
|
||||
Simple Framebuffer
|
||||
|
||||
A simple frame-buffer describes a frame-buffer setup by firmware or
|
||||
the bootloader, with the assumption that the display hardware has already
|
||||
been set up to scan out from the memory pointed to by the reg property.
|
||||
|
||||
Since simplefb nodes represent runtime information they must be sub-nodes of
|
||||
the chosen node (*). Simplefb nodes must be named "framebuffer@<address>".
|
||||
|
||||
If the devicetree contains nodes for the display hardware used by a simplefb,
|
||||
then the simplefb node must contain a property called "display", which
|
||||
contains a phandle pointing to the primary display hw node, so that the OS
|
||||
knows which simplefb to disable when handing over control to a driver for the
|
||||
real hardware. The bindings for the hw nodes must specify which node is
|
||||
considered the primary node.
|
||||
|
||||
It is advised to add display# aliases to help the OS determine how to number
|
||||
things. If display# aliases are used, then if the simplefb node contains a
|
||||
"display" property then the /aliases/display# path must point to the display
|
||||
hw node the "display" property points to, otherwise it must point directly
|
||||
to the simplefb node.
|
||||
|
||||
If a simplefb node represents the preferred console for user interaction,
|
||||
then the chosen node's stdout-path property should point to it, or to the
|
||||
primary display hw node, as with display# aliases. If display aliases are
|
||||
used then it should be set to the alias instead.
|
||||
|
||||
It is advised that devicetree files contain pre-filled, disabled framebuffer
|
||||
nodes, so that the firmware only needs to update the mode information and
|
||||
enable them. This way if e.g. later on support for more display clocks get
|
||||
added, the simplefb nodes will already contain this info and the firmware
|
||||
does not need to be updated.
|
||||
|
||||
If pre-filled framebuffer nodes are used, the firmware may need extra
|
||||
information to find the right node. In that case an extra platform specific
|
||||
compatible and platform specific properties should be used and documented,
|
||||
see e.g. simple-framebuffer-sunxi.txt .
|
||||
|
||||
Required properties:
|
||||
- compatible: "simple-framebuffer"
|
||||
- reg: Should contain the location and size of the framebuffer memory.
|
||||
- width: The width of the framebuffer in pixels.
|
||||
- height: The height of the framebuffer in pixels.
|
||||
- stride: The number of bytes in each line of the framebuffer.
|
||||
- format: The format of the framebuffer surface. Valid values are:
|
||||
- r5g6b5 (16-bit pixels, d[15:11]=r, d[10:5]=g, d[4:0]=b).
|
||||
- a8b8g8r8 (32-bit pixels, d[31:24]=a, d[23:16]=b, d[15:8]=g, d[7:0]=r).
|
||||
|
||||
Optional properties:
|
||||
- clocks : List of clocks used by the framebuffer.
|
||||
- *-supply : Any number of regulators used by the framebuffer. These should
|
||||
be named according to the names in the device's design.
|
||||
|
||||
The above resources are expected to already be configured correctly.
|
||||
The OS must ensure they are not modified or disabled while the simple
|
||||
framebuffer remains active.
|
||||
|
||||
- display : phandle pointing to the primary display hardware node
|
||||
|
||||
Example:
|
||||
|
||||
aliases {
|
||||
display0 = &lcdc0;
|
||||
}
|
||||
|
||||
chosen {
|
||||
framebuffer0: framebuffer@1d385000 {
|
||||
compatible = "simple-framebuffer";
|
||||
reg = <0x1d385000 (1600 * 1200 * 2)>;
|
||||
width = <1600>;
|
||||
height = <1200>;
|
||||
stride = <(1600 * 2)>;
|
||||
format = "r5g6b5";
|
||||
clocks = <&ahb_gates 36>, <&ahb_gates 43>, <&ahb_gates 44>;
|
||||
lcd-supply = <®_dc1sw>;
|
||||
display = <&lcdc0>;
|
||||
};
|
||||
stdout-path = "display0";
|
||||
};
|
||||
|
||||
soc@1c00000 {
|
||||
lcdc0: lcdc@1c0c000 {
|
||||
compatible = "allwinner,sun4i-a10-lcdc";
|
||||
...
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
*) Older devicetree files may have a compatible = "simple-framebuffer" node
|
||||
in a different place, operating systems must first enumerate any compatible
|
||||
nodes found under chosen and then check for other compatible nodes.
|
160
Bindings/display/simple-framebuffer.yaml
Normal file
160
Bindings/display/simple-framebuffer.yaml
Normal file
@ -0,0 +1,160 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/simple-framebuffer.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Simple Framebuffer Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
|
||||
- Hans de Goede <hdegoede@redhat.com>
|
||||
|
||||
description: |+
|
||||
A simple frame-buffer describes a frame-buffer setup by firmware or
|
||||
the bootloader, with the assumption that the display hardware has
|
||||
already been set up to scan out from the memory pointed to by the
|
||||
reg property.
|
||||
|
||||
Since simplefb nodes represent runtime information they must be
|
||||
sub-nodes of the chosen node (*). Simplefb nodes must be named
|
||||
framebuffer@<address>.
|
||||
|
||||
If the devicetree contains nodes for the display hardware used by a
|
||||
simplefb, then the simplefb node must contain a property called
|
||||
display, which contains a phandle pointing to the primary display
|
||||
hw node, so that the OS knows which simplefb to disable when handing
|
||||
over control to a driver for the real hardware. The bindings for the
|
||||
hw nodes must specify which node is considered the primary node.
|
||||
|
||||
It is advised to add display# aliases to help the OS determine how
|
||||
to number things. If display# aliases are used, then if the simplefb
|
||||
node contains a display property then the /aliases/display# path
|
||||
must point to the display hw node the display property points to,
|
||||
otherwise it must point directly to the simplefb node.
|
||||
|
||||
If a simplefb node represents the preferred console for user
|
||||
interaction, then the chosen node stdout-path property should point
|
||||
to it, or to the primary display hw node, as with display#
|
||||
aliases. If display aliases are used then it should be set to the
|
||||
alias instead.
|
||||
|
||||
It is advised that devicetree files contain pre-filled, disabled
|
||||
framebuffer nodes, so that the firmware only needs to update the
|
||||
mode information and enable them. This way if e.g. later on support
|
||||
for more display clocks get added, the simplefb nodes will already
|
||||
contain this info and the firmware does not need to be updated.
|
||||
|
||||
If pre-filled framebuffer nodes are used, the firmware may need
|
||||
extra information to find the right node. In that case an extra
|
||||
platform specific compatible and platform specific properties should
|
||||
be used and documented.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- allwinner,simple-framebuffer
|
||||
- amlogic,simple-framebuffer
|
||||
- const: simple-framebuffer
|
||||
|
||||
reg:
|
||||
description: Location and size of the framebuffer memory
|
||||
|
||||
clocks:
|
||||
description: List of clocks used by the framebuffer.
|
||||
|
||||
power-domains:
|
||||
description: List of power domains used by the framebuffer.
|
||||
|
||||
width:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: Width of the framebuffer in pixels
|
||||
|
||||
height:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: Height of the framebuffer in pixels
|
||||
|
||||
stride:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: Number of bytes of a line in the framebuffer
|
||||
|
||||
format:
|
||||
description: >
|
||||
Format of the framebuffer:
|
||||
* `a8b8g8r8` - 32-bit pixels, d[31:24]=a, d[23:16]=b, d[15:8]=g, d[7:0]=r
|
||||
* `r5g6b5` - 16-bit pixels, d[15:11]=r, d[10:5]=g, d[4:0]=b
|
||||
enum:
|
||||
- a8b8g8r8
|
||||
- r5g6b5
|
||||
|
||||
display:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description: Primary display hardware node
|
||||
|
||||
allwinner,pipeline:
|
||||
description: Pipeline used by the framebuffer on Allwinner SoCs
|
||||
enum:
|
||||
- de_be0-lcd0
|
||||
- de_be0-lcd0-hdmi
|
||||
- de_be0-lcd0-tve0
|
||||
- de_be1-lcd0
|
||||
- de_be1-lcd1-hdmi
|
||||
- de_fe0-de_be0-lcd0
|
||||
- de_fe0-de_be0-lcd0-hdmi
|
||||
- de_fe0-de_be0-lcd0-tve0
|
||||
- mixer0-lcd0
|
||||
- mixer0-lcd0-hdmi
|
||||
- mixer1-lcd1-hdmi
|
||||
- mixer1-lcd1-tve
|
||||
|
||||
amlogic,pipeline:
|
||||
description: Pipeline used by the framebuffer on Amlogic SoCs
|
||||
enum:
|
||||
- vpu-cvbs
|
||||
- vpu-hdmi
|
||||
|
||||
patternProperties:
|
||||
"^[a-zA-Z0-9-]+-supply$":
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description:
|
||||
Regulators used by the framebuffer. These should be named
|
||||
according to the names in the device design.
|
||||
|
||||
required:
|
||||
# The binding requires also reg, width, height, stride and format,
|
||||
# but usually they will be filled by the bootloader.
|
||||
- compatible
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
aliases {
|
||||
display0 = &lcdc0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
stdout-path = "display0";
|
||||
framebuffer0: framebuffer@1d385000 {
|
||||
compatible = "simple-framebuffer";
|
||||
reg = <0x1d385000 3840000>;
|
||||
width = <1600>;
|
||||
height = <1200>;
|
||||
stride = <3200>;
|
||||
format = "r5g6b5";
|
||||
clocks = <&ahb_gates 36>, <&ahb_gates 43>, <&ahb_gates 44>;
|
||||
lcd-supply = <®_dc1sw>;
|
||||
display = <&lcdc0>;
|
||||
};
|
||||
};
|
||||
|
||||
soc@1c00000 {
|
||||
lcdc0: lcdc@1c0c000 {
|
||||
compatible = "allwinner,sun4i-a10-lcdc";
|
||||
};
|
||||
};
|
||||
|
||||
...
|
104
Bindings/display/ste,mcde.txt
Normal file
104
Bindings/display/ste,mcde.txt
Normal file
@ -0,0 +1,104 @@
|
||||
ST-Ericsson Multi Channel Display Engine MCDE
|
||||
|
||||
The ST-Ericsson MCDE is a display controller with support for compositing
|
||||
and displaying several channels memory resident graphics data on DSI or
|
||||
LCD displays or bridges. It is used in the ST-Ericsson U8500 platform.
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: must be:
|
||||
"ste,mcde"
|
||||
- reg: register base for the main MCDE control registers, should be
|
||||
0x1000 in size
|
||||
- interrupts: the interrupt line for the MCDE
|
||||
- epod-supply: a phandle to the EPOD regulator
|
||||
- vana-supply: a phandle to the analog voltage regulator
|
||||
- clocks: an array of the MCDE clocks in this strict order:
|
||||
MCDECLK (main MCDE clock), LCDCLK (LCD clock), PLLDSI
|
||||
(HDMI clock), DSI0ESCLK (DSI0 energy save clock),
|
||||
DSI1ESCLK (DSI1 energy save clock), DSI2ESCLK (DSI2 energy
|
||||
save clock)
|
||||
- clock-names: must be the following array:
|
||||
"mcde", "lcd", "hdmi"
|
||||
to match the required clock inputs above.
|
||||
- #address-cells: should be <1> (for the DSI hosts that will be children)
|
||||
- #size-cells: should be <1> (for the DSI hosts that will be children)
|
||||
- ranges: this should always be stated
|
||||
|
||||
Required subnodes:
|
||||
|
||||
The devicetree must specify subnodes for the DSI host adapters.
|
||||
These must have the following characteristics:
|
||||
|
||||
- compatible: must be:
|
||||
"ste,mcde-dsi"
|
||||
- reg: must specify the register range for the DSI host
|
||||
- vana-supply: phandle to the VANA voltage regulator
|
||||
- clocks: phandles to the high speed and low power (energy save) clocks
|
||||
the high speed clock is not present on the third (dsi2) block, so it
|
||||
should only have the "lp" clock
|
||||
- clock-names: "hs" for the high speed clock and "lp" for the low power
|
||||
(energy save) clock
|
||||
- #address-cells: should be <1>
|
||||
- #size-cells: should be <0>
|
||||
|
||||
Display panels and bridges will appear as children on the DSI hosts, and
|
||||
the displays are connected to the DSI hosts using the common binding
|
||||
for video transmitter interfaces; see
|
||||
Documentation/devicetree/bindings/media/video-interfaces.txt
|
||||
|
||||
If a DSI host is unused (not connected) it will have no children defined.
|
||||
|
||||
Example:
|
||||
|
||||
mcde@a0350000 {
|
||||
compatible = "ste,mcde";
|
||||
reg = <0xa0350000 0x1000>;
|
||||
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
|
||||
epod-supply = <&db8500_b2r2_mcde_reg>;
|
||||
vana-supply = <&ab8500_ldo_ana_reg>;
|
||||
clocks = <&prcmu_clk PRCMU_MCDECLK>, /* Main MCDE clock */
|
||||
<&prcmu_clk PRCMU_LCDCLK>, /* LCD clock */
|
||||
<&prcmu_clk PRCMU_PLLDSI>; /* HDMI clock */
|
||||
clock-names = "mcde", "lcd", "hdmi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
dsi0: dsi@a0351000 {
|
||||
compatible = "ste,mcde-dsi";
|
||||
reg = <0xa0351000 0x1000>;
|
||||
vana-supply = <&ab8500_ldo_ana_reg>;
|
||||
clocks = <&prcmu_clk PRCMU_DSI0CLK>, <&prcmu_clk PRCMU_DSI0ESCCLK>;
|
||||
clock-names = "hs", "lp";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
panel {
|
||||
compatible = "samsung,s6d16d0";
|
||||
reg = <0>;
|
||||
vdd1-supply = <&ab8500_ldo_aux1_reg>;
|
||||
reset-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
};
|
||||
dsi1: dsi@a0352000 {
|
||||
compatible = "ste,mcde-dsi";
|
||||
reg = <0xa0352000 0x1000>;
|
||||
vana-supply = <&ab8500_ldo_ana_reg>;
|
||||
clocks = <&prcmu_clk PRCMU_DSI1CLK>, <&prcmu_clk PRCMU_DSI1ESCCLK>;
|
||||
clock-names = "hs", "lp";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
dsi2: dsi@a0353000 {
|
||||
compatible = "ste,mcde-dsi";
|
||||
reg = <0xa0353000 0x1000>;
|
||||
vana-supply = <&ab8500_ldo_ana_reg>;
|
||||
/* This DSI port only has the Low Power / Energy Save clock */
|
||||
clocks = <&prcmu_clk PRCMU_DSI2ESCCLK>;
|
||||
clock-names = "lp";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
};
|
@ -18,7 +18,6 @@ Required properties for adi,channels sub-node:
|
||||
|
||||
Required channel sub-node properties:
|
||||
- reg: Which channel this node refers to.
|
||||
- adi,length-width: Width of the DMA transfer length register.
|
||||
- adi,source-bus-width,
|
||||
adi,destination-bus-width: Width of the source or destination bus in bits.
|
||||
- adi,source-bus-type,
|
||||
@ -28,7 +27,8 @@ Required channel sub-node properties:
|
||||
1 (AXI_DMAC_TYPE_AXI_STREAM): Streaming AXI interface
|
||||
2 (AXI_DMAC_TYPE_AXI_FIFO): FIFO interface
|
||||
|
||||
Optional channel properties:
|
||||
Deprecated optional channel properties:
|
||||
- adi,length-width: Width of the DMA transfer length register.
|
||||
- adi,cyclic: Must be set if the channel supports hardware cyclic DMA
|
||||
transfers.
|
||||
- adi,2d: Must be set if the channel supports hardware 2D DMA transfers.
|
||||
|
@ -9,6 +9,7 @@ Required properties:
|
||||
"fsl,imx53-sdma"
|
||||
"fsl,imx6q-sdma"
|
||||
"fsl,imx7d-sdma"
|
||||
"fsl,imx8mq-sdma"
|
||||
The -to variants should be preferred since they allow to determine the
|
||||
correct ROM script addresses needed for the driver to work without additional
|
||||
firmware.
|
||||
|
@ -4,7 +4,9 @@ The Tegra Audio DMA controller that is used for transferring data
|
||||
between system memory and the Audio Processing Engine (APE).
|
||||
|
||||
Required properties:
|
||||
- compatible: Must be "nvidia,tegra210-adma".
|
||||
- compatible: Should contain one of the following:
|
||||
- "nvidia,tegra210-adma": for Tegra210
|
||||
- "nvidia,tegra186-adma": for Tegra186 and Tegra194
|
||||
- reg: Should contain DMA registers location and length. This should be
|
||||
a single entry that includes all of the per-channel registers in one
|
||||
contiguous bank.
|
||||
|
@ -232,37 +232,152 @@ Example:
|
||||
};
|
||||
};
|
||||
|
||||
Stratix10 SoCFPGA ECC Manager
|
||||
Stratix10 SoCFPGA ECC Manager (ARM64)
|
||||
The Stratix10 SoC ECC Manager handles the IRQs for each peripheral
|
||||
in a shared register similar to the Arria10. However, ECC requires
|
||||
access to registers that can only be read from Secure Monitor with
|
||||
SMC calls. Therefore the device tree is slightly different.
|
||||
in a shared register similar to the Arria10. However, Stratix10 ECC
|
||||
requires access to registers that can only be read from Secure Monitor
|
||||
with SMC calls. Therefore the device tree is slightly different. Note
|
||||
that only 1 interrupt is sent in Stratix10 because the double bit errors
|
||||
are treated as SErrors in ARM64 instead of IRQs in ARM32.
|
||||
|
||||
Required Properties:
|
||||
- compatible : Should be "altr,socfpga-s10-ecc-manager"
|
||||
- interrupts : Should be single bit error interrupt, then double bit error
|
||||
interrupt.
|
||||
- altr,sysgr-syscon : phandle to Stratix10 System Manager Block
|
||||
containing the ECC manager registers.
|
||||
- interrupts : Should be single bit error interrupt.
|
||||
- interrupt-controller : boolean indicator that ECC Manager is an interrupt controller
|
||||
- #interrupt-cells : must be set to 2.
|
||||
- #address-cells: must be 1
|
||||
- #size-cells: must be 1
|
||||
- ranges : standard definition, should translate from local addresses
|
||||
|
||||
Subcomponents:
|
||||
|
||||
SDRAM ECC
|
||||
Required Properties:
|
||||
- compatible : Should be "altr,sdram-edac-s10"
|
||||
- interrupts : Should be single bit error interrupt, then double bit error
|
||||
interrupt, in this order.
|
||||
- interrupts : Should be single bit error interrupt.
|
||||
|
||||
On-Chip RAM ECC
|
||||
Required Properties:
|
||||
- compatible : Should be "altr,socfpga-s10-ocram-ecc"
|
||||
- reg : Address and size for ECC block registers.
|
||||
- altr,ecc-parent : phandle to parent OCRAM node.
|
||||
- interrupts : Should be single bit error interrupt.
|
||||
|
||||
Ethernet FIFO ECC
|
||||
Required Properties:
|
||||
- compatible : Should be "altr,socfpga-s10-eth-mac-ecc"
|
||||
- reg : Address and size for ECC block registers.
|
||||
- altr,ecc-parent : phandle to parent Ethernet node.
|
||||
- interrupts : Should be single bit error interrupt.
|
||||
|
||||
NAND FIFO ECC
|
||||
Required Properties:
|
||||
- compatible : Should be "altr,socfpga-s10-nand-ecc"
|
||||
- reg : Address and size for ECC block registers.
|
||||
- altr,ecc-parent : phandle to parent NAND node.
|
||||
- interrupts : Should be single bit error interrupt.
|
||||
|
||||
DMA FIFO ECC
|
||||
Required Properties:
|
||||
- compatible : Should be "altr,socfpga-s10-dma-ecc"
|
||||
- reg : Address and size for ECC block registers.
|
||||
- altr,ecc-parent : phandle to parent DMA node.
|
||||
- interrupts : Should be single bit error interrupt.
|
||||
|
||||
USB FIFO ECC
|
||||
Required Properties:
|
||||
- compatible : Should be "altr,socfpga-s10-usb-ecc"
|
||||
- reg : Address and size for ECC block registers.
|
||||
- altr,ecc-parent : phandle to parent USB node.
|
||||
- interrupts : Should be single bit error interrupt.
|
||||
|
||||
SDMMC FIFO ECC
|
||||
Required Properties:
|
||||
- compatible : Should be "altr,socfpga-s10-sdmmc-ecc"
|
||||
- reg : Address and size for ECC block registers.
|
||||
- altr,ecc-parent : phandle to parent SD/MMC node.
|
||||
- interrupts : Should be single bit error interrupt for port A
|
||||
and then single bit error interrupt for port B.
|
||||
|
||||
Example:
|
||||
|
||||
eccmgr {
|
||||
compatible = "altr,socfpga-s10-ecc-manager";
|
||||
interrupts = <0 15 4>, <0 95 4>;
|
||||
altr,sysmgr-syscon = <&sysmgr>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
interrupts = <0 15 4>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
ranges;
|
||||
|
||||
sdramedac {
|
||||
compatible = "altr,sdram-edac-s10";
|
||||
interrupts = <16 4>, <48 4>;
|
||||
interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
ocram-ecc@ff8cc000 {
|
||||
compatible = "altr,socfpga-s10-ocram-ecc";
|
||||
reg = <ff8cc000 0x100>;
|
||||
altr,ecc-parent = <&ocram>;
|
||||
interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
emac0-rx-ecc@ff8c0000 {
|
||||
compatible = "altr,socfpga-s10-eth-mac-ecc";
|
||||
reg = <0xff8c0000 0x100>;
|
||||
altr,ecc-parent = <&gmac0>;
|
||||
interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
emac0-tx-ecc@ff8c0400 {
|
||||
compatible = "altr,socfpga-s10-eth-mac-ecc";
|
||||
reg = <0xff8c0400 0x100>;
|
||||
altr,ecc-parent = <&gmac0>;
|
||||
interrupts = <5 IRQ_TYPE_LEVEL_HIGH>'
|
||||
};
|
||||
|
||||
nand-buf-ecc@ff8c8000 {
|
||||
compatible = "altr,socfpga-s10-nand-ecc";
|
||||
reg = <0xff8c8000 0x100>;
|
||||
altr,ecc-parent = <&nand>;
|
||||
interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
nand-rd-ecc@ff8c8400 {
|
||||
compatible = "altr,socfpga-s10-nand-ecc";
|
||||
reg = <0xff8c8400 0x100>;
|
||||
altr,ecc-parent = <&nand>;
|
||||
interrupts = <13 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
nand-wr-ecc@ff8c8800 {
|
||||
compatible = "altr,socfpga-s10-nand-ecc";
|
||||
reg = <0xff8c8800 0x100>;
|
||||
altr,ecc-parent = <&nand>;
|
||||
interrupts = <12 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
dma-ecc@ff8c9000 {
|
||||
compatible = "altr,socfpga-s10-dma-ecc";
|
||||
reg = <0xff8c9000 0x100>;
|
||||
altr,ecc-parent = <&pdma>;
|
||||
interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
usb0-ecc@ff8c4000 {
|
||||
compatible = "altr,socfpga-s10-usb-ecc";
|
||||
reg = <0xff8c4000 0x100>;
|
||||
altr,ecc-parent = <&usb0>;
|
||||
interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
sdmmc-ecc@ff8c8c00 {
|
||||
compatible = "altr,socfpga-s10-sdmmc-ecc";
|
||||
reg = <0xff8c8c00 0x100>;
|
||||
altr,ecc-parent = <&mmc>;
|
||||
interrupts = <14 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<15 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
|
@ -50,6 +50,7 @@ Required properties:
|
||||
|
||||
"nxp,se97b" - the fallback is "atmel,24c02",
|
||||
"renesas,r1ex24002" - the fallback is "atmel,24c02"
|
||||
"renesas,r1ex24016" - the fallback is "atmel,24c16"
|
||||
"renesas,r1ex24128" - the fallback is "atmel,24c128"
|
||||
"rohm,br24t01" - the fallback is "atmel,24c01"
|
||||
|
||||
|
71
Bindings/fieldbus/arcx,anybus-controller.txt
Normal file
71
Bindings/fieldbus/arcx,anybus-controller.txt
Normal file
@ -0,0 +1,71 @@
|
||||
* Arcx Anybus-S controller
|
||||
|
||||
This chip communicates with the SoC over a parallel bus. It is
|
||||
expected that its Device Tree node is specified as the child of a node
|
||||
corresponding to the parallel bus used for communication.
|
||||
|
||||
Required properties:
|
||||
--------------------
|
||||
|
||||
- compatible : The following chip-specific string:
|
||||
"arcx,anybus-controller"
|
||||
|
||||
- reg : three areas:
|
||||
index 0: bus memory area where the cpld registers are located.
|
||||
index 1: bus memory area of the first host's dual-port ram.
|
||||
index 2: bus memory area of the second host's dual-port ram.
|
||||
|
||||
- reset-gpios : the GPIO pin connected to the reset line of the controller.
|
||||
|
||||
- interrupts : two interrupts:
|
||||
index 0: interrupt connected to the first host
|
||||
index 1: interrupt connected to the second host
|
||||
Generic interrupt client node bindings are described in
|
||||
interrupt-controller/interrupts.txt
|
||||
|
||||
Optional: use of subnodes
|
||||
-------------------------
|
||||
|
||||
The card connected to a host may need additional properties. These can be
|
||||
specified in subnodes to the controller node.
|
||||
|
||||
The subnodes are identified by the standard 'reg' property. Which information
|
||||
exactly can be specified depends on the bindings for the function driver
|
||||
for the subnode.
|
||||
|
||||
Required controller node properties when using subnodes:
|
||||
- #address-cells: should be one.
|
||||
- #size-cells: should be zero.
|
||||
|
||||
Required subnode properties:
|
||||
- reg: Must contain the host index of the card this subnode describes:
|
||||
<0> for the first host on the controller
|
||||
<1> for the second host on the controller
|
||||
Note that only a single card can be plugged into a host, so the host
|
||||
index uniquely describes the card location.
|
||||
|
||||
Example of usage:
|
||||
-----------------
|
||||
|
||||
This example places the bridge on top of the i.MX WEIM parallel bus, see:
|
||||
Documentation/devicetree/bindings/bus/imx-weim.txt
|
||||
|
||||
&weim {
|
||||
controller@0,0 {
|
||||
compatible = "arcx,anybus-controller";
|
||||
reg = <0 0 0x100>, <0 0x400000 0x800>, <1 0x400000 0x800>;
|
||||
reset-gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>;
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <1 IRQ_TYPE_LEVEL_LOW>, <5 IRQ_TYPE_LEVEL_LOW>;
|
||||
/* fsl,weim-cs-timing is a i.MX WEIM bus specific property */
|
||||
fsl,weim-cs-timing = <0x024400b1 0x00001010 0x20081100
|
||||
0x00000000 0xa0000240 0x00000000>;
|
||||
/* optional subnode for a card plugged into the first host */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
card@0 {
|
||||
reg = <0>;
|
||||
/* card specific properties go here */
|
||||
};
|
||||
};
|
||||
};
|
@ -0,0 +1,44 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
# Copyright 2019 Linaro Ltd.
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/firmware/intel-ixp4xx-network-processing-engine.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
|
||||
title: Intel IXP4xx Network Processing Engine
|
||||
|
||||
maintainers:
|
||||
- Linus Walleij <linus.walleij@linaro.org>
|
||||
|
||||
description: |
|
||||
On the IXP4xx SoCs, the Network Processing Engine (NPE) is a small
|
||||
processor that can load a firmware to perform offloading of networking
|
||||
and crypto tasks. It also manages the MDIO bus to the ethernet PHYs
|
||||
on the IXP4xx platform. All IXP4xx platforms have three NPEs at
|
||||
consecutive memory locations. They are all included in the same
|
||||
device node since they are not independent of each other.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- const: intel,ixp4xx-network-processing-engine
|
||||
|
||||
reg:
|
||||
minItems: 3
|
||||
maxItems: 3
|
||||
items:
|
||||
- description: NPE0 register range
|
||||
- description: NPE1 register range
|
||||
- description: NPE2 register range
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
examples:
|
||||
- |
|
||||
npe@c8006000 {
|
||||
compatible = "intel,ixp4xx-network-processing-engine";
|
||||
reg = <0xc8006000 0x1000>, <0xc8007000 0x1000>, <0xc8008000 0x1000>;
|
||||
};
|
@ -17,53 +17,6 @@ Required properties:
|
||||
- "smc" : SMC #0, following the SMCCC
|
||||
- "hvc" : HVC #0, following the SMCCC
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
Device Tree Clock bindings for the Zynq Ultrascale+ MPSoC controlled using
|
||||
Zynq MPSoC firmware interface
|
||||
--------------------------------------------------------------------------
|
||||
The clock controller is a h/w block of Zynq Ultrascale+ MPSoC clock
|
||||
tree. It reads required input clock frequencies from the devicetree and acts
|
||||
as clock provider for all clock consumers of PS clocks.
|
||||
|
||||
See clock_bindings.txt for more information on the generic clock bindings.
|
||||
|
||||
Required properties:
|
||||
- #clock-cells: Must be 1
|
||||
- compatible: Must contain: "xlnx,zynqmp-clk"
|
||||
- clocks: List of clock specifiers which are external input
|
||||
clocks to the given clock controller. Please refer
|
||||
the next section to find the input clocks for a
|
||||
given controller.
|
||||
- clock-names: List of clock names which are exteral input clocks
|
||||
to the given clock controller. Please refer to the
|
||||
clock bindings for more details.
|
||||
|
||||
Input clocks for zynqmp Ultrascale+ clock controller:
|
||||
|
||||
The Zynq UltraScale+ MPSoC has one primary and four alternative reference clock
|
||||
inputs. These required clock inputs are:
|
||||
- pss_ref_clk (PS reference clock)
|
||||
- video_clk (reference clock for video system )
|
||||
- pss_alt_ref_clk (alternative PS reference clock)
|
||||
- aux_ref_clk
|
||||
- gt_crx_ref_clk (transceiver reference clock)
|
||||
|
||||
The following strings are optional parameters to the 'clock-names' property in
|
||||
order to provide an optional (E)MIO clock source:
|
||||
- swdt0_ext_clk
|
||||
- swdt1_ext_clk
|
||||
- gem0_emio_clk
|
||||
- gem1_emio_clk
|
||||
- gem2_emio_clk
|
||||
- gem3_emio_clk
|
||||
- mio_clk_XX # with XX = 00..77
|
||||
- mio_clk_50_or_51 #for the mux clock to gem tsu from 50 or 51
|
||||
|
||||
|
||||
Output clocks are registered based on clock information received
|
||||
from firmware. Output clocks indexes are mentioned in
|
||||
include/dt-bindings/clock/xlnx,zynqmp-clk.h.
|
||||
|
||||
-------
|
||||
Example
|
||||
-------
|
||||
@ -72,11 +25,6 @@ firmware {
|
||||
zynqmp_firmware: zynqmp-firmware {
|
||||
compatible = "xlnx,zynqmp-firmware";
|
||||
method = "smc";
|
||||
zynqmp_clk: clock-controller {
|
||||
#clock-cells = <1>;
|
||||
compatible = "xlnx,zynqmp-clk";
|
||||
clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, <&aux_ref_clk>, <>_crx_ref_clk>;
|
||||
clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk","aux_ref_clk", "gt_crx_ref_clk";
|
||||
};
|
||||
...
|
||||
};
|
||||
};
|
||||
|
25
Bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
Normal file
25
Bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
Normal file
@ -0,0 +1,25 @@
|
||||
Devicetree bindings for Zynq Ultrascale MPSoC FPGA Manager.
|
||||
The ZynqMP SoC uses the PCAP (Processor configuration Port) to configure the
|
||||
Programmable Logic (PL). The configuration uses the firmware interface.
|
||||
|
||||
Required properties:
|
||||
- compatible: should contain "xlnx,zynqmp-pcap-fpga"
|
||||
|
||||
Example for full FPGA configuration:
|
||||
|
||||
fpga-region0 {
|
||||
compatible = "fpga-region";
|
||||
fpga-mgr = <&zynqmp_pcap>;
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x1>;
|
||||
};
|
||||
|
||||
firmware {
|
||||
zynqmp_firmware: zynqmp-firmware {
|
||||
compatible = "xlnx,zynqmp-firmware";
|
||||
method = "smc";
|
||||
zynqmp_pcap: pcap {
|
||||
compatible = "xlnx,zynqmp-pcap-fpga";
|
||||
};
|
||||
};
|
||||
};
|
@ -9,6 +9,7 @@ Required properties:
|
||||
|
||||
- compatible : Must be one of
|
||||
|
||||
"u-blox,neo-6m"
|
||||
"u-blox,neo-8"
|
||||
"u-blox,neo-m8"
|
||||
|
||||
|
@ -2,6 +2,7 @@
|
||||
|
||||
Required properties:
|
||||
- compatible: Has to contain one of the following:
|
||||
nxp,pca6416
|
||||
nxp,pca9505
|
||||
nxp,pca9534
|
||||
nxp,pca9535
|
||||
@ -30,6 +31,7 @@ Required properties:
|
||||
ti,tca6424
|
||||
ti,tca9539
|
||||
ti,tca9554
|
||||
onnn,cat9554
|
||||
onnn,pca9654
|
||||
exar,xra1202
|
||||
- gpio-controller: if used as gpio expander.
|
||||
|
92
Bindings/gpu/arm,mali-bifrost.txt
Normal file
92
Bindings/gpu/arm,mali-bifrost.txt
Normal file
@ -0,0 +1,92 @@
|
||||
ARM Mali Bifrost GPU
|
||||
====================
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible :
|
||||
* Since Mali Bifrost GPU model/revision is fully discoverable by reading
|
||||
some determined registers, must contain the following:
|
||||
+ "arm,mali-bifrost"
|
||||
* which must be preceded by one of the following vendor specifics:
|
||||
+ "amlogic,meson-g12a-mali"
|
||||
|
||||
- reg : Physical base address of the device and length of the register area.
|
||||
|
||||
- interrupts : Contains the three IRQ lines required by Mali Bifrost devices,
|
||||
in the following defined order.
|
||||
|
||||
- interrupt-names : Contains the names of IRQ resources in this exact defined
|
||||
order: "job", "mmu", "gpu".
|
||||
|
||||
Optional properties:
|
||||
|
||||
- clocks : Phandle to clock for the Mali Bifrost device.
|
||||
|
||||
- mali-supply : Phandle to regulator for the Mali device. Refer to
|
||||
Documentation/devicetree/bindings/regulator/regulator.txt for details.
|
||||
|
||||
- operating-points-v2 : Refer to Documentation/devicetree/bindings/opp/opp.txt
|
||||
for details.
|
||||
|
||||
- resets : Phandle of the GPU reset line.
|
||||
|
||||
Vendor-specific bindings
|
||||
------------------------
|
||||
|
||||
The Mali GPU is integrated very differently from one SoC to
|
||||
another. In order to accommodate those differences, you have the option
|
||||
to specify one more vendor-specific compatible, among:
|
||||
|
||||
- "amlogic,meson-g12a-mali"
|
||||
Required properties:
|
||||
- resets : Should contain phandles of :
|
||||
+ GPU reset line
|
||||
+ GPU APB glue reset line
|
||||
|
||||
Example for a Mali-G31:
|
||||
|
||||
gpu@ffa30000 {
|
||||
compatible = "amlogic,meson-g12a-mali", "arm,mali-bifrost";
|
||||
reg = <0xffe40000 0x10000>;
|
||||
interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "job", "mmu", "gpu";
|
||||
clocks = <&clk CLKID_MALI>;
|
||||
mali-supply = <&vdd_gpu>;
|
||||
operating-points-v2 = <&gpu_opp_table>;
|
||||
resets = <&reset RESET_DVALIN_CAPB3>, <&reset RESET_DVALIN>;
|
||||
};
|
||||
|
||||
gpu_opp_table: opp_table0 {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
opp@533000000 {
|
||||
opp-hz = /bits/ 64 <533000000>;
|
||||
opp-microvolt = <1250000>;
|
||||
};
|
||||
opp@450000000 {
|
||||
opp-hz = /bits/ 64 <450000000>;
|
||||
opp-microvolt = <1150000>;
|
||||
};
|
||||
opp@400000000 {
|
||||
opp-hz = /bits/ 64 <400000000>;
|
||||
opp-microvolt = <1125000>;
|
||||
};
|
||||
opp@350000000 {
|
||||
opp-hz = /bits/ 64 <350000000>;
|
||||
opp-microvolt = <1075000>;
|
||||
};
|
||||
opp@266000000 {
|
||||
opp-hz = /bits/ 64 <266000000>;
|
||||
opp-microvolt = <1025000>;
|
||||
};
|
||||
opp@160000000 {
|
||||
opp-hz = /bits/ 64 <160000000>;
|
||||
opp-microvolt = <925000>;
|
||||
};
|
||||
opp@100000000 {
|
||||
opp-hz = /bits/ 64 <100000000>;
|
||||
opp-microvolt = <912500>;
|
||||
};
|
||||
};
|
@ -37,6 +37,20 @@ Optional properties:
|
||||
- operating-points-v2 : Refer to Documentation/devicetree/bindings/opp/opp.txt
|
||||
for details.
|
||||
|
||||
- resets : Phandle of the GPU reset line.
|
||||
|
||||
Vendor-specific bindings
|
||||
------------------------
|
||||
|
||||
The Mali GPU is integrated very differently from one SoC to
|
||||
another. In order to accomodate those differences, you have the option
|
||||
to specify one more vendor-specific compatible, among:
|
||||
|
||||
- "amlogic,meson-gxm-mali"
|
||||
Required properties:
|
||||
- resets : Should contain phandles of :
|
||||
+ GPU reset line
|
||||
+ GPU APB glue reset line
|
||||
|
||||
Example for a Mali-T760:
|
||||
|
||||
|
41
Bindings/gpu/aspeed-gfx.txt
Normal file
41
Bindings/gpu/aspeed-gfx.txt
Normal file
@ -0,0 +1,41 @@
|
||||
Device tree configuration for the GFX display device on the ASPEED SoCs
|
||||
|
||||
Required properties:
|
||||
- compatible
|
||||
* Must be one of the following:
|
||||
+ aspeed,ast2500-gfx
|
||||
+ aspeed,ast2400-gfx
|
||||
* In addition, the ASPEED pinctrl bindings require the 'syscon' property to
|
||||
be present
|
||||
|
||||
- reg: Physical base address and length of the GFX registers
|
||||
|
||||
- interrupts: interrupt number for the GFX device
|
||||
|
||||
- clocks: clock number used to generate the pixel clock
|
||||
|
||||
- resets: reset line that must be released to use the GFX device
|
||||
|
||||
- memory-region:
|
||||
Phandle to a memory region to allocate from, as defined in
|
||||
Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
|
||||
|
||||
|
||||
Example:
|
||||
|
||||
gfx: display@1e6e6000 {
|
||||
compatible = "aspeed,ast2500-gfx", "syscon";
|
||||
reg = <0x1e6e6000 0x1000>;
|
||||
reg-io-width = <4>;
|
||||
clocks = <&syscon ASPEED_CLK_GATE_D1CLK>;
|
||||
resets = <&syscon ASPEED_RESET_CRT1>;
|
||||
interrupts = <0x19>;
|
||||
memory-region = <&gfx_memory>;
|
||||
};
|
||||
|
||||
gfx_memory: framebuffer {
|
||||
size = <0x01000000>;
|
||||
alignment = <0x01000000>;
|
||||
compatible = "shared-dma-pool";
|
||||
reusable;
|
||||
};
|
@ -6,15 +6,20 @@ For V3D 2.x, see brcm,bcm-vc4.txt.
|
||||
Required properties:
|
||||
- compatible: Should be "brcm,7268-v3d" or "brcm,7278-v3d"
|
||||
- reg: Physical base addresses and lengths of the register areas
|
||||
- reg-names: Names for the register areas. The "hub", "bridge", and "core0"
|
||||
- reg-names: Names for the register areas. The "hub" and "core0"
|
||||
register areas are always required. The "gca" register area
|
||||
is required if the GCA cache controller is present.
|
||||
is required if the GCA cache controller is present. The
|
||||
"bridge" register area is required if an external reset
|
||||
controller is not present.
|
||||
- interrupts: The interrupt numbers. The first interrupt is for the hub,
|
||||
while the following interrupts are for the cores.
|
||||
while the following interrupts are separate interrupt lines
|
||||
for the cores (if they don't share the hub's interrupt).
|
||||
See bindings/interrupt-controller/interrupts.txt
|
||||
|
||||
Optional properties:
|
||||
- clocks: The core clock the unit runs on
|
||||
- resets: The reset line for v3d, if not using a mapping of the bridge
|
||||
See bindings/reset/reset.txt
|
||||
|
||||
v3d {
|
||||
compatible = "brcm,7268-v3d";
|
||||
|
26
Bindings/hwmon/cirrus,lochnagar.txt
Normal file
26
Bindings/hwmon/cirrus,lochnagar.txt
Normal file
@ -0,0 +1,26 @@
|
||||
Cirrus Logic Lochnagar Audio Development Board
|
||||
|
||||
Lochnagar is an evaluation and development board for Cirrus Logic
|
||||
Smart CODEC and Amp devices. It allows the connection of most Cirrus
|
||||
Logic devices on mini-cards, as well as allowing connection of
|
||||
various application processor systems to provide a full evaluation
|
||||
platform. Audio system topology, clocking and power can all be
|
||||
controlled through the Lochnagar, allowing the device under test
|
||||
to be used in a variety of possible use cases.
|
||||
|
||||
This binding document describes the binding for the hardware monitor
|
||||
portion of the driver.
|
||||
|
||||
This binding must be part of the Lochnagar MFD binding:
|
||||
[4] ../mfd/cirrus,lochnagar.txt
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : One of the following strings:
|
||||
"cirrus,lochnagar2-hwmon"
|
||||
|
||||
Example:
|
||||
|
||||
lochnagar-hwmon {
|
||||
compatible = "cirrus,lochnagar2-hwmon";
|
||||
};
|
@ -21,7 +21,7 @@ If an optional property is not set in .dts file, then current value is kept
|
||||
unmodified (e.g. u-boot installed value).
|
||||
|
||||
Additional information on operational parameters for the device is available
|
||||
in Documentation/hwmon/g762. A detailed datasheet for the device is available
|
||||
in Documentation/hwmon/g762.rst. A detailed datasheet for the device is available
|
||||
at http://natisbad.org/NAS/refs/GMT_EDS-762_763-080710-0.2.pdf.
|
||||
|
||||
Example g762 node:
|
||||
|
@ -25,6 +25,7 @@ Required properties:
|
||||
"ti,tmp175",
|
||||
"ti,tmp275",
|
||||
"ti,tmp75",
|
||||
"ti,tmp75b",
|
||||
"ti,tmp75c",
|
||||
|
||||
- reg: I2C bus address of the device
|
||||
|
@ -7,13 +7,20 @@ Required properties:
|
||||
which correspond to thermal cooling states
|
||||
|
||||
Optional properties:
|
||||
- fan-supply : phandle to the regulator that provides power to the fan
|
||||
- fan-supply : phandle to the regulator that provides power to the fan
|
||||
- interrupts : This contains a single interrupt specifier which
|
||||
describes the tachometer output of the fan as an
|
||||
interrupt source. The output signal must generate a
|
||||
defined number of interrupts per fan revolution, which
|
||||
require that it must be self resetting edge interrupts.
|
||||
See interrupt-controller/interrupts.txt for the format.
|
||||
- pulses-per-revolution : define the tachometer pulses per fan revolution as
|
||||
an integer (default is 2 interrupts per revolution).
|
||||
The value must be greater than zero.
|
||||
|
||||
Example:
|
||||
fan0: pwm-fan {
|
||||
compatible = "pwm-fan";
|
||||
cooling-min-state = <0>;
|
||||
cooling-max-state = <3>;
|
||||
#cooling-cells = <2>;
|
||||
pwms = <&pwm 0 10000 0>;
|
||||
cooling-levels = <0 102 170 230>;
|
||||
@ -38,3 +45,13 @@ Example:
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
Example 2:
|
||||
fan0: pwm-fan {
|
||||
compatible = "pwm-fan";
|
||||
pwms = <&pwm 0 40000 0>;
|
||||
fan-supply = <®_fan>;
|
||||
interrupt-parent = <&gpio5>;
|
||||
interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
|
||||
pulses-per-revolution = <2>;
|
||||
};
|
||||
|
@ -3,15 +3,12 @@ Broadcom iProc I2C controller
|
||||
Required properties:
|
||||
|
||||
- compatible:
|
||||
Must be "brcm,iproc-i2c"
|
||||
Must be "brcm,iproc-i2c" or "brcm,iproc-nic-i2c"
|
||||
|
||||
- reg:
|
||||
Define the base and range of the I/O address space that contain the iProc
|
||||
I2C controller registers
|
||||
|
||||
- interrupts:
|
||||
Should contain the I2C interrupt
|
||||
|
||||
- clock-frequency:
|
||||
This is the I2C bus clock. Need to be either 100000 or 400000
|
||||
|
||||
@ -21,6 +18,18 @@ Required properties:
|
||||
- #size-cells:
|
||||
Always 0
|
||||
|
||||
Optional properties:
|
||||
|
||||
- interrupts:
|
||||
Should contain the I2C interrupt. For certain revisions of the I2C
|
||||
controller, I2C interrupt is unwired to the interrupt controller. In such
|
||||
case, this property should be left unspecified, and driver will fall back
|
||||
to polling mode
|
||||
|
||||
- brcm,ape-hsls-addr-mask:
|
||||
Required for "brcm,iproc-nic-i2c". Host view of address mask into the
|
||||
'APE' co-processor. Value must be unsigned, 32-bit
|
||||
|
||||
Example:
|
||||
i2c0: i2c@18008000 {
|
||||
compatible = "brcm,iproc-i2c";
|
||||
|
@ -6,12 +6,21 @@ Required properties :
|
||||
or "mscc,ocelot-i2c" with "snps,designware-i2c" for fallback
|
||||
- reg : Offset and length of the register set for the device
|
||||
- interrupts : <IRQ> where IRQ is the interrupt number.
|
||||
- clocks : phandles for the clocks, see the description of clock-names below.
|
||||
The phandle for the "ic_clk" clock is required. The phandle for the "pclk"
|
||||
clock is optional. If a single clock is specified but no clock-name, it is
|
||||
the "ic_clk" clock. If both clocks are listed, the "ic_clk" must be first.
|
||||
|
||||
Recommended properties :
|
||||
|
||||
- clock-frequency : desired I2C bus clock frequency in Hz.
|
||||
|
||||
Optional properties :
|
||||
|
||||
- clock-names : Contains the names of the clocks:
|
||||
"ic_clk", for the core clock used to generate the external I2C clock.
|
||||
"pclk", the interface clock, required for register access.
|
||||
|
||||
- reg : for "mscc,ocelot-i2c", a second register set to configure the SDA hold
|
||||
time, named ICPU_CFG:TWI_DELAY in the datasheet.
|
||||
|
||||
|
@ -12,13 +12,16 @@ Required properties:
|
||||
"mediatek,mt7623-i2c", "mediatek,mt6577-i2c": for MediaTek MT7623
|
||||
"mediatek,mt7629-i2c", "mediatek,mt2712-i2c": for MediaTek MT7629
|
||||
"mediatek,mt8173-i2c": for MediaTek MT8173
|
||||
"mediatek,mt8183-i2c": for MediaTek MT8183
|
||||
"mediatek,mt8516-i2c", "mediatek,mt2712-i2c": for MediaTek MT8516
|
||||
- reg: physical base address of the controller and dma base, length of memory
|
||||
mapped region.
|
||||
- interrupts: interrupt number to the cpu.
|
||||
- clock-div: the fixed value for frequency divider of clock source in i2c
|
||||
module. Each IC may be different.
|
||||
- clocks: clock name from clock manager
|
||||
- clock-names: Must include "main" and "dma", if enable have-pmic need include
|
||||
- clock-names: Must include "main" and "dma", "arb" is for multi-master that
|
||||
one bus has more than two i2c controllers, if enable have-pmic need include
|
||||
"pmic" extra.
|
||||
|
||||
Optional properties:
|
||||
|
@ -1,7 +1,10 @@
|
||||
Device tree configuration for Renesas RIIC driver
|
||||
|
||||
Required properties:
|
||||
- compatible : "renesas,riic-<soctype>". "renesas,riic-rz" as fallback
|
||||
- compatible :
|
||||
"renesas,riic-r7s72100" if the device is a part of a R7S72100 SoC.
|
||||
"renesas,riic-r7s9210" if the device is a part of a R7S9210 SoC.
|
||||
"renesas,riic-rz" for a generic RZ/A compatible device.
|
||||
- reg : address start and address range size of device
|
||||
- interrupts : 8 interrupts (TEI, RI, TI, SPI, STI, NAKI, ALI, TMOI)
|
||||
- clock-frequency : frequency of bus clock in Hz
|
||||
|
@ -1,11 +1,11 @@
|
||||
* I2C controller embedded in STMicroelectronics STM32 I2C platform
|
||||
|
||||
Required properties :
|
||||
- compatible : Must be one of the following
|
||||
Required properties:
|
||||
- compatible: Must be one of the following
|
||||
- "st,stm32f4-i2c"
|
||||
- "st,stm32f7-i2c"
|
||||
- reg : Offset and length of the register set for the device
|
||||
- interrupts : Must contain the interrupt id for I2C event and then the
|
||||
- reg: Offset and length of the register set for the device
|
||||
- interrupts: Must contain the interrupt id for I2C event and then the
|
||||
interrupt id for I2C error.
|
||||
- resets: Must contain the phandle to the reset controller.
|
||||
- clocks: Must contain the input clock of the I2C instance.
|
||||
@ -14,25 +14,26 @@ Required properties :
|
||||
- #address-cells = <1>;
|
||||
- #size-cells = <0>;
|
||||
|
||||
Optional properties :
|
||||
- clock-frequency : Desired I2C bus clock frequency in Hz. If not specified,
|
||||
Optional properties:
|
||||
- clock-frequency: Desired I2C bus clock frequency in Hz. If not specified,
|
||||
the default 100 kHz frequency will be used.
|
||||
For STM32F4 SoC Standard-mode and Fast-mode are supported, possible values are
|
||||
100000 and 400000.
|
||||
For STM32F7 SoC, Standard-mode, Fast-mode and Fast-mode Plus are supported,
|
||||
possible values are 100000, 400000 and 1000000.
|
||||
- i2c-scl-rising-time-ns : Only for STM32F7, I2C SCL Rising time for the board
|
||||
(default: 25)
|
||||
- i2c-scl-falling-time-ns : Only for STM32F7, I2C SCL Falling time for the board
|
||||
(default: 10)
|
||||
For STM32F7, STM32H7 and STM32MP1 SoCs, Standard-mode, Fast-mode and Fast-mode
|
||||
Plus are supported, possible values are 100000, 400000 and 1000000.
|
||||
- i2c-scl-rising-time-ns: I2C SCL Rising time for the board (default: 25)
|
||||
For STM32F7, STM32H7 and STM32MP1 only.
|
||||
- i2c-scl-falling-time-ns: I2C SCL Falling time for the board (default: 10)
|
||||
For STM32F7, STM32H7 and STM32MP1 only.
|
||||
I2C Timings are derived from these 2 values
|
||||
- st,syscfg-fmp: Only for STM32F7, use to set Fast Mode Plus bit within SYSCFG
|
||||
whether Fast Mode Plus speed is selected by slave.
|
||||
1st cell : phandle to syscfg
|
||||
2nd cell : register offset within SYSCFG
|
||||
3rd cell : register bitmask for FMP bit
|
||||
- st,syscfg-fmp: Use to set Fast Mode Plus bit within SYSCFG when Fast Mode
|
||||
Plus speed is selected by slave.
|
||||
1st cell: phandle to syscfg
|
||||
2nd cell: register offset within SYSCFG
|
||||
3rd cell: register bitmask for FMP bit
|
||||
For STM32F7, STM32H7 and STM32MP1 only.
|
||||
|
||||
Example :
|
||||
Example:
|
||||
|
||||
i2c@40005400 {
|
||||
compatible = "st,stm32f4-i2c";
|
||||
|
17
Bindings/iio/accel/kionix,kxcjk1013.txt
Normal file
17
Bindings/iio/accel/kionix,kxcjk1013.txt
Normal file
@ -0,0 +1,17 @@
|
||||
Kionix KXCJK-1013 Accelerometer device tree bindings
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: Must be one of:
|
||||
"kionix,kxcjk1013"
|
||||
"kionix,kxcj91008"
|
||||
"kionix,kxtj21009"
|
||||
"kionix,kxtf9"
|
||||
- reg: i2c slave address
|
||||
|
||||
Example:
|
||||
|
||||
kxtf9@f {
|
||||
compatible = "kionix,kxtf9";
|
||||
reg = <0x0F>;
|
||||
};
|
@ -7,6 +7,7 @@ Required properties for the AD7606:
|
||||
* "adi,ad7606-8"
|
||||
* "adi,ad7606-6"
|
||||
* "adi,ad7606-4"
|
||||
* "adi,ad7616"
|
||||
- reg: SPI chip select number for the device
|
||||
- spi-max-frequency: Max SPI frequency to use
|
||||
see: Documentation/devicetree/bindings/spi/spi-bus.txt
|
||||
|
48
Bindings/iio/adc/adi,ad7780.txt
Normal file
48
Bindings/iio/adc/adi,ad7780.txt
Normal file
@ -0,0 +1,48 @@
|
||||
* Analog Devices AD7170/AD7171/AD7780/AD7781
|
||||
|
||||
Data sheets:
|
||||
|
||||
- AD7170:
|
||||
* https://www.analog.com/media/en/technical-documentation/data-sheets/AD7170.pdf
|
||||
- AD7171:
|
||||
* https://www.analog.com/media/en/technical-documentation/data-sheets/AD7171.pdf
|
||||
- AD7780:
|
||||
* https://www.analog.com/media/en/technical-documentation/data-sheets/ad7780.pdf
|
||||
- AD7781:
|
||||
* https://www.analog.com/media/en/technical-documentation/data-sheets/AD7781.pdf
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: should be one of
|
||||
* "adi,ad7170"
|
||||
* "adi,ad7171"
|
||||
* "adi,ad7780"
|
||||
* "adi,ad7781"
|
||||
- reg: spi chip select number for the device
|
||||
- vref-supply: the regulator supply for the ADC reference voltage
|
||||
|
||||
Optional properties:
|
||||
|
||||
- powerdown-gpios: must be the device tree identifier of the PDRST pin. If
|
||||
specified, it will be asserted during driver probe. As the
|
||||
line is active high, it should be marked GPIO_ACTIVE_HIGH.
|
||||
- adi,gain-gpios: must be the device tree identifier of the GAIN pin. Only for
|
||||
the ad778x chips. If specified, it will be asserted during
|
||||
driver probe. As the line is active low, it should be marked
|
||||
GPIO_ACTIVE_LOW.
|
||||
- adi,filter-gpios: must be the device tree identifier of the FILTER pin. Only
|
||||
for the ad778x chips. If specified, it will be asserted
|
||||
during driver probe. As the line is active low, it should be
|
||||
marked GPIO_ACTIVE_LOW.
|
||||
|
||||
Example:
|
||||
|
||||
adc@0 {
|
||||
compatible = "adi,ad7780";
|
||||
reg = <0>;
|
||||
vref-supply = <&vdd_supply>
|
||||
|
||||
powerdown-gpios = <&gpio 12 GPIO_ACTIVE_HIGH>;
|
||||
adi,gain-gpios = <&gpio 5 GPIO_ACTIVE_LOW>;
|
||||
adi,filter-gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
|
||||
};
|
@ -9,6 +9,7 @@ Required properties:
|
||||
- "amlogic,meson-gxl-saradc" for GXL
|
||||
- "amlogic,meson-gxm-saradc" for GXM
|
||||
- "amlogic,meson-axg-saradc" for AXG
|
||||
- "amlogic,meson-g12a-saradc" for AXG
|
||||
along with the generic "amlogic,meson-saradc"
|
||||
- reg: the physical base address and length of the registers
|
||||
- interrupts: the interrupt indicating end of sampling
|
||||
|
@ -1,24 +0,0 @@
|
||||
* AVIA HX711 ADC chip for weight cells
|
||||
Bit-banging driver
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "avia,hx711"
|
||||
- sck-gpios: Definition of the GPIO for the clock
|
||||
- dout-gpios: Definition of the GPIO for data-out
|
||||
See Documentation/devicetree/bindings/gpio/gpio.txt
|
||||
- avdd-supply: Definition of the regulator used as analog supply
|
||||
|
||||
Optional properties:
|
||||
- clock-frequency: Frequency of PD_SCK in Hz
|
||||
Minimum value allowed is 10 kHz because of maximum
|
||||
high time of 50 microseconds.
|
||||
|
||||
Example:
|
||||
weight {
|
||||
compatible = "avia,hx711";
|
||||
sck-gpios = <&gpio3 10 GPIO_ACTIVE_HIGH>;
|
||||
dout-gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>;
|
||||
avdd-suppy = <&avdd>;
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
66
Bindings/iio/adc/avia-hx711.yaml
Normal file
66
Bindings/iio/adc/avia-hx711.yaml
Normal file
@ -0,0 +1,66 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/iio/adc/avia-hx711.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
|
||||
title: AVIA HX711 ADC chip for weight cells
|
||||
|
||||
maintainers:
|
||||
- Andreas Klinger <ak@it-klinger.de>
|
||||
|
||||
description: |
|
||||
Bit-banging driver using two GPIOs:
|
||||
- sck-gpio gives a clock to the sensor with 24 cycles for data retrieval
|
||||
and up to 3 cycles for selection of the input channel and gain for the
|
||||
next measurement
|
||||
- dout-gpio is the sensor data the sensor responds to the clock
|
||||
|
||||
Specifications about the driver can be found at:
|
||||
http://www.aviaic.com/ENProducts.aspx
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- avia,hx711
|
||||
|
||||
sck-gpios:
|
||||
description:
|
||||
Definition of the GPIO for the clock (output). In the datasheet it is
|
||||
named PD_SCK
|
||||
maxItems: 1
|
||||
|
||||
dout-gpios:
|
||||
description:
|
||||
Definition of the GPIO for the data-out sent by the sensor in
|
||||
response to the clock (input).
|
||||
See Documentation/devicetree/bindings/gpio/gpio.txt for information
|
||||
on how to specify a consumer gpio.
|
||||
maxItems: 1
|
||||
|
||||
avdd-supply:
|
||||
description:
|
||||
Definition of the regulator used as analog supply
|
||||
maxItems: 1
|
||||
|
||||
clock-frequency:
|
||||
minimum: 20000
|
||||
maximum: 2500000
|
||||
default: 400000
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- sck-gpios
|
||||
- dout-gpios
|
||||
- avdd-supply
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
weight {
|
||||
compatible = "avia,hx711";
|
||||
sck-gpios = <&gpio3 10 GPIO_ACTIVE_HIGH>;
|
||||
dout-gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>;
|
||||
avdd-suppy = <&avdd>;
|
||||
clock-frequency = <100000>;
|
||||
};
|
@ -10,6 +10,7 @@ Required properties:
|
||||
- clocks: The root clock of the ADC controller
|
||||
- clock-names: Must contain "adc", matching entry in the clocks property
|
||||
- vref-supply: The regulator supply ADC reference voltage
|
||||
- #io-channel-cells: Must be 1 as per ../iio-bindings.txt
|
||||
|
||||
Example:
|
||||
adc1: adc@30610000 {
|
||||
@ -19,4 +20,5 @@ adc1: adc@30610000 {
|
||||
clocks = <&clks IMX7D_ADC_ROOT_CLK>;
|
||||
clock-names = "adc";
|
||||
vref-supply = <®_vcc_3v3_mcu>;
|
||||
#io-channel-cells = <1>;
|
||||
};
|
||||
|
@ -6,6 +6,10 @@ Required properties:
|
||||
region.
|
||||
- interrupts: The ADC interrupt
|
||||
|
||||
Optional:
|
||||
- vref-supply: The regulator supply ADC reference voltage, optional
|
||||
for legacy reason, but highly encouraging to us in new device tree
|
||||
|
||||
Example:
|
||||
|
||||
adc@40048000 {
|
||||
@ -13,4 +17,5 @@ Example:
|
||||
reg = <0x40048000 0x1000>;
|
||||
interrupt-parent = <&mic>;
|
||||
interrupts = <39 0>;
|
||||
vref-supply = <&vcc>;
|
||||
};
|
||||
|
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user