Add support for assembling and disassembling Intel Random Number
Generator extensions (e.g. the 'rdrand' mnemonic) to our copy of binutils. Approved by: re (kib) Obtained from: OpenBSD, via pfg MFC after: 1 week
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Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=256112
@ -6438,14 +6438,22 @@ VMX_Fixup (int extrachar ATTRIBUTE_UNUSED, int sizeflag)
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static void
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static void
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OP_VMX (int bytemode, int sizeflag)
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OP_VMX (int bytemode, int sizeflag)
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{
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{
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used_prefixes |= (prefixes & (PREFIX_DATA | PREFIX_REPZ));
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if (modrm.mod == 3)
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if (prefixes & PREFIX_DATA)
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{
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strcpy (obuf, "vmclear");
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strcpy (obuf, "rdrand");
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else if (prefixes & PREFIX_REPZ)
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OP_E (v_mode, sizeflag);
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strcpy (obuf, "vmxon");
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}
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else
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else
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strcpy (obuf, "vmptrld");
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{
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OP_E (bytemode, sizeflag);
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used_prefixes |= (prefixes & (PREFIX_DATA | PREFIX_REPZ));
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if (prefixes & PREFIX_DATA)
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strcpy (obuf, "vmclear");
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else if (prefixes & PREFIX_REPZ)
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strcpy (obuf, "vmxon");
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else
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strcpy (obuf, "vmptrld");
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OP_E (bytemode, sizeflag);
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}
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}
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}
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static void
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static void
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@ -79,6 +79,7 @@ typedef struct template
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#define CpuNo64 0x8000000 /* Not supported in the 64bit mode */
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#define CpuNo64 0x8000000 /* Not supported in the 64bit mode */
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#define CpuPCLMUL 0x10000000 /* Carry-less Multiplication extensions */
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#define CpuPCLMUL 0x10000000 /* Carry-less Multiplication extensions */
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#define CpuRdRnd 0x20000000 /* Intel Random Number Generator extensions */
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/* SSE4.1/4.2 Instructions required */
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/* SSE4.1/4.2 Instructions required */
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#define CpuSSE4 (CpuSSE4_1|CpuSSE4_2)
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#define CpuSSE4 (CpuSSE4_1|CpuSSE4_2)
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@ -87,7 +88,7 @@ typedef struct template
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#define CpuUnknownFlags (Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686 \
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#define CpuUnknownFlags (Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686 \
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|CpuP4|CpuSledgehammer|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuVMX \
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|CpuP4|CpuSledgehammer|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuVMX \
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|Cpu3dnow|Cpu3dnowA|CpuK6|CpuPadLock|CpuSVME|CpuSSSE3|CpuSSE4_1 \
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|Cpu3dnow|Cpu3dnowA|CpuK6|CpuPadLock|CpuSVME|CpuSSSE3|CpuSSE4_1 \
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|CpuSSE4_2|CpuABM|CpuSSE4a|CpuXSAVE|CpuAES|CpuPCLMUL)
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|CpuSSE4_2|CpuABM|CpuSSE4a|CpuXSAVE|CpuAES|CpuPCLMUL|CpuRdRnd)
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/* the bits in opcode_modifier are used to generate the final opcode from
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/* the bits in opcode_modifier are used to generate the final opcode from
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the base_opcode. These bits also are used to detect alternate forms of
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the base_opcode. These bits also are used to detect alternate forms of
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@ -1502,3 +1502,21 @@ xrstor, 1, 0xfae, 0x5, CpuXSAVE, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf,
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// INVPCID
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// INVPCID
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invpcid, 2, 0x660f3882, None, CpuNo64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32 }
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invpcid, 2, 0x660f3882, None, CpuNo64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32 }
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invpcid, 2, 0x660f3882, None, Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg64 }
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invpcid, 2, 0x660f3882, None, Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg64 }
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// Intel AES extensions
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aesdec, 2, 0x660f38de, None, CpuAES, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegXMM|LLongMem, RegXMM }
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aesdeclast, 2, 0x660f38df, None, CpuAES, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegXMM|LLongMem, RegXMM }
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aesenc, 2, 0x660f38dc, None, CpuAES, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegXMM|LLongMem, RegXMM }
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aesenclast, 2, 0x660f38dd, None, CpuAES, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegXMM|LLongMem, RegXMM }
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aesimc, 2, 0x660f38db, None, CpuAES, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegXMM|LLongMem, RegXMM }
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aeskeygenassist, 3, 0x660f3adf, None, CpuAES, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, RegXMM|LLongMem, RegXMM }
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// Intel Carry-less Multiplication extensions
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pclmulqdq, 3, 0x660f3a44, None, CpuPCLMUL, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, RegXMM|LLongMem, RegXMM }
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pclmullqlqdq, 2, 0x660f3a44, 0x0, CpuPCLMUL, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { RegXMM|LLongMem, RegXMM }
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pclmulhqlqdq, 2, 0x660f3a44, 0x1, CpuPCLMUL, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { RegXMM|LLongMem, RegXMM }
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pclmullqhqdq, 2, 0x660f3a44, 0x10, CpuPCLMUL, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { RegXMM|LLongMem, RegXMM }
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pclmulhqhqdq, 2, 0x660f3a44, 0x11, CpuPCLMUL, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { RegXMM|LLongMem, RegXMM }
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// Intel Random Number Generator extensions
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rdrand, 1, 0x0fc7, 0x6, CpuRdRnd, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg16|Reg32|Reg64 }
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@ -4374,6 +4374,11 @@ const template i386_optab[] =
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Modrm|IgnoreSize|NoSuf|ImmExt,
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Modrm|IgnoreSize|NoSuf|ImmExt,
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{ RegXMM|LLongMem,
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{ RegXMM|LLongMem,
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RegXMM } },
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RegXMM } },
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/* Intel Random Number Generator extensions */
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{"rdrand", 1, 0x0fc7, 0x6, CpuRdRnd,
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Modrm|NoSuf,
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{ Reg16|Reg32|Reg64 } },
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{ NULL, 0, 0, 0, 0, 0, { 0 } }
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{ NULL, 0, 0, 0, 0, 0, { 0 } }
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};
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};
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