arm64: rockchip: Correctly set armclk
Parent needs to be the same frequency as the armclk, not twice the freq. The real divider is incremented by one so write it with - 1 The rate can be at index 0 Pointy Hat To: myself
This commit is contained in:
parent
6ee7d5afcc
commit
e34425be26
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=334996
@ -154,12 +154,13 @@ rk_clk_armclk_set_freq(struct clknode *clk, uint64_t fparent, uint64_t *fout,
|
|||||||
if (sc->rates[i].freq == *fout) {
|
if (sc->rates[i].freq == *fout) {
|
||||||
best = sc->rates[i].freq;
|
best = sc->rates[i].freq;
|
||||||
div = sc->rates[i].div;
|
div = sc->rates[i].div;
|
||||||
best_p = best * (div + 1);
|
best_p = best * div;
|
||||||
rate = i;
|
rate = i;
|
||||||
|
break;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
if (rate == 0)
|
if (rate == sc->nrates)
|
||||||
return (0);
|
return (0);
|
||||||
|
|
||||||
err = clknode_set_freq(p_main, best_p, 0, 1);
|
err = clknode_set_freq(p_main, best_p, 0, 1);
|
||||||
@ -177,7 +178,7 @@ rk_clk_armclk_set_freq(struct clknode *clk, uint64_t fparent, uint64_t *fout,
|
|||||||
DEVICE_LOCK(clk);
|
DEVICE_LOCK(clk);
|
||||||
READ4(clk, sc->muxdiv_offset, &val);
|
READ4(clk, sc->muxdiv_offset, &val);
|
||||||
val &= ~sc->div_mask;
|
val &= ~sc->div_mask;
|
||||||
val |= div << sc->div_shift;
|
val |= (div - 1) << sc->div_shift;
|
||||||
WRITE4(clk, sc->muxdiv_offset, val | RK_CLK_ARMCLK_MASK);
|
WRITE4(clk, sc->muxdiv_offset, val | RK_CLK_ARMCLK_MASK);
|
||||||
DEVICE_UNLOCK(clk);
|
DEVICE_UNLOCK(clk);
|
||||||
|
|
||||||
|
Loading…
Reference in New Issue
Block a user