Import device-tree files from Linux 5.17
Sponsored by: Beckhoff Automation GmbH & Co. KG
This commit is contained in:
Emmanuel Vadot
commit
e67e85659c
@ -65,7 +65,9 @@ DT_DOCS = $(patsubst $(srctree)/%,%,$(shell $(find_all_cmd)))
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override DTC_FLAGS := \
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-Wno-avoid_unnecessary_addr_size \
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-Wno-graph_child_address \
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-Wno-interrupt_provider
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-Wno-interrupt_provider \
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-Wno-unique_unit_address \
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-Wunique_unit_address_if_enabled
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# Disable undocumented compatible checks until warning free
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override DT_CHECKER_FLAGS ?=
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@ -12,12 +12,19 @@ maintainers:
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description: |
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ARM platforms using SoCs designed by Apple Inc., branded "Apple Silicon".
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This currently includes devices based on the "M1" SoC, starting with the
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three Mac models released in late 2020:
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This currently includes devices based on the "M1" SoC:
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- Mac mini (M1, 2020)
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- MacBook Pro (13-inch, M1, 2020)
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- MacBook Air (M1, 2020)
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- iMac (24-inch, M1, 2021)
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And devices based on the "M1 Pro" and "M1 Max" SoCs:
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- MacBook Pro (14-inch, M1 Pro, 2021)
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- MacBook Pro (14-inch, M1 Max, 2021)
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- MacBook Pro (16-inch, M1 Pro, 2021)
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- MacBook Pro (16-inch, M1 Max, 2021)
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The compatible property should follow this format:
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@ -56,8 +63,24 @@ properties:
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- apple,j274 # Mac mini (M1, 2020)
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- apple,j293 # MacBook Pro (13-inch, M1, 2020)
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- apple,j313 # MacBook Air (M1, 2020)
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- apple,j456 # iMac (24-inch, 4x USB-C, M1, 2021)
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- apple,j457 # iMac (24-inch, 2x USB-C, M1, 2021)
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- const: apple,t8103
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- const: apple,arm-platform
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- description: Apple M1 Pro SoC based platforms
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items:
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- enum:
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- apple,j314s # MacBook Pro (14-inch, M1 Pro, 2021)
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- apple,j316s # MacBook Pro (16-inch, M1 Pro, 2021)
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- const: apple,t6000
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- const: apple,arm-platform
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- description: Apple M1 Max SoC based platforms
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items:
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- enum:
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- apple,j314c # MacBook Pro (14-inch, M1 Max, 2021)
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- apple,j316c # MacBook Pro (16-inch, M1 Max, 2021)
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- const: apple,t6001
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- const: apple,arm-platform
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additionalProperties: true
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134
sys/contrib/device-tree/Bindings/arm/apple/apple,pmgr.yaml
Normal file
134
sys/contrib/device-tree/Bindings/arm/apple/apple,pmgr.yaml
Normal file
@ -0,0 +1,134 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/arm/apple/apple,pmgr.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Apple SoC Power Manager (PMGR)
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maintainers:
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- Hector Martin <marcan@marcan.st>
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description: |
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Apple SoCs include PMGR blocks responsible for power management,
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which can control various clocks, resets, power states, and
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performance features. This node represents the PMGR as a syscon,
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with sub-nodes representing individual features.
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properties:
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$nodename:
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pattern: "^power-management@[0-9a-f]+$"
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compatible:
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items:
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- enum:
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- apple,t8103-pmgr
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- apple,t6000-pmgr
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- const: apple,pmgr
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- const: syscon
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- const: simple-mfd
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reg:
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maxItems: 1
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"#address-cells":
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const: 1
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"#size-cells":
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const: 1
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patternProperties:
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"power-controller@[0-9a-f]+$":
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description:
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The individual power management domains within this controller
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type: object
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$ref: /power/apple,pmgr-pwrstate.yaml#
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required:
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- compatible
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- reg
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additionalProperties: false
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examples:
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- |
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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power-management@23b700000 {
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compatible = "apple,t8103-pmgr", "apple,pmgr", "syscon", "simple-mfd";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x2 0x3b700000 0x0 0x14000>;
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ps_sio: power-controller@1c0 {
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compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
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reg = <0x1c0 8>;
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#power-domain-cells = <0>;
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#reset-cells = <0>;
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label = "sio";
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apple,always-on;
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};
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ps_uart_p: power-controller@220 {
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compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
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reg = <0x220 8>;
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#power-domain-cells = <0>;
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#reset-cells = <0>;
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label = "uart_p";
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power-domains = <&ps_sio>;
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};
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ps_uart0: power-controller@270 {
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compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
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reg = <0x270 8>;
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#power-domain-cells = <0>;
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#reset-cells = <0>;
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label = "uart0";
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power-domains = <&ps_uart_p>;
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};
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};
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power-management@23d280000 {
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compatible = "apple,t8103-pmgr", "apple,pmgr", "syscon", "simple-mfd";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x2 0x3d280000 0x0 0xc000>;
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ps_aop_filter: power-controller@4000 {
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compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
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reg = <0x4000 8>;
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#power-domain-cells = <0>;
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#reset-cells = <0>;
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label = "aop_filter";
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};
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ps_aop_base: power-controller@4010 {
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compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
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reg = <0x4010 8>;
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#power-domain-cells = <0>;
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#reset-cells = <0>;
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label = "aop_base";
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power-domains = <&ps_aop_filter>;
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};
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ps_aop_shim: power-controller@4038 {
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compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
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reg = <0x4038 8>;
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#power-domain-cells = <0>;
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#reset-cells = <0>;
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label = "aop_shim";
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power-domains = <&ps_aop_base>;
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};
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ps_aop_uart0: power-controller@4048 {
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compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
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reg = <0x4048 8>;
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#power-domain-cells = <0>;
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#reset-cells = <0>;
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label = "aop_uart0";
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power-domains = <&ps_aop_shim>;
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};
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};
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};
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@ -166,16 +166,6 @@ examples:
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};
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};
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dma0: dma@3000000 {
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/* compatible = "arm,pl330", "arm,primecell"; */
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cci-control-port = <&cci_control0>;
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reg = <0x0 0x3000000 0x0 0x1000>;
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interrupts = <10>;
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#dma-cells = <1>;
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#dma-channels = <8>;
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#dma-requests = <32>;
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};
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cci@2c090000 {
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compatible = "arm,cci-400";
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#address-cells = <1>;
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37
sys/contrib/device-tree/Bindings/arm/aspeed/aspeed,sbc.yaml
Normal file
37
sys/contrib/device-tree/Bindings/arm/aspeed/aspeed,sbc.yaml
Normal file
@ -0,0 +1,37 @@
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# SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
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# Copyright 2021 Joel Stanley, IBM Corp.
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/arm/aspeed/aspeed,sbc.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: ASPEED Secure Boot Controller
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maintainers:
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- Joel Stanley <joel@jms.id.au>
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- Andrew Jeffery <andrew@aj.id.au>
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description: |
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The ASPEED SoCs have a register bank for interacting with the secure boot
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controller.
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properties:
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compatible:
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items:
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- const: aspeed,ast2600-sbc
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reg:
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maxItems: 1
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required:
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- compatible
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- reg
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additionalProperties: false
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examples:
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- |
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sbc: secure-boot-controller@1e6f2000 {
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compatible = "aspeed,ast2600-sbc";
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reg = <0x1e6f2000 0x1000>;
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};
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@ -8,7 +8,8 @@ title: Atmel AT91 device tree bindings.
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maintainers:
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- Alexandre Belloni <alexandre.belloni@bootlin.com>
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- Ludovic Desroches <ludovic.desroches@microchip.com>
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- Claudiu Beznea <claudiu.beznea@microchip.com>
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- Nicolas Ferre <nicolas.ferre@microchip.com>
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description: |
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Boards with a SoC of the Atmel AT91 or SMART family shall have the following
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@ -29,6 +29,7 @@ properties:
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items:
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- enum:
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- asus,gt-ac5300
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- netgear,raxe500
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- const: brcm,bcm4908
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- description: BCM49408 based boards
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@ -137,6 +137,9 @@ properties:
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- arm,cortex-a75
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- arm,cortex-a76
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- arm,cortex-a77
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- arm,cortex-a78
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- arm,cortex-a510
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- arm,cortex-a710
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- arm,cortex-m0
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- arm,cortex-m0+
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- arm,cortex-m1
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@ -145,8 +148,12 @@ properties:
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- arm,cortex-r4
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- arm,cortex-r5
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- arm,cortex-r7
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- arm,cortex-x1
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- arm,cortex-x2
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- arm,neoverse-e1
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- arm,neoverse-n1
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- arm,neoverse-n2
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- arm,neoverse-v1
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- brcm,brahma-b15
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- brcm,brahma-b53
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- brcm,vulcan
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@ -174,6 +181,7 @@ properties:
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- qcom,kryo560
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- qcom,kryo570
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- qcom,kryo685
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- qcom,kryo780
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- qcom,scorpion
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enable-method:
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@ -24,6 +24,12 @@ properties:
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compatible:
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const: linaro,optee-tz
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interrupts:
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maxItems: 1
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description: |
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This interrupt which is used to signal an event by the secure world
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software is expected to be edge-triggered.
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method:
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enum: [smc, hvc]
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description: |
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@ -42,10 +48,12 @@ additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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firmware {
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optee {
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compatible = "linaro,optee-tz";
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method = "smc";
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interrupts = <GIC_SPI 187 IRQ_TYPE_EDGE_RISING>;
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};
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};
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@ -8,7 +8,7 @@ Required properties:
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- compatible: Should contain a chip-specific compatible string,
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Chip-specific strings are of the form "fsl,<chip>-dcfg",
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The following <chip>s are known to be supported:
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ls1012a, ls1021a, ls1043a, ls1046a, ls2080a.
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ls1012a, ls1021a, ls1043a, ls1046a, ls2080a, lx2160a
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- reg : should contain base address and length of DCFG memory-mapped registers
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@ -240,6 +240,7 @@ properties:
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- uniwest,imx6q-evi # Uniwest Evi
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- variscite,dt6customboard
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- wand,imx6q-wandboard # Wandboard i.MX6 Quad Board
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- ysoft,imx6q-yapp4-crux # i.MX6 Quad Y Soft IOTA Crux board
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- zealz,imx6q-gk802 # Zealz GK802
|
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- zii,imx6q-zii-rdu2 # ZII RDU2 Board
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- const: fsl,imx6q
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@ -323,6 +324,20 @@ properties:
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- const: toradex,apalis_imx6q
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- const: fsl,imx6q
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- description: TQ-Systems TQMa6Q SoM (variant A) on MBa6x
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items:
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- const: tq,imx6q-mba6x-a
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- const: tq,mba6a # Expected by bootloader, to be removed in the future
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- const: tq,imx6q-tqma6q-a
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- const: fsl,imx6q
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- description: TQ-Systems TQMa6Q SoM (variant B) on MBa6x
|
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items:
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- const: tq,imx6q-mba6x-b
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- const: tq,mba6b # Expected by bootloader, to be removed in the future
|
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- const: tq,imx6q-tqma6q-b
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- const: fsl,imx6q
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||||
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- description: i.MX6QP based Boards
|
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items:
|
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- enum:
|
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@ -334,6 +349,7 @@ properties:
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- kvg,vicutp # Kverneland UT1P board
|
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- prt,prtwd3 # Protonic WD3 board
|
||||
- wand,imx6qp-wandboard # Wandboard i.MX6 QuadPlus Board
|
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- ysoft,imx6qp-yapp4-crux-plus # i.MX6 Quad Plus Y Soft IOTA Crux+ board
|
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- zii,imx6qp-zii-rdu2 # ZII RDU2+ Board
|
||||
- const: fsl,imx6qp
|
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|
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@ -344,6 +360,13 @@ properties:
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- const: phytec,imx6qdl-pcm058 # PHYTEC phyCORE-i.MX6
|
||||
- const: fsl,imx6qp
|
||||
|
||||
- description: TQ-Systems TQMa6QP SoM on MBa6x
|
||||
items:
|
||||
- const: tq,imx6qp-mba6x-b
|
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- const: tq,mba6b # Expected by bootloader, to be removed in the future
|
||||
- const: tq,imx6qp-tqma6qp-b
|
||||
- const: fsl,imx6qp
|
||||
|
||||
- description: i.MX6DL based Boards
|
||||
items:
|
||||
- enum:
|
||||
@ -482,6 +505,20 @@ properties:
|
||||
- const: dh,imx6s-dhcom-som
|
||||
- const: fsl,imx6dl
|
||||
|
||||
- description: TQ-Systems TQMa6DL SoM (variant A) on MBa6x
|
||||
items:
|
||||
- const: tq,imx6dl-mba6x-a
|
||||
- const: tq,mba6a # Expected by bootloader, to be removed in the future
|
||||
- const: tq,imx6dl-tqma6dl-a
|
||||
- const: fsl,imx6dl
|
||||
|
||||
- description: TQ-Systems TQMa6DL SoM (variant B) on MBa6x
|
||||
items:
|
||||
- const: tq,imx6dl-mba6x-b
|
||||
- const: tq,mba6b # Expected by bootloader, to be removed in the future
|
||||
- const: tq,imx6dl-tqma6dl-b
|
||||
- const: fsl,imx6dl
|
||||
|
||||
- description: i.MX6SL based Boards
|
||||
items:
|
||||
- enum:
|
||||
@ -580,6 +617,7 @@ properties:
|
||||
items:
|
||||
- enum:
|
||||
- fsl,imx6ull-14x14-evk # i.MX6 UltraLiteLite 14x14 EVK Board
|
||||
- joz,jozacp # JOZ Access Point
|
||||
- kontron,imx6ull-n6411-som # Kontron N6411 SOM
|
||||
- myir,imx6ull-mys-6ulx-eval # MYiR Tech iMX6ULL Evaluation Board
|
||||
- toradex,colibri-imx6ull # Colibri iMX6ULL Modules
|
||||
@ -632,6 +670,7 @@ properties:
|
||||
- description: i.MX6ULZ based Boards
|
||||
items:
|
||||
- enum:
|
||||
- bsh,imx6ulz-bsh-smm-m2 # i.MX6 ULZ BSH SystemMaster
|
||||
- fsl,imx6ulz-14x14-evk # i.MX6 ULZ 14x14 EVK Board
|
||||
- const: fsl,imx6ull # This seems odd. Should be last?
|
||||
- const: fsl,imx6ulz
|
||||
@ -754,10 +793,23 @@ properties:
|
||||
- const: variscite,var-som-mx8mm
|
||||
- const: fsl,imx8mm
|
||||
|
||||
- description:
|
||||
TQMa8MxML is a series of SOM featuring NXP i.MX8MM system-on-chip
|
||||
variants. It is designed to be soldered on different carrier boards.
|
||||
All variants (TQMa8M[Q,D,S][L]ML) use the same device tree, hence only
|
||||
one compatible is needed.
|
||||
items:
|
||||
- enum:
|
||||
- tq,imx8mm-tqma8mqml-mba8mx # TQ-Systems GmbH i.MX8MM TQMa8MQML SOM on MBa8Mx
|
||||
- const: tq,imx8mm-tqma8mqml # TQ-Systems GmbH i.MX8MM TQMa8MQML SOM
|
||||
- const: fsl,imx8mm
|
||||
|
||||
- description: i.MX8MN based Boards
|
||||
items:
|
||||
- enum:
|
||||
- beacon,imx8mn-beacon-kit # i.MX8MN Beacon Development Kit
|
||||
- bsh,imx8mn-bsh-smm-s2 # i.MX8MN BSH SystemMaster S2
|
||||
- bsh,imx8mn-bsh-smm-s2pro # i.MX8MN BSH SystemMaster S2 PRO
|
||||
- fsl,imx8mn-ddr4-evk # i.MX8MN DDR4 EVK Board
|
||||
- fsl,imx8mn-evk # i.MX8MN LPDDR4 EVK Board
|
||||
- gw,imx8mn-gw7902 # i.MX8MM Gateworks Board
|
||||
@ -769,6 +821,17 @@ properties:
|
||||
- const: variscite,var-som-mx8mn
|
||||
- const: fsl,imx8mn
|
||||
|
||||
- description:
|
||||
TQMa8MxNL is a series of SOM featuring NXP i.MX8MN system-on-chip
|
||||
variants. It is designed to be soldered on different carrier boards.
|
||||
All variants (TQMa8M[Q,D,S][L]NL) use the same device tree, hence only
|
||||
one compatible is needed.
|
||||
items:
|
||||
- enum:
|
||||
- tq,imx8mn-tqma8mqnl-mba8mx # TQ-Systems GmbH i.MX8MN TQMa8MQNL SOM on MBa8Mx
|
||||
- const: tq,imx8mn-tqma8mqnl # TQ-Systems GmbH i.MX8MN TQMa8MQNL SOM
|
||||
- const: fsl,imx8mn
|
||||
|
||||
- description: i.MX8MP based Boards
|
||||
items:
|
||||
- enum:
|
||||
@ -805,6 +868,15 @@ properties:
|
||||
- const: purism,librem5
|
||||
- const: fsl,imx8mq
|
||||
|
||||
- description:
|
||||
TQMa8Mx is a series of SOM featuring NXP i.MX8MQ system-on-chip
|
||||
variants. It is designed to be clicked on different carrier boards.
|
||||
items:
|
||||
- enum:
|
||||
- tq,imx8mq-tqma8mq-mba8mx # TQ-Systems GmbH i.MX8MQ TQMa8Mx SOM on MBa8Mx
|
||||
- const: tq,imx8mq-tqma8mq # TQ-Systems GmbH i.MX8MQ TQMa8Mx SOM
|
||||
- const: fsl,imx8mq
|
||||
|
||||
- description: Zodiac Inflight Innovations Ultra Boards
|
||||
items:
|
||||
- enum:
|
||||
@ -834,6 +906,12 @@ properties:
|
||||
- const: toradex,colibri-imx8x
|
||||
- const: fsl,imx8qxp
|
||||
|
||||
- description: i.MX8ULP based Boards
|
||||
items:
|
||||
- enum:
|
||||
- fsl,imx8ulp-evk # i.MX8ULP EVK Board
|
||||
- const: fsl,imx8ulp
|
||||
|
||||
- description:
|
||||
Freescale Vybrid Platform Device Tree Bindings
|
||||
|
||||
|
||||
@ -77,6 +77,14 @@ properties:
|
||||
- enum:
|
||||
- mediatek,mt7629-rfb
|
||||
- const: mediatek,mt7629
|
||||
- items:
|
||||
- enum:
|
||||
- mediatek,mt7986a-rfb
|
||||
- const: mediatek,mt7986a
|
||||
- items:
|
||||
- enum:
|
||||
- mediatek,mt7986b-rfb
|
||||
- const: mediatek,mt7986b
|
||||
- items:
|
||||
- enum:
|
||||
- mediatek,mt8127-moose
|
||||
@ -134,6 +142,10 @@ properties:
|
||||
- google,krane-sku176
|
||||
- const: google,krane
|
||||
- const: mediatek,mt8183
|
||||
- description: Google Cozmo (Acer Chromebook 314)
|
||||
items:
|
||||
- const: google,cozmo
|
||||
- const: mediatek,mt8183
|
||||
- description: Google Damu (ASUS Chromebook Flip CM3)
|
||||
items:
|
||||
- const: google,damu
|
||||
@ -143,7 +155,9 @@ properties:
|
||||
- enum:
|
||||
- google,fennel-sku0
|
||||
- google,fennel-sku1
|
||||
- google,fennel-sku2
|
||||
- google,fennel-sku6
|
||||
- google,fennel-sku7
|
||||
- const: google,fennel
|
||||
- const: mediatek,mt8183
|
||||
- description: Google Juniper (Acer Chromebook Spin 311) / Kenzo (Acer Chromebook 311)
|
||||
@ -159,6 +173,12 @@ properties:
|
||||
- const: google,kakadu-rev2
|
||||
- const: google,kakadu
|
||||
- const: mediatek,mt8183
|
||||
- description: Google Kakadu (ASUS Chromebook Detachable CM3)
|
||||
items:
|
||||
- const: google,kakadu-rev3-sku22
|
||||
- const: google,kakadu-rev2-sku22
|
||||
- const: google,kakadu
|
||||
- const: mediatek,mt8183
|
||||
- description: Google Kappa (HP Chromebook 11a)
|
||||
items:
|
||||
- const: google,kappa
|
||||
|
||||
@ -14,6 +14,7 @@ Required Properties:
|
||||
- "mediatek,mt7622-apmixedsys"
|
||||
- "mediatek,mt7623-apmixedsys", "mediatek,mt2701-apmixedsys"
|
||||
- "mediatek,mt7629-apmixedsys"
|
||||
- "mediatek,mt7986-apmixedsys"
|
||||
- "mediatek,mt8135-apmixedsys"
|
||||
- "mediatek,mt8167-apmixedsys", "syscon"
|
||||
- "mediatek,mt8173-apmixedsys"
|
||||
|
||||
@ -10,6 +10,7 @@ Required Properties:
|
||||
- "mediatek,mt7622-ethsys", "syscon"
|
||||
- "mediatek,mt7623-ethsys", "mediatek,mt2701-ethsys", "syscon"
|
||||
- "mediatek,mt7629-ethsys", "syscon"
|
||||
- "mediatek,mt7986-ethsys", "syscon"
|
||||
- #clock-cells: Must be 1
|
||||
- #reset-cells: Must be 1
|
||||
|
||||
|
||||
@ -15,6 +15,7 @@ Required Properties:
|
||||
- "mediatek,mt7622-infracfg", "syscon"
|
||||
- "mediatek,mt7623-infracfg", "mediatek,mt2701-infracfg", "syscon"
|
||||
- "mediatek,mt7629-infracfg", "syscon"
|
||||
- "mediatek,mt7986-infracfg", "syscon"
|
||||
- "mediatek,mt8135-infracfg", "syscon"
|
||||
- "mediatek,mt8167-infracfg", "syscon"
|
||||
- "mediatek,mt8173-infracfg", "syscon"
|
||||
|
||||
@ -8,6 +8,8 @@ Required Properties:
|
||||
- compatible: Should be:
|
||||
- "mediatek,mt7622-sgmiisys", "syscon"
|
||||
- "mediatek,mt7629-sgmiisys", "syscon"
|
||||
- "mediatek,mt7986-sgmiisys_0", "syscon"
|
||||
- "mediatek,mt7986-sgmiisys_1", "syscon"
|
||||
- #clock-cells: Must be 1
|
||||
|
||||
The SGMIISYS controller uses the common clk binding from
|
||||
|
||||
@ -14,6 +14,7 @@ Required Properties:
|
||||
- "mediatek,mt7622-topckgen"
|
||||
- "mediatek,mt7623-topckgen", "mediatek,mt2701-topckgen"
|
||||
- "mediatek,mt7629-topckgen"
|
||||
- "mediatek,mt7986-topckgen", "syscon"
|
||||
- "mediatek,mt8135-topckgen"
|
||||
- "mediatek,mt8167-topckgen", "syscon"
|
||||
- "mediatek,mt8173-topckgen"
|
||||
|
||||
@ -24,6 +24,7 @@ properties:
|
||||
- qcom,sc7180-llcc
|
||||
- qcom,sc7280-llcc
|
||||
- qcom,sdm845-llcc
|
||||
- qcom,sm6350-llcc
|
||||
- qcom,sm8150-llcc
|
||||
- qcom,sm8250-llcc
|
||||
|
||||
@ -44,7 +45,6 @@ required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- interrupts
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
|
||||
@ -119,6 +119,9 @@ Boards (incomplete list of examples):
|
||||
- OMAP3 BeagleBoard : Low cost community board
|
||||
compatible = "ti,omap3-beagle", "ti,omap3430", "ti,omap3"
|
||||
|
||||
- OMAP3 BeagleBoard A to B4 : Early BeagleBoard revisions A to B4 with a timer quirk
|
||||
compatible = "ti,omap3-beagle-ab4", "ti,omap3-beagle", "ti,omap3430", "ti,omap3"
|
||||
|
||||
- OMAP3 Tobi with Overo : Commercial expansion board with daughter board
|
||||
compatible = "gumstix,omap3-overo-tobi", "gumstix,omap3-overo", "ti,omap3430", "ti,omap3"
|
||||
|
||||
|
||||
@ -44,10 +44,18 @@ properties:
|
||||
- arm,cortex-a76-pmu
|
||||
- arm,cortex-a77-pmu
|
||||
- arm,cortex-a78-pmu
|
||||
- arm,cortex-a510-pmu
|
||||
- arm,cortex-a710-pmu
|
||||
- arm,cortex-x1-pmu
|
||||
- arm,cortex-x2-pmu
|
||||
- arm,neoverse-e1-pmu
|
||||
- arm,neoverse-n1-pmu
|
||||
- arm,neoverse-n2-pmu
|
||||
- arm,neoverse-v1-pmu
|
||||
- brcm,vulcan-pmu
|
||||
- cavium,thunder-pmu
|
||||
- nvidia,denver-pmu
|
||||
- nvidia,carmel-pmu
|
||||
- qcom,krait-pmu
|
||||
- qcom,scorpion-pmu
|
||||
- qcom,scorpion-mp-pmu
|
||||
|
||||
@ -50,6 +50,7 @@ description: |
|
||||
sm8150
|
||||
sm8250
|
||||
sm8350
|
||||
sm8450
|
||||
|
||||
The 'board' element must be one of the following strings:
|
||||
|
||||
@ -201,8 +202,10 @@ properties:
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,sc7280-crd
|
||||
- qcom,sc7280-idp
|
||||
- qcom,sc7280-idp2
|
||||
- google,hoglin
|
||||
- google,piglin
|
||||
- google,senor
|
||||
- const: qcom,sc7280
|
||||
@ -257,6 +260,11 @@ properties:
|
||||
- qcom,sm8350-mtp
|
||||
- const: qcom,sm8350
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,sm8450-qrd
|
||||
- const: qcom,sm8450
|
||||
|
||||
additionalProperties: true
|
||||
|
||||
...
|
||||
|
||||
@ -315,6 +315,18 @@ properties:
|
||||
- const: renesas,falcon-cpu
|
||||
- const: renesas,r8a779a0
|
||||
|
||||
- description: R-Car S4-8 (R8A779F0)
|
||||
items:
|
||||
- enum:
|
||||
- renesas,spider-cpu # Spider CPU board (RTP8A779F0ASKB0SC2S)
|
||||
- const: renesas,r8a779f0
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- renesas,spider-breakout # Spider BreakOut board (RTP8A779F0ASKB0SB0S)
|
||||
- const: renesas,spider-cpu
|
||||
- const: renesas,r8a779f0
|
||||
|
||||
- description: R-Car H3e (R8A779M0)
|
||||
items:
|
||||
- enum:
|
||||
|
||||
@ -199,6 +199,18 @@ properties:
|
||||
- samsung,exynos7-espresso # Samsung Exynos7 Espresso
|
||||
- const: samsung,exynos7
|
||||
|
||||
- description: Exynos7885 based boards
|
||||
items:
|
||||
- enum:
|
||||
- samsung,jackpotlte # Samsung Galaxy A8 (2018)
|
||||
- const: samsung,exynos7885
|
||||
|
||||
- description: Exynos850 based boards
|
||||
items:
|
||||
- enum:
|
||||
- winlink,e850-96 # WinLink E850-96
|
||||
- const: samsung,exynos850
|
||||
|
||||
- description: Exynos Auto v9 based boards
|
||||
items:
|
||||
- enum:
|
||||
|
||||
@ -77,6 +77,7 @@ properties:
|
||||
items:
|
||||
- enum:
|
||||
- engicam,icore-stm32mp1-ctouch2 # STM32MP1 Engicam i.Core STM32MP1 C.TOUCH 2.0
|
||||
- engicam,icore-stm32mp1-ctouch2-of10 # STM32MP1 Engicam i.Core STM32MP1 C.TOUCH 2.0 10.1" OF
|
||||
- engicam,icore-stm32mp1-edimm2.2 # STM32MP1 Engicam i.Core STM32MP1 EDIMM2.2 Starter Kit
|
||||
- const: engicam,icore-stm32mp1 # STM32MP1 Engicam i.Core STM32MP1 SoM
|
||||
- const: st,stm32mp157
|
||||
|
||||
@ -808,6 +808,11 @@ properties:
|
||||
- const: oranth,tanix-tx6
|
||||
- const: allwinner,sun50i-h6
|
||||
|
||||
- description: Tanix TX6 mini
|
||||
items:
|
||||
- const: oranth,tanix-tx6-mini
|
||||
- const: allwinner,sun50i-h6
|
||||
|
||||
- description: TBS A711 Tablet
|
||||
items:
|
||||
- const: tbs-biometrics,a711
|
||||
|
||||
@ -32,12 +32,38 @@ properties:
|
||||
- allwinner,sun8i-h3-mbus
|
||||
- allwinner,sun8i-r40-mbus
|
||||
- allwinner,sun50i-a64-mbus
|
||||
- allwinner,sun50i-h5-mbus
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
minItems: 1
|
||||
items:
|
||||
- description: MBUS interconnect/bandwidth limit/PMU registers
|
||||
- description: DRAM controller/PHY registers
|
||||
|
||||
reg-names:
|
||||
minItems: 1
|
||||
items:
|
||||
- const: mbus
|
||||
- const: dram
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
items:
|
||||
- description: MBUS interconnect module clock
|
||||
- description: DRAM controller/PHY module clock
|
||||
- description: Register bus clock, shared by MBUS and DRAM
|
||||
|
||||
clock-names:
|
||||
minItems: 1
|
||||
items:
|
||||
- const: mbus
|
||||
- const: dram
|
||||
- const: bus
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
description:
|
||||
MBUS PMU activity interrupt.
|
||||
|
||||
dma-ranges:
|
||||
description:
|
||||
@ -54,13 +80,55 @@ required:
|
||||
- clocks
|
||||
- dma-ranges
|
||||
|
||||
if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- allwinner,sun8i-h3-mbus
|
||||
- allwinner,sun50i-a64-mbus
|
||||
- allwinner,sun50i-h5-mbus
|
||||
|
||||
then:
|
||||
properties:
|
||||
reg:
|
||||
minItems: 2
|
||||
|
||||
reg-names:
|
||||
minItems: 2
|
||||
|
||||
clocks:
|
||||
minItems: 3
|
||||
|
||||
clock-names:
|
||||
minItems: 3
|
||||
|
||||
required:
|
||||
- reg-names
|
||||
- clock-names
|
||||
|
||||
else:
|
||||
properties:
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
reg-names:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
maxItems: 1
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/sun5i-ccu.h>
|
||||
#include <dt-bindings/clock/sun50i-a64-ccu.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
mbus: dram-controller@1c01000 {
|
||||
dram-controller@1c01000 {
|
||||
compatible = "allwinner,sun5i-a13-mbus";
|
||||
reg = <0x01c01000 0x1000>;
|
||||
clocks = <&ccu CLK_MBUS>;
|
||||
@ -70,4 +138,21 @@ examples:
|
||||
#interconnect-cells = <1>;
|
||||
};
|
||||
|
||||
- |
|
||||
dram-controller@1c62000 {
|
||||
compatible = "allwinner,sun50i-a64-mbus";
|
||||
reg = <0x01c62000 0x1000>,
|
||||
<0x01c63000 0x1000>;
|
||||
reg-names = "mbus", "dram";
|
||||
clocks = <&ccu CLK_MBUS>,
|
||||
<&ccu CLK_DRAM>,
|
||||
<&ccu CLK_BUS_DRAM>;
|
||||
clock-names = "mbus", "dram", "bus";
|
||||
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
dma-ranges = <0x00000000 0x40000000 0xc0000000>;
|
||||
#interconnect-cells = <1>;
|
||||
};
|
||||
|
||||
...
|
||||
|
||||
@ -36,6 +36,9 @@ properties:
|
||||
- toradex,colibri_t20-iris
|
||||
- const: toradex,colibri_t20
|
||||
- const: nvidia,tegra20
|
||||
- items:
|
||||
- const: asus,tf101
|
||||
- const: nvidia,tegra20
|
||||
- items:
|
||||
- const: acer,picasso
|
||||
- const: nvidia,tegra20
|
||||
@ -49,6 +52,18 @@ properties:
|
||||
- nvidia,cardhu-a04
|
||||
- const: nvidia,cardhu
|
||||
- const: nvidia,tegra30
|
||||
- items:
|
||||
- const: asus,tf201
|
||||
- const: nvidia,tegra30
|
||||
- items:
|
||||
- const: asus,tf300t
|
||||
- const: nvidia,tegra30
|
||||
- items:
|
||||
- const: asus,tf300tg
|
||||
- const: nvidia,tegra30
|
||||
- items:
|
||||
- const: asus,tf700t
|
||||
- const: nvidia,tegra30
|
||||
- items:
|
||||
- const: toradex,apalis_t30-eval
|
||||
- const: toradex,apalis_t30
|
||||
@ -74,8 +89,12 @@ properties:
|
||||
- items:
|
||||
- const: ouya,ouya
|
||||
- const: nvidia,tegra30
|
||||
- items:
|
||||
- const: pegatron,chagall
|
||||
- const: nvidia,tegra30
|
||||
- items:
|
||||
- enum:
|
||||
- asus,tf701t
|
||||
- nvidia,dalmore
|
||||
- nvidia,roth
|
||||
- nvidia,tn7
|
||||
@ -108,14 +127,17 @@ properties:
|
||||
- nvidia,p2571
|
||||
- nvidia,p2894-0050-a08
|
||||
- const: nvidia,tegra210
|
||||
- items:
|
||||
- enum:
|
||||
- nvidia,p2771-0000
|
||||
- nvidia,p3509-0000+p3636-0001
|
||||
- description: Jetson TX2 Developer Kit
|
||||
items:
|
||||
- const: nvidia,p2771-0000
|
||||
- const: nvidia,tegra186
|
||||
- items:
|
||||
- enum:
|
||||
- nvidia,p2972-0000
|
||||
- description: Jetson TX2 NX Developer Kit
|
||||
items:
|
||||
- const: nvidia,p3509-0000+p3636-0001
|
||||
- const: nvidia,tegra186
|
||||
- description: Jetson AGX Xavier Developer Kit
|
||||
items:
|
||||
- const: nvidia,p2972-0000
|
||||
- const: nvidia,tegra194
|
||||
- description: Jetson Xavier NX
|
||||
items:
|
||||
@ -134,8 +156,16 @@ properties:
|
||||
- const: nvidia,p3509-0000+p3668-0001
|
||||
- const: nvidia,tegra194
|
||||
- items:
|
||||
- enum:
|
||||
- nvidia,tegra234-vdk
|
||||
- const: nvidia,tegra234-vdk
|
||||
- const: nvidia,tegra234
|
||||
- description: Jetson AGX Orin
|
||||
items:
|
||||
- const: nvidia,p3701-0000
|
||||
- const: nvidia,tegra234
|
||||
- description: Jetson AGX Orin Developer Kit
|
||||
items:
|
||||
- const: nvidia,p3737-0000+p3701-0000
|
||||
- const: nvidia,p3701-0000
|
||||
- const: nvidia,tegra234
|
||||
|
||||
additionalProperties: true
|
||||
|
||||
@ -0,0 +1,198 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra186-pmc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: NVIDIA Tegra Power Management Controller (PMC)
|
||||
|
||||
maintainers:
|
||||
- Thierry Reding <thierry.reding@gmail.com>
|
||||
- Jon Hunter <jonathanh@nvidia.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- nvidia,tegra186-pmc
|
||||
- nvidia,tegra194-pmc
|
||||
- nvidia,tegra234-pmc
|
||||
|
||||
reg:
|
||||
minItems: 4
|
||||
maxItems: 5
|
||||
|
||||
reg-names:
|
||||
minItems: 4
|
||||
items:
|
||||
- const: pmc
|
||||
- const: wake
|
||||
- const: aotag
|
||||
- const: scratch
|
||||
- const: misc
|
||||
|
||||
interrupt-controller: true
|
||||
|
||||
"#interrupt-cells":
|
||||
description: Specifies the number of cells needed to encode an
|
||||
interrupt source. The value must be 2.
|
||||
const: 2
|
||||
|
||||
nvidia,invert-interrupt:
|
||||
description: If present, inverts the PMU interrupt signal.
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
|
||||
if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: nvidia,tegra186-pmc
|
||||
then:
|
||||
properties:
|
||||
reg:
|
||||
maxItems: 4
|
||||
|
||||
reg-names:
|
||||
maxItems: 4
|
||||
else:
|
||||
properties:
|
||||
reg:
|
||||
minItems: 5
|
||||
|
||||
reg-names:
|
||||
minItems: 5
|
||||
|
||||
patternProperties:
|
||||
"^[a-z0-9]+-[a-z0-9]+$":
|
||||
if:
|
||||
type: object
|
||||
then:
|
||||
description: |
|
||||
These are pad configuration nodes. On Tegra SoCs a pad is a set of
|
||||
pins which are configured as a group. The pin grouping is a fixed
|
||||
attribute of the hardware. The PMC can be used to set pad power
|
||||
state and signaling voltage. A pad can be either in active or
|
||||
power down mode. The support for power state and signaling voltage
|
||||
configuration varies depending on the pad in question. 3.3 V and
|
||||
1.8 V signaling voltages are supported on pins where software
|
||||
controllable signaling voltage switching is available.
|
||||
|
||||
Pad configurations are described with pin configuration nodes
|
||||
which are placed under the pmc node and they are referred to by
|
||||
the pinctrl client properties. For more information see
|
||||
|
||||
Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
|
||||
|
||||
The following pads are present on Tegra186:
|
||||
|
||||
csia, csib, dsi, mipi-bias, pex-clk-bias, pex-clk3, pex-clk2,
|
||||
pex-clk1, usb0, usb1, usb2, usb-bias, uart, audio, hsic, dbg,
|
||||
hdmi-dp0, hdmi-dp1, pex-cntrl, sdmmc2-hv, sdmmc4, cam, dsib,
|
||||
dsic, dsid, csic, csid, csie, dsif, spi, ufs, dmic-hv, edp,
|
||||
sdmmc1-hv, sdmmc3-hv, conn, audio-hv, ao-hv
|
||||
|
||||
The following pads are present on Tegra194:
|
||||
|
||||
csia, csib, mipi-bias, pex-clk-bias, pex-clk3, pex-clk2,
|
||||
pex-clk1, eqos, pex-clk-2-bias, pex-clk-2, dap3, dap5, uart,
|
||||
pwr-ctl, soc-gpio53, audio, gp-pwm2, gp-pwm3, soc-gpio12,
|
||||
soc-gpio13, soc-gpio10, uart4, uart5, dbg, hdmi-dp3, hdmi-dp2,
|
||||
hdmi-dp0, hdmi-dp1, pex-cntrl, pex-ctl2, pex-l0-rst,
|
||||
pex-l1-rst, sdmmc4, pex-l5-rst, cam, csic, csid, csie, csif,
|
||||
spi, ufs, csig, csih, edp, sdmmc1-hv, sdmmc3-hv, conn,
|
||||
audio-hv, ao-hv
|
||||
|
||||
properties:
|
||||
pins:
|
||||
$ref: /schemas/types.yaml#/definitions/string
|
||||
description: Must contain the name of the pad(s) to be
|
||||
configured.
|
||||
|
||||
low-power-enable:
|
||||
description: Configure the pad into power down mode.
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
|
||||
low-power-disable:
|
||||
description: Configure the pad into active mode.
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
|
||||
power-source:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: |
|
||||
Must contain either TEGRA_IO_PAD_VOLTAGE_1V8 or
|
||||
TEGRA_IO_PAD_VOLTAGE_3V3 to select between signalling
|
||||
voltages.
|
||||
|
||||
The values are defined in
|
||||
|
||||
include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h
|
||||
|
||||
The power state can be configured on all of the above pads
|
||||
except for ao-hv. Following pads have software configurable
|
||||
signaling voltages: sdmmc2-hv, dmic-hv, sdmmc1-hv, sdmmc3-hv,
|
||||
audio-hv, ao-hv.
|
||||
|
||||
phandle: true
|
||||
|
||||
required:
|
||||
- pins
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
dependencies:
|
||||
interrupt-controller: ['#interrupt-cells']
|
||||
"#interrupt-cells":
|
||||
required:
|
||||
- interrupt-controller
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/tegra186-clock.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
|
||||
#include <dt-bindings/memory/tegra186-mc.h>
|
||||
#include <dt-bindings/reset/tegra186-reset.h>
|
||||
|
||||
pmc@c3600000 {
|
||||
compatible = "nvidia,tegra186-pmc";
|
||||
reg = <0x0c360000 0x10000>,
|
||||
<0x0c370000 0x10000>,
|
||||
<0x0c380000 0x10000>,
|
||||
<0x0c390000 0x10000>;
|
||||
reg-names = "pmc", "wake", "aotag", "scratch";
|
||||
nvidia,invert-interrupt;
|
||||
|
||||
sdmmc1_3v3: sdmmc1-3v3 {
|
||||
pins = "sdmmc1-hv";
|
||||
power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
|
||||
};
|
||||
|
||||
sdmmc1_1v8: sdmmc1-1v8 {
|
||||
pins = "sdmmc1-hv";
|
||||
power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
|
||||
};
|
||||
};
|
||||
|
||||
sdmmc1: mmc@3400000 {
|
||||
compatible = "nvidia,tegra186-sdhci";
|
||||
reg = <0x03400000 0x10000>;
|
||||
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&bpmp TEGRA186_CLK_SDMMC1>,
|
||||
<&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>;
|
||||
clock-names = "sdhci", "tmclk";
|
||||
resets = <&bpmp TEGRA186_RESET_SDMMC1>;
|
||||
reset-names = "sdhci";
|
||||
interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRA &emc>,
|
||||
<&mc TEGRA186_MEMORY_CLIENT_SDMMCWA &emc>;
|
||||
interconnect-names = "dma-mem", "write";
|
||||
iommus = <&smmu TEGRA186_SID_SDMMC1>;
|
||||
pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
|
||||
pinctrl-0 = <&sdmmc1_3v3>;
|
||||
pinctrl-1 = <&sdmmc1_1v8>;
|
||||
};
|
||||
@ -53,6 +53,12 @@ properties:
|
||||
- ti,am642-sk
|
||||
- const: ti,am642
|
||||
|
||||
- description: K3 J721s2 SoC
|
||||
items:
|
||||
- enum:
|
||||
- ti,j721s2-evm
|
||||
- const: ti,j721s2
|
||||
|
||||
additionalProperties: true
|
||||
|
||||
...
|
||||
|
||||
@ -20,6 +20,11 @@ properties:
|
||||
- const: st-ericsson,mop500
|
||||
- const: st-ericsson,u8500
|
||||
|
||||
- description: ST-Ericsson HREF520
|
||||
items:
|
||||
- const: st-ericsson,href520
|
||||
- const: st-ericsson,u8500
|
||||
|
||||
- description: ST-Ericsson HREF (v60+)
|
||||
items:
|
||||
- const: st-ericsson,hrefv60+
|
||||
@ -30,9 +35,34 @@ properties:
|
||||
- const: calaosystems,snowball-a9500
|
||||
- const: st-ericsson,u9500
|
||||
|
||||
- description: Samsung Galaxy Ace 2 (GT-I8160)
|
||||
items:
|
||||
- const: samsung,codina
|
||||
- const: st-ericsson,u8500
|
||||
|
||||
- description: Samsung Galaxy Beam (GT-I8530)
|
||||
items:
|
||||
- const: samsung,gavini
|
||||
- const: st-ericsson,u8500
|
||||
|
||||
- description: Samsung Galaxy S III mini (GT-I8190)
|
||||
items:
|
||||
- const: samsung,golden
|
||||
- const: st-ericsson,u8500
|
||||
|
||||
- description: Samsung Galaxy S Advance (GT-I9070)
|
||||
items:
|
||||
- const: samsung,janice
|
||||
- const: st-ericsson,u8500
|
||||
|
||||
- description: Samsung Galaxy Amp (SGH-I407)
|
||||
items:
|
||||
- const: samsung,kyle
|
||||
- const: st-ericsson,u8500
|
||||
|
||||
- description: Samsung Galaxy XCover 2 (GT-S7710)
|
||||
items:
|
||||
- const: samsung,skomer
|
||||
- const: st-ericsson,u8500
|
||||
|
||||
additionalProperties: true
|
||||
|
||||
@ -7,15 +7,17 @@ the following properties:
|
||||
compatible = "xen,xen-<version>", "xen,xen";
|
||||
where <version> is the version of the Xen ABI of the platform.
|
||||
|
||||
- reg: specifies the base physical address and size of a region in
|
||||
memory where the grant table should be mapped to, using an
|
||||
HYPERVISOR_memory_op hypercall. The memory region is large enough to map
|
||||
the whole grant table (it is larger or equal to gnttab_max_grant_frames()).
|
||||
This property is unnecessary when booting Dom0 using ACPI.
|
||||
- reg: specifies the base physical address and size of the regions in memory
|
||||
where the special resources should be mapped to, using an HYPERVISOR_memory_op
|
||||
hypercall.
|
||||
Region 0 is reserved for mapping grant table, it must be always present.
|
||||
The memory region is large enough to map the whole grant table (it is larger
|
||||
or equal to gnttab_max_grant_frames()).
|
||||
Regions 1...N are extended regions (unused address space) for mapping foreign
|
||||
GFNs and grants, they might be absent if there is nothing to expose.
|
||||
|
||||
- interrupts: the interrupt used by Xen to inject event notifications.
|
||||
A GIC node is also required.
|
||||
This property is unnecessary when booting Dom0 using ACPI.
|
||||
|
||||
To support UEFI on Xen ARM virtual platforms, Xen populates the FDT "uefi" node
|
||||
under /hypervisor with following parameters:
|
||||
|
||||
90
sys/contrib/device-tree/Bindings/ata/brcm,sata-brcm.yaml
Normal file
90
sys/contrib/device-tree/Bindings/ata/brcm,sata-brcm.yaml
Normal file
@ -0,0 +1,90 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/ata/brcm,sata-brcm.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Broadcom SATA3 AHCI Controller
|
||||
|
||||
description:
|
||||
SATA nodes are defined to describe on-chip Serial ATA controllers.
|
||||
Each SATA controller should have its own node.
|
||||
|
||||
maintainers:
|
||||
- Florian Fainelli <f.fainelli@gmail.com>
|
||||
|
||||
allOf:
|
||||
- $ref: sata-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- enum:
|
||||
- brcm,bcm7216-ahci
|
||||
- brcm,bcm7445-ahci
|
||||
- brcm,bcm7425-ahci
|
||||
- brcm,bcm63138-ahci
|
||||
- const: brcm,sata3-ahci
|
||||
- items:
|
||||
- const: brcm,bcm-nsp-ahci
|
||||
|
||||
reg:
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: ahci
|
||||
- const: top-ctrl
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
dma-coherent: true
|
||||
|
||||
if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- brcm,bcm7216-ahci
|
||||
- brcm,bcm63138-ahci
|
||||
then:
|
||||
properties:
|
||||
resets:
|
||||
maxItems: 1
|
||||
reset-names:
|
||||
enum:
|
||||
- rescal
|
||||
- ahci
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- "#address-cells"
|
||||
- "#size-cells"
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
sata@f045a000 {
|
||||
compatible = "brcm,bcm7445-ahci", "brcm,sata3-ahci";
|
||||
reg = <0xf045a000 0xa9c>, <0xf0458040 0x24>;
|
||||
reg-names = "ahci", "top-ctrl";
|
||||
interrupts = <0 30 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
sata0: sata-port@0 {
|
||||
reg = <0>;
|
||||
phys = <&sata_phy 0>;
|
||||
};
|
||||
|
||||
sata1: sata-port@1 {
|
||||
reg = <1>;
|
||||
phys = <&sata_phy 1>;
|
||||
};
|
||||
};
|
||||
66
sys/contrib/device-tree/Bindings/bus/brcm,gisb-arb.yaml
Normal file
66
sys/contrib/device-tree/Bindings/bus/brcm,gisb-arb.yaml
Normal file
@ -0,0 +1,66 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/bus/brcm,gisb-arb.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Broadcom GISB bus Arbiter controller
|
||||
|
||||
maintainers:
|
||||
- Florian Fainelli <f.fainelli@gmail.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- enum:
|
||||
- brcm,bcm7445-gisb-arb # for other 28nm chips
|
||||
- const: brcm,gisb-arb
|
||||
- items:
|
||||
- enum:
|
||||
- brcm,bcm7278-gisb-arb # for V7 28nm chips
|
||||
- brcm,bcm7435-gisb-arb # for newer 40nm chips
|
||||
- brcm,bcm7400-gisb-arb # for older 40nm chips and all 65nm chips
|
||||
- brcm,bcm7038-gisb-arb # for 130nm chips
|
||||
- brcm,gisb-arb # fallback compatible
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
minItems: 2
|
||||
items:
|
||||
- description: timeout interrupt line
|
||||
- description: target abort interrupt line
|
||||
- description: breakpoint interrupt line
|
||||
|
||||
brcm,gisb-arb-master-mask:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: >
|
||||
32-bits wide bitmask used to specify which GISB masters are valid at the
|
||||
system level
|
||||
|
||||
brcm,gisb-arb-master-names:
|
||||
$ref: /schemas/types.yaml#/definitions/string-array
|
||||
description: >
|
||||
String list of the litteral name of the GISB masters. Should match the
|
||||
number of bits set in brcm,gisb-master-mask and the order in which they
|
||||
appear from MSB to LSB.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
gisb-arb@f0400000 {
|
||||
compatible = "brcm,gisb-arb";
|
||||
reg = <0xf0400000 0x800>;
|
||||
interrupts = <0>, <2>;
|
||||
interrupt-parent = <&sun_l2_intc>;
|
||||
brcm,gisb-arb-master-mask = <0x7>;
|
||||
brcm,gisb-arb-master-names = "bsp_0", "scpu_0", "cpu_0";
|
||||
};
|
||||
68
sys/contrib/device-tree/Bindings/bus/fsl,spba-bus.yaml
Normal file
68
sys/contrib/device-tree/Bindings/bus/fsl,spba-bus.yaml
Normal file
@ -0,0 +1,68 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/bus/fsl,spba-bus.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Shared Peripherals Bus Interface
|
||||
|
||||
maintainers:
|
||||
- Shawn Guo <shawnguo@kernel.org>
|
||||
|
||||
description: |
|
||||
A simple bus enabling access to shared peripherals.
|
||||
|
||||
The "spba-bus" follows the "simple-bus" set of properties, as
|
||||
specified in the Devicetree Specification. It is an extension of
|
||||
"simple-bus" because the SDMA controller uses this compatible flag to
|
||||
determine which peripherals are available to it and the range over which
|
||||
the SDMA can access. There are no special clocks for the bus, because
|
||||
the SDMA controller itself has its interrupt and clock assignments.
|
||||
|
||||
select:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: fsl,spba-bus
|
||||
required:
|
||||
- compatible
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
pattern: "^spba-bus(@[0-9a-f]+)?$"
|
||||
|
||||
compatible:
|
||||
items:
|
||||
- const: fsl,spba-bus
|
||||
- const: simple-bus
|
||||
|
||||
'#address-cells':
|
||||
enum: [ 1, 2 ]
|
||||
|
||||
'#size-cells':
|
||||
enum: [ 1, 2 ]
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
ranges: true
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- '#address-cells'
|
||||
- '#size-cells'
|
||||
- reg
|
||||
- ranges
|
||||
|
||||
additionalProperties:
|
||||
type: object
|
||||
|
||||
examples:
|
||||
- |
|
||||
spba-bus@30000000 {
|
||||
compatible = "fsl,spba-bus", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x30000000 0x100000>;
|
||||
ranges;
|
||||
};
|
||||
@ -48,6 +48,11 @@ Optional properties:
|
||||
devices, the presence of this property indicates that
|
||||
the weim bus should operate in Burst Clock Mode.
|
||||
|
||||
- fsl,continuous-burst-clk Make Burst Clock to output continuous clock.
|
||||
Without this option Burst Clock will output clock
|
||||
only when necessary. This takes effect only if
|
||||
"fsl,burst-clk-enable" is set.
|
||||
|
||||
Timing property for child nodes. It is mandatory, not optional.
|
||||
|
||||
- fsl,weim-cs-timing: The timing array, contains timing values for the
|
||||
|
||||
@ -34,6 +34,8 @@ properties:
|
||||
- allwinner,sun8i-v3-ccu
|
||||
- allwinner,sun8i-v3s-ccu
|
||||
- allwinner,sun9i-a80-ccu
|
||||
- allwinner,sun20i-d1-ccu
|
||||
- allwinner,sun20i-d1-r-ccu
|
||||
- allwinner,sun50i-a64-ccu
|
||||
- allwinner,sun50i-a64-r-ccu
|
||||
- allwinner,sun50i-a100-ccu
|
||||
@ -79,6 +81,7 @@ if:
|
||||
enum:
|
||||
- allwinner,sun8i-a83t-r-ccu
|
||||
- allwinner,sun8i-h3-r-ccu
|
||||
- allwinner,sun20i-d1-r-ccu
|
||||
- allwinner,sun50i-a64-r-ccu
|
||||
- allwinner,sun50i-a100-r-ccu
|
||||
- allwinner,sun50i-h6-r-ccu
|
||||
@ -99,6 +102,7 @@ else:
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- allwinner,sun20i-d1-ccu
|
||||
- allwinner,sun50i-a100-ccu
|
||||
- allwinner,sun50i-h6-ccu
|
||||
- allwinner,sun50i-h616-ccu
|
||||
|
||||
@ -55,11 +55,4 @@ examples:
|
||||
<0 72 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
can@53fc8000 {
|
||||
compatible = "fsl,imx53-flexcan", "fsl,imx25-flexcan";
|
||||
reg = <0x53fc8000 0x4000>;
|
||||
interrupts = <82>;
|
||||
clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>, <&clks IMX5_CLK_CAN1_SERIAL_GATE>;
|
||||
clock-names = "ipg", "per";
|
||||
};
|
||||
...
|
||||
|
||||
@ -0,0 +1,60 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/microchip,lan966x-gck.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Microchip LAN966X Generic Clock Controller
|
||||
|
||||
maintainers:
|
||||
- Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com>
|
||||
|
||||
description: |
|
||||
The LAN966X Generic clock controller contains 3 PLLs - cpu_clk,
|
||||
ddr_clk and sys_clk. This clock controller generates and supplies
|
||||
clock to various peripherals within the SoC.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: microchip,lan966x-gck
|
||||
|
||||
reg:
|
||||
minItems: 1
|
||||
items:
|
||||
- description: Generic clock registers
|
||||
- description: Optional gate clock registers
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: CPU clock source
|
||||
- description: DDR clock source
|
||||
- description: System clock source
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: cpu
|
||||
- const: ddr
|
||||
- const: sys
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#clock-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
clks: clock-controller@e00c00a8 {
|
||||
compatible = "microchip,lan966x-gck";
|
||||
#clock-cells = <1>;
|
||||
clocks = <&cpu_clk>, <&ddr_clk>, <&sys_clk>;
|
||||
clock-names = "cpu", "ddr", "sys";
|
||||
reg = <0xe00c00a8 0x38>;
|
||||
};
|
||||
...
|
||||
@ -42,6 +42,36 @@ properties:
|
||||
"#reset-cells":
|
||||
const: 1
|
||||
|
||||
patternProperties:
|
||||
"^(sclk)|(pll-[cem])$":
|
||||
type: object
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- nvidia,tegra20-sclk
|
||||
- nvidia,tegra30-sclk
|
||||
- nvidia,tegra30-pllc
|
||||
- nvidia,tegra30-plle
|
||||
- nvidia,tegra30-pllm
|
||||
|
||||
operating-points-v2: true
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: node's clock
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
description: phandle to the core SoC power domain
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- operating-points-v2
|
||||
- clocks
|
||||
- power-domains
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
@ -59,6 +89,13 @@ examples:
|
||||
reg = <0x60006000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
|
||||
sclk {
|
||||
compatible = "nvidia,tegra20-sclk";
|
||||
operating-points-v2 = <&opp_table>;
|
||||
clocks = <&tegra_car TEGRA20_CLK_SCLK>;
|
||||
power-domains = <&domain>;
|
||||
};
|
||||
};
|
||||
|
||||
usb-controller@c5004000 {
|
||||
|
||||
97
sys/contrib/device-tree/Bindings/clock/qcom,gcc-msm8976.yaml
Normal file
97
sys/contrib/device-tree/Bindings/clock/qcom,gcc-msm8976.yaml
Normal file
@ -0,0 +1,97 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8976.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller Binding for MSM8976
|
||||
|
||||
maintainers:
|
||||
- Stephen Boyd <sboyd@kernel.org>
|
||||
- Taniya Das <tdas@codeaurora.org>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module which supports the clocks, resets and
|
||||
power domains on MSM8976.
|
||||
|
||||
See also:
|
||||
- dt-bindings/clock/qcom,gcc-msm8976.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,gcc-msm8976
|
||||
- qcom,gcc-msm8976-v1.1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: XO source
|
||||
- description: Always-on XO source
|
||||
- description: Pixel clock from DSI PHY0
|
||||
- description: Byte clock from DSI PHY0
|
||||
- description: Pixel clock from DSI PHY1
|
||||
- description: Byte clock from DSI PHY1
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: xo
|
||||
- const: xo_a
|
||||
- const: dsi0pll
|
||||
- const: dsi0pllbyte
|
||||
- const: dsi1pll
|
||||
- const: dsi1pllbyte
|
||||
|
||||
vdd_gfx-supply:
|
||||
description:
|
||||
Phandle to voltage regulator providing power to the GX domain.
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- vdd_gfx-supply
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
clock-controller@1800000 {
|
||||
compatible = "qcom,gcc-msm8976";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
reg = <0x1800000 0x80000>;
|
||||
|
||||
clocks = <&xo_board>,
|
||||
<&xo_board>,
|
||||
<&dsi0_phy 1>,
|
||||
<&dsi0_phy 0>,
|
||||
<&dsi1_phy 1>,
|
||||
<&dsi1_phy 0>;
|
||||
|
||||
clock-names = "xo",
|
||||
"xo_a",
|
||||
"dsi0pll",
|
||||
"dsi0pllbyte",
|
||||
"dsi1pll",
|
||||
"dsi1pllbyte";
|
||||
|
||||
vdd_gfx-supply = <&pm8004_s5>;
|
||||
};
|
||||
...
|
||||
80
sys/contrib/device-tree/Bindings/clock/qcom,gcc-sdx65.yaml
Normal file
80
sys/contrib/device-tree/Bindings/clock/qcom,gcc-sdx65.yaml
Normal file
@ -0,0 +1,80 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,gcc-sdx65.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller Binding for SDX65
|
||||
|
||||
maintainers:
|
||||
- Vamsi krishna Lanka <quic_vamslank@quicinc.com>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module which supports the clocks, resets and
|
||||
power domains on SDX65
|
||||
|
||||
See also:
|
||||
- dt-bindings/clock/qcom,gcc-sdx65.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,gcc-sdx65
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: Board active XO source
|
||||
- description: Sleep clock source
|
||||
- description: PCIE Pipe clock source
|
||||
- description: USB3 phy wrapper pipe clock source
|
||||
- description: PLL test clock source (Optional clock)
|
||||
minItems: 5
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: bi_tcxo
|
||||
- const: bi_tcxo_ao
|
||||
- const: sleep_clk
|
||||
- const: pcie_pipe_clk
|
||||
- const: usb3_phy_wrapper_gcc_usb30_pipe_clk
|
||||
- const: core_bi_pll_test_se # Optional clock
|
||||
minItems: 5
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
clock-controller@100000 {
|
||||
compatible = "qcom,gcc-sdx65";
|
||||
reg = <0x100000 0x1f7400>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>,
|
||||
<&pcie_pipe_clk>, <&usb3_phy_wrapper_gcc_usb30_pipe_clk>, <&pll_test_clk>;
|
||||
clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk",
|
||||
"pcie_pipe_clk", "usb3_phy_wrapper_gcc_usb30_pipe_clk", "core_bi_pll_test_se";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
...
|
||||
85
sys/contrib/device-tree/Bindings/clock/qcom,gcc-sm8450.yaml
Normal file
85
sys/contrib/device-tree/Bindings/clock/qcom,gcc-sm8450.yaml
Normal file
@ -0,0 +1,85 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,gcc-sm8450.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller Binding for SM8450
|
||||
|
||||
maintainers:
|
||||
- Vinod Koul <vkoul@kernel.org>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module which supports the clocks, resets and
|
||||
power domains on SM8450
|
||||
|
||||
See also:
|
||||
- dt-bindings/clock/qcom,gcc-sm8450.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,gcc-sm8450
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: Sleep clock source
|
||||
- description: PCIE 0 Pipe clock source (Optional clock)
|
||||
- description: PCIE 1 Pipe clock source (Optional clock)
|
||||
- description: PCIE 1 Phy Auxillary clock source (Optional clock)
|
||||
- description: UFS Phy Rx symbol 0 clock source (Optional clock)
|
||||
- description: UFS Phy Rx symbol 1 clock source (Optional clock)
|
||||
- description: UFS Phy Tx symbol 0 clock source (Optional clock)
|
||||
- description: USB3 Phy wrapper pipe clock source (Optional clock)
|
||||
minItems: 2
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: bi_tcxo
|
||||
- const: sleep_clk
|
||||
- const: pcie_0_pipe_clk # Optional clock
|
||||
- const: pcie_1_pipe_clk # Optional clock
|
||||
- const: pcie_1_phy_aux_clk # Optional clock
|
||||
- const: ufs_phy_rx_symbol_0_clk # Optional clock
|
||||
- const: ufs_phy_rx_symbol_1_clk # Optional clock
|
||||
- const: ufs_phy_tx_symbol_0_clk # Optional clock
|
||||
- const: usb3_phy_wrapper_gcc_usb30_pipe_clk # Optional clock
|
||||
minItems: 2
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
clock-controller@100000 {
|
||||
compatible = "qcom,gcc-sm8450";
|
||||
reg = <0x00100000 0x001f4200>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>;
|
||||
clock-names = "bi_tcxo", "sleep_clk";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
...
|
||||
@ -22,10 +22,12 @@ properties:
|
||||
- qcom,sc8180x-rpmh-clk
|
||||
- qcom,sdm845-rpmh-clk
|
||||
- qcom,sdx55-rpmh-clk
|
||||
- qcom,sdx65-rpmh-clk
|
||||
- qcom,sm6350-rpmh-clk
|
||||
- qcom,sm8150-rpmh-clk
|
||||
- qcom,sm8250-rpmh-clk
|
||||
- qcom,sm8350-rpmh-clk
|
||||
- qcom,sm8450-rpmh-clk
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
@ -44,6 +44,7 @@ Required properties:
|
||||
* "fsl,ls1046a-clockgen"
|
||||
* "fsl,ls1088a-clockgen"
|
||||
* "fsl,ls2080a-clockgen"
|
||||
* "fsl,lx2160a-clockgen"
|
||||
Chassis-version clock strings include:
|
||||
* "fsl,qoriq-clockgen-1.0": for chassis 1.0 clocks
|
||||
* "fsl,qoriq-clockgen-2.0": for chassis 2.0 clocks
|
||||
|
||||
@ -48,6 +48,7 @@ properties:
|
||||
- renesas,r8a77990-cpg-mssr # R-Car E3
|
||||
- renesas,r8a77995-cpg-mssr # R-Car D3
|
||||
- renesas,r8a779a0-cpg-mssr # R-Car V3U
|
||||
- renesas,r8a779f0-cpg-mssr # R-Car S4-8
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
@ -0,0 +1,382 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/samsung,exynos5260-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Samsung Exynos5260 SoC clock controller
|
||||
|
||||
maintainers:
|
||||
- Chanwoo Choi <cw00.choi@samsung.com>
|
||||
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
|
||||
- Sylwester Nawrocki <s.nawrocki@samsung.com>
|
||||
- Tomasz Figa <tomasz.figa@gmail.com>
|
||||
|
||||
description: |
|
||||
Expected external clocks, defined in DTS as fixed-rate clocks with a matching
|
||||
name::
|
||||
- "fin_pll" - PLL input clock from XXTI
|
||||
- "xrtcxti" - input clock from XRTCXTI
|
||||
- "ioclk_pcm_extclk" - pcm external operation clock
|
||||
- "ioclk_spdif_extclk" - spdif external operation clock
|
||||
- "ioclk_i2s_cdclk" - i2s0 codec clock
|
||||
|
||||
Phy clocks::
|
||||
There are several clocks which are generated by specific PHYs. These clocks
|
||||
are fed into the clock controller and then routed to the hardware blocks.
|
||||
These clocks are defined as fixed clocks in the driver with following names::
|
||||
- "phyclk_dptx_phy_ch3_txd_clk" - dp phy clock for channel 3
|
||||
- "phyclk_dptx_phy_ch2_txd_clk" - dp phy clock for channel 2
|
||||
- "phyclk_dptx_phy_ch1_txd_clk" - dp phy clock for channel 1
|
||||
- "phyclk_dptx_phy_ch0_txd_clk" - dp phy clock for channel 0
|
||||
- "phyclk_hdmi_phy_tmds_clko" - hdmi phy tmds clock
|
||||
- "phyclk_hdmi_phy_pixel_clko" - hdmi phy pixel clock
|
||||
- "phyclk_hdmi_link_o_tmds_clkhi" - hdmi phy for hdmi link
|
||||
- "phyclk_dptx_phy_o_ref_clk_24m" - dp phy reference clock
|
||||
- "phyclk_dptx_phy_clk_div2"
|
||||
- "phyclk_mipi_dphy_4l_m_rxclkesc0"
|
||||
- "phyclk_usbhost20_phy_phyclock" - usb 2.0 phy clock
|
||||
- "phyclk_usbhost20_phy_freeclk"
|
||||
- "phyclk_usbhost20_phy_clk48mohci"
|
||||
- "phyclk_usbdrd30_udrd30_pipe_pclk"
|
||||
- "phyclk_usbdrd30_udrd30_phyclock" - usb 3.0 phy clock
|
||||
|
||||
All available clocks are defined as preprocessor macros in
|
||||
include/dt-bindings/clock/exynos5260-clk.h header.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- samsung,exynos5260-clock-top
|
||||
- samsung,exynos5260-clock-peri
|
||||
- samsung,exynos5260-clock-egl
|
||||
- samsung,exynos5260-clock-kfc
|
||||
- samsung,exynos5260-clock-g2d
|
||||
- samsung,exynos5260-clock-mif
|
||||
- samsung,exynos5260-clock-mfc
|
||||
- samsung,exynos5260-clock-g3d
|
||||
- samsung,exynos5260-clock-fsys
|
||||
- samsung,exynos5260-clock-aud
|
||||
- samsung,exynos5260-clock-isp
|
||||
- samsung,exynos5260-clock-gscl
|
||||
- samsung,exynos5260-clock-disp
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
maxItems: 19
|
||||
|
||||
clock-names:
|
||||
minItems: 1
|
||||
maxItems: 19
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- "#clock-cells"
|
||||
- reg
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynos5260-clock-top
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 4
|
||||
maxItems: 4
|
||||
clock-names:
|
||||
items:
|
||||
- const: fin_pll
|
||||
- const: dout_mem_pll
|
||||
- const: dout_bus_pll
|
||||
- const: dout_media_pll
|
||||
required:
|
||||
- clock-names
|
||||
- clocks
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynos5260-clock-peri
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 13
|
||||
maxItems: 13
|
||||
clock-names:
|
||||
items:
|
||||
- const: fin_pll
|
||||
- const: ioclk_pcm_extclk
|
||||
- const: ioclk_i2s_cdclk
|
||||
- const: ioclk_spdif_extclk
|
||||
- const: phyclk_hdmi_phy_ref_cko
|
||||
- const: dout_aclk_peri_66
|
||||
- const: dout_sclk_peri_uart0
|
||||
- const: dout_sclk_peri_uart1
|
||||
- const: dout_sclk_peri_uart2
|
||||
- const: dout_sclk_peri_spi0_b
|
||||
- const: dout_sclk_peri_spi1_b
|
||||
- const: dout_sclk_peri_spi2_b
|
||||
- const: dout_aclk_peri_aud
|
||||
required:
|
||||
- clock-names
|
||||
- clocks
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynos5260-clock-egl
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
clock-names:
|
||||
items:
|
||||
- const: fin_pll
|
||||
- const: dout_bus_pll
|
||||
required:
|
||||
- clock-names
|
||||
- clocks
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynos5260-clock-kfc
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
clock-names:
|
||||
items:
|
||||
- const: fin_pll
|
||||
- const: dout_media_pll
|
||||
required:
|
||||
- clock-names
|
||||
- clocks
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynos5260-clock-g2d
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
clock-names:
|
||||
items:
|
||||
- const: fin_pll
|
||||
- const: dout_aclk_g2d_333
|
||||
required:
|
||||
- clock-names
|
||||
- clocks
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynos5260-clock-mif
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 1
|
||||
maxItems: 1
|
||||
clock-names:
|
||||
items:
|
||||
- const: fin_pll
|
||||
required:
|
||||
- clock-names
|
||||
- clocks
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynos5260-clock-mfc
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
clock-names:
|
||||
items:
|
||||
- const: fin_pll
|
||||
- const: dout_aclk_mfc_333
|
||||
required:
|
||||
- clock-names
|
||||
- clocks
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynos5260-clock-g3d
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 1
|
||||
maxItems: 1
|
||||
clock-names:
|
||||
items:
|
||||
- const: fin_pll
|
||||
required:
|
||||
- clock-names
|
||||
- clocks
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynos5260-clock-fsys
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 7
|
||||
maxItems: 7
|
||||
clock-names:
|
||||
items:
|
||||
- const: fin_pll
|
||||
- const: phyclk_usbhost20_phy_phyclock
|
||||
- const: phyclk_usbhost20_phy_freeclk
|
||||
- const: phyclk_usbhost20_phy_clk48mohci
|
||||
- const: phyclk_usbdrd30_udrd30_pipe_pclk
|
||||
- const: phyclk_usbdrd30_udrd30_phyclock
|
||||
- const: dout_aclk_fsys_200
|
||||
required:
|
||||
- clock-names
|
||||
- clocks
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynos5260-clock-aud
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 4
|
||||
maxItems: 4
|
||||
clock-names:
|
||||
items:
|
||||
- const: fin_pll
|
||||
- const: fout_aud_pll
|
||||
- const: ioclk_i2s_cdclk
|
||||
- const: ioclk_pcm_extclk
|
||||
required:
|
||||
- clock-names
|
||||
- clocks
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynos5260-clock-isp
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 4
|
||||
maxItems: 4
|
||||
clock-names:
|
||||
items:
|
||||
- const: fin_pll
|
||||
- const: dout_aclk_isp1_266
|
||||
- const: dout_aclk_isp1_400
|
||||
- const: mout_aclk_isp1_266
|
||||
|
||||
required:
|
||||
- clock-names
|
||||
- clocks
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynos5260-clock-gscl
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 3
|
||||
maxItems: 3
|
||||
clock-names:
|
||||
items:
|
||||
- const: fin_pll
|
||||
- const: dout_aclk_gscl_400
|
||||
- const: dout_aclk_gscl_333
|
||||
required:
|
||||
- clock-names
|
||||
- clocks
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynos5260-clock-disp
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 19
|
||||
maxItems: 19
|
||||
clock-names:
|
||||
items:
|
||||
- const: fin_pll
|
||||
- const: phyclk_dptx_phy_ch3_txd_clk
|
||||
- const: phyclk_dptx_phy_ch2_txd_clk
|
||||
- const: phyclk_dptx_phy_ch1_txd_clk
|
||||
- const: phyclk_dptx_phy_ch0_txd_clk
|
||||
- const: phyclk_hdmi_phy_tmds_clko
|
||||
- const: phyclk_hdmi_phy_ref_clko
|
||||
- const: phyclk_hdmi_phy_pixel_clko
|
||||
- const: phyclk_hdmi_link_o_tmds_clkhi
|
||||
- const: phyclk_mipi_dphy_4l_m_txbyte_clkhs
|
||||
- const: phyclk_dptx_phy_o_ref_clk_24m
|
||||
- const: phyclk_dptx_phy_clk_div2
|
||||
- const: phyclk_mipi_dphy_4l_m_rxclkesc0
|
||||
- const: phyclk_hdmi_phy_ref_cko
|
||||
- const: ioclk_spdif_extclk
|
||||
- const: dout_aclk_peri_aud
|
||||
- const: dout_aclk_disp_222
|
||||
- const: dout_sclk_disp_pixel
|
||||
- const: dout_aclk_disp_333
|
||||
required:
|
||||
- clock-names
|
||||
- clocks
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/exynos5260-clk.h>
|
||||
|
||||
fin_pll: clock {
|
||||
compatible = "fixed-clock";
|
||||
clock-output-names = "fin_pll";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
|
||||
clock-controller@10010000 {
|
||||
compatible = "samsung,exynos5260-clock-top";
|
||||
reg = <0x10010000 0x10000>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&fin_pll>,
|
||||
<&clock_mif MIF_DOUT_MEM_PLL>,
|
||||
<&clock_mif MIF_DOUT_BUS_PLL>,
|
||||
<&clock_mif MIF_DOUT_MEDIA_PLL>;
|
||||
clock-names = "fin_pll",
|
||||
"dout_mem_pll",
|
||||
"dout_bus_pll",
|
||||
"dout_media_pll";
|
||||
};
|
||||
@ -0,0 +1,66 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/samsung,exynos5410-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Samsung Exynos5410 SoC clock controller
|
||||
|
||||
maintainers:
|
||||
- Chanwoo Choi <cw00.choi@samsung.com>
|
||||
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
|
||||
- Sylwester Nawrocki <s.nawrocki@samsung.com>
|
||||
- Tomasz Figa <tomasz.figa@gmail.com>
|
||||
|
||||
description: |
|
||||
Expected external clocks, defined in DTS as fixed-rate clocks with a matching
|
||||
name::
|
||||
- "fin_pll" - PLL input clock from XXTI
|
||||
|
||||
All available clocks are defined as preprocessor macros in
|
||||
include/dt-bindings/clock/exynos5410.h header.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- enum:
|
||||
- samsung,exynos5410-clock
|
||||
|
||||
clocks:
|
||||
description:
|
||||
Should contain an entry specifying the root clock from external
|
||||
oscillator supplied through XXTI or XusbXTI pin. This clock should be
|
||||
defined using standard clock bindings with "fin_pll" clock-output-name.
|
||||
That clock is being passed internally to the 9 PLLs.
|
||||
maxItems: 1
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- "#clock-cells"
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/exynos5410.h>
|
||||
|
||||
fin_pll: osc-clock {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <24000000>;
|
||||
clock-output-names = "fin_pll";
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
clock-controller@10010000 {
|
||||
compatible = "samsung,exynos5410-clock";
|
||||
reg = <0x10010000 0x30000>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&fin_pll>;
|
||||
};
|
||||
@ -0,0 +1,524 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/samsung,exynos5433-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Samsung Exynos5433 SoC clock controller
|
||||
|
||||
maintainers:
|
||||
- Chanwoo Choi <cw00.choi@samsung.com>
|
||||
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
|
||||
- Sylwester Nawrocki <s.nawrocki@samsung.com>
|
||||
- Tomasz Figa <tomasz.figa@gmail.com>
|
||||
|
||||
description: |
|
||||
Expected external clocks, defined in DTS as fixed-rate clocks with a matching
|
||||
name::
|
||||
- "oscclk" - PLL input clock from XXTI
|
||||
|
||||
All available clocks are defined as preprocessor macros in
|
||||
include/dt-bindings/clock/exynos5433.h header.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
# CMU_TOP which generates clocks for
|
||||
# IMEM/FSYS/G3D/GSCL/HEVC/MSCL/G2D/MFC/PERIC/PERIS domains and bus
|
||||
# clocks
|
||||
- samsung,exynos5433-cmu-top
|
||||
# CMU_CPIF which generates clocks for LLI (Low Latency Interface) IP
|
||||
- samsung,exynos5433-cmu-cpif
|
||||
# CMU_MIF which generates clocks for DRAM Memory Controller domain
|
||||
- samsung,exynos5433-cmu-mif
|
||||
# CMU_PERIC which generates clocks for
|
||||
# UART/I2C/SPI/I2S/PCM/SPDIF/PWM/SLIMBUS IPs
|
||||
- samsung,exynos5433-cmu-peric
|
||||
# CMU_PERIS which generates clocks for PMU/TMU/MCT/WDT/RTC/SECKEY/TZPC IPs
|
||||
- samsung,exynos5433-cmu-peris
|
||||
# CMU_FSYS which generates clocks for USB/UFS/SDMMC/TSI/PDMA IPs
|
||||
- samsung,exynos5433-cmu-fsys
|
||||
- samsung,exynos5433-cmu-g2d
|
||||
# CMU_DISP which generates clocks for Display (DECON/HDMI/DSIM/MIXER) IPs
|
||||
- samsung,exynos5433-cmu-disp
|
||||
- samsung,exynos5433-cmu-aud
|
||||
- samsung,exynos5433-cmu-bus0
|
||||
- samsung,exynos5433-cmu-bus1
|
||||
- samsung,exynos5433-cmu-bus2
|
||||
- samsung,exynos5433-cmu-g3d
|
||||
- samsung,exynos5433-cmu-gscl
|
||||
- samsung,exynos5433-cmu-apollo
|
||||
# CMU_ATLAS which generates clocks for Cortex-A57 Quad-core processor,
|
||||
# CoreSight and L2 cache controller
|
||||
- samsung,exynos5433-cmu-atlas
|
||||
# CMU_MSCL which generates clocks for M2M (Memory to Memory) scaler and
|
||||
# JPEG IPs
|
||||
- samsung,exynos5433-cmu-mscl
|
||||
- samsung,exynos5433-cmu-mfc
|
||||
- samsung,exynos5433-cmu-hevc
|
||||
# CMU_ISP which generates clocks for FIMC-ISP/DRC/SCLC/DIS/3DNR IPs
|
||||
- samsung,exynos5433-cmu-isp
|
||||
# CMU_CAM0 which generates clocks for
|
||||
# MIPI_CSIS{0|1}/FIMC_LITE_{A|B|D}/FIMC_3AA{0|1} IPs
|
||||
- samsung,exynos5433-cmu-cam0
|
||||
# CMU_CAM1 which generates clocks for
|
||||
# Cortex-A5/MIPI_CSIS2/FIMC-LITE_C/FIMC-FD IPs
|
||||
- samsung,exynos5433-cmu-cam1
|
||||
# CMU_IMEM which generates clocks for SSS (Security SubSystem) and
|
||||
# SlimSSS IPs
|
||||
- samsung,exynos5433-cmu-imem
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
maxItems: 10
|
||||
|
||||
clock-names:
|
||||
minItems: 1
|
||||
maxItems: 10
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- "#clock-cells"
|
||||
- reg
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynos5433-cmu-top
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 4
|
||||
maxItems: 4
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
- const: sclk_mphy_pll
|
||||
- const: sclk_mfc_pll
|
||||
- const: sclk_bus_pll
|
||||
required:
|
||||
- clock-names
|
||||
- clocks
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynos5433-cmu-cpif
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 1
|
||||
maxItems: 1
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
required:
|
||||
- clock-names
|
||||
- clocks
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynos5433-cmu-mif
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
- const: sclk_mphy_pll
|
||||
required:
|
||||
- clock-names
|
||||
- clocks
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynos5433-cmu-fsys
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 10
|
||||
maxItems: 10
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
- const: sclk_ufs_mphy
|
||||
- const: aclk_fsys_200
|
||||
- const: sclk_pcie_100_fsys
|
||||
- const: sclk_ufsunipro_fsys
|
||||
- const: sclk_mmc2_fsys
|
||||
- const: sclk_mmc1_fsys
|
||||
- const: sclk_mmc0_fsys
|
||||
- const: sclk_usbhost30_fsys
|
||||
- const: sclk_usbdrd30_fsys
|
||||
required:
|
||||
- clock-names
|
||||
- clocks
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynos5433-cmu-g2d
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 3
|
||||
maxItems: 3
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
- const: aclk_g2d_266
|
||||
- const: aclk_g2d_400
|
||||
required:
|
||||
- clock-names
|
||||
- clocks
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynos5433-cmu-disp
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 9
|
||||
maxItems: 9
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
- const: sclk_dsim1_disp
|
||||
- const: sclk_dsim0_disp
|
||||
- const: sclk_dsd_disp
|
||||
- const: sclk_decon_tv_eclk_disp
|
||||
- const: sclk_decon_vclk_disp
|
||||
- const: sclk_decon_eclk_disp
|
||||
- const: sclk_decon_tv_vclk_disp
|
||||
- const: aclk_disp_333
|
||||
required:
|
||||
- clock-names
|
||||
- clocks
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynos5433-cmu-aud
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
- const: fout_aud_pll
|
||||
required:
|
||||
- clock-names
|
||||
- clocks
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynos5433-cmu-bus0
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 1
|
||||
maxItems: 1
|
||||
clock-names:
|
||||
items:
|
||||
- const: aclk_bus0_400
|
||||
required:
|
||||
- clock-names
|
||||
- clocks
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynos5433-cmu-bus1
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 1
|
||||
maxItems: 1
|
||||
clock-names:
|
||||
items:
|
||||
- const: aclk_bus1_400
|
||||
required:
|
||||
- clock-names
|
||||
- clocks
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynos5433-cmu-bus2
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
- const: aclk_bus2_400
|
||||
required:
|
||||
- clock-names
|
||||
- clocks
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynos5433-cmu-g3d
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
- const: aclk_g3d_400
|
||||
required:
|
||||
- clock-names
|
||||
- clocks
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynos5433-cmu-gscl
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 3
|
||||
maxItems: 3
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
- const: aclk_gscl_111
|
||||
- const: aclk_gscl_333
|
||||
required:
|
||||
- clock-names
|
||||
- clocks
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynos5433-cmu-apollo
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
- const: sclk_bus_pll_apollo
|
||||
required:
|
||||
- clock-names
|
||||
- clocks
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynos5433-cmu-atlas
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
- const: sclk_bus_pll_atlas
|
||||
required:
|
||||
- clock-names
|
||||
- clocks
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynos5433-cmu-mscl
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 3
|
||||
maxItems: 3
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
- const: sclk_jpeg_mscl
|
||||
- const: aclk_mscl_400
|
||||
required:
|
||||
- clock-names
|
||||
- clocks
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynos5433-cmu-mfc
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
- const: aclk_mfc_400
|
||||
required:
|
||||
- clock-names
|
||||
- clocks
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynos5433-cmu-hevc
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
- const: aclk_hevc_400
|
||||
required:
|
||||
- clock-names
|
||||
- clocks
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynos5433-cmu-isp
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 3
|
||||
maxItems: 3
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
- const: aclk_isp_dis_400
|
||||
- const: aclk_isp_400
|
||||
required:
|
||||
- clock-names
|
||||
- clocks
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynos5433-cmu-cam0
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 4
|
||||
maxItems: 4
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
- const: aclk_cam0_333
|
||||
- const: aclk_cam0_400
|
||||
- const: aclk_cam0_552
|
||||
required:
|
||||
- clock-names
|
||||
- clocks
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynos5433-cmu-cam1
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 7
|
||||
maxItems: 7
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
- const: sclk_isp_uart_cam1
|
||||
- const: sclk_isp_spi1_cam1
|
||||
- const: sclk_isp_spi0_cam1
|
||||
- const: aclk_cam1_333
|
||||
- const: aclk_cam1_400
|
||||
- const: aclk_cam1_552
|
||||
required:
|
||||
- clock-names
|
||||
- clocks
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynos5433-cmu-imem
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 4
|
||||
maxItems: 4
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
- const: aclk_imem_sssx_266
|
||||
- const: aclk_imem_266
|
||||
- const: aclk_imem_200
|
||||
required:
|
||||
- clock-names
|
||||
- clocks
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/exynos5433.h>
|
||||
xxti: clock {
|
||||
compatible = "fixed-clock";
|
||||
clock-output-names = "oscclk";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
|
||||
clock-controller@10030000 {
|
||||
compatible = "samsung,exynos5433-cmu-top";
|
||||
reg = <0x10030000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
|
||||
clock-names = "oscclk",
|
||||
"sclk_mphy_pll",
|
||||
"sclk_mfc_pll",
|
||||
"sclk_bus_pll";
|
||||
clocks = <&xxti>,
|
||||
<&cmu_cpif CLK_SCLK_MPHY_PLL>,
|
||||
<&cmu_mif CLK_SCLK_MFC_PLL>,
|
||||
<&cmu_mif CLK_SCLK_BUS_PLL>;
|
||||
};
|
||||
@ -0,0 +1,272 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/samsung,exynos7-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Samsung Exynos7 SoC clock controller
|
||||
|
||||
maintainers:
|
||||
- Chanwoo Choi <cw00.choi@samsung.com>
|
||||
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
|
||||
- Sylwester Nawrocki <s.nawrocki@samsung.com>
|
||||
- Tomasz Figa <tomasz.figa@gmail.com>
|
||||
|
||||
description: |
|
||||
Expected external clocks, defined in DTS as fixed-rate clocks with a matching
|
||||
name::
|
||||
- "fin_pll" - PLL input clock from XXTI
|
||||
|
||||
All available clocks are defined as preprocessor macros in
|
||||
include/dt-bindings/clock/exynos7-clk.h header.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- samsung,exynos7-clock-topc
|
||||
- samsung,exynos7-clock-top0
|
||||
- samsung,exynos7-clock-top1
|
||||
- samsung,exynos7-clock-ccore
|
||||
- samsung,exynos7-clock-peric0
|
||||
- samsung,exynos7-clock-peric1
|
||||
- samsung,exynos7-clock-peris
|
||||
- samsung,exynos7-clock-fsys0
|
||||
- samsung,exynos7-clock-fsys1
|
||||
- samsung,exynos7-clock-mscl
|
||||
- samsung,exynos7-clock-aud
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
maxItems: 13
|
||||
|
||||
clock-names:
|
||||
minItems: 1
|
||||
maxItems: 13
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- "#clock-cells"
|
||||
- reg
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynos7-clock-top0
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 6
|
||||
maxItems: 6
|
||||
clock-names:
|
||||
items:
|
||||
- const: fin_pll
|
||||
- const: dout_sclk_bus0_pll
|
||||
- const: dout_sclk_bus1_pll
|
||||
- const: dout_sclk_cc_pll
|
||||
- const: dout_sclk_mfc_pll
|
||||
- const: dout_sclk_aud_pll
|
||||
required:
|
||||
- clock-names
|
||||
- clocks
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynos7-clock-top1
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 5
|
||||
maxItems: 5
|
||||
clock-names:
|
||||
items:
|
||||
- const: fin_pll
|
||||
- const: dout_sclk_bus0_pll
|
||||
- const: dout_sclk_bus1_pll
|
||||
- const: dout_sclk_cc_pll
|
||||
- const: dout_sclk_mfc_pll
|
||||
required:
|
||||
- clock-names
|
||||
- clocks
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynos7-clock-ccore
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
clock-names:
|
||||
items:
|
||||
- const: fin_pll
|
||||
- const: dout_aclk_ccore_133
|
||||
required:
|
||||
- clock-names
|
||||
- clocks
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynos7-clock-peric0
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 3
|
||||
maxItems: 3
|
||||
clock-names:
|
||||
items:
|
||||
- const: fin_pll
|
||||
- const: dout_aclk_peric0_66
|
||||
- const: sclk_uart0
|
||||
required:
|
||||
- clock-names
|
||||
- clocks
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynos7-clock-peric1
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 13
|
||||
maxItems: 13
|
||||
clock-names:
|
||||
items:
|
||||
- const: fin_pll
|
||||
- const: dout_aclk_peric1_66
|
||||
- const: sclk_uart1
|
||||
- const: sclk_uart2
|
||||
- const: sclk_uart3
|
||||
- const: sclk_spi0
|
||||
- const: sclk_spi1
|
||||
- const: sclk_spi2
|
||||
- const: sclk_spi3
|
||||
- const: sclk_spi4
|
||||
- const: sclk_i2s1
|
||||
- const: sclk_pcm1
|
||||
- const: sclk_spdif
|
||||
required:
|
||||
- clock-names
|
||||
- clocks
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynos7-clock-peris
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
clock-names:
|
||||
items:
|
||||
- const: fin_pll
|
||||
- const: dout_aclk_peris_66
|
||||
required:
|
||||
- clock-names
|
||||
- clocks
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynos7-clock-fsys0
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 3
|
||||
maxItems: 3
|
||||
clock-names:
|
||||
items:
|
||||
- const: fin_pll
|
||||
- const: dout_aclk_fsys0_200
|
||||
- const: dout_sclk_mmc2
|
||||
required:
|
||||
- clock-names
|
||||
- clocks
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynos7-clock-fsys1
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 7
|
||||
maxItems: 7
|
||||
clock-names:
|
||||
items:
|
||||
- const: fin_pll
|
||||
- const: dout_aclk_fsys1_200
|
||||
- const: dout_sclk_mmc0
|
||||
- const: dout_sclk_mmc1
|
||||
- const: dout_sclk_ufsunipro20
|
||||
- const: dout_sclk_phy_fsys1
|
||||
- const: dout_sclk_phy_fsys1_26m
|
||||
required:
|
||||
- clock-names
|
||||
- clocks
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynos7-clock-aud
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
clock-names:
|
||||
items:
|
||||
- const: fin_pll
|
||||
- const: fout_aud_pll
|
||||
required:
|
||||
- clock-names
|
||||
- clocks
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/exynos7-clk.h>
|
||||
|
||||
fin_pll: clock {
|
||||
compatible = "fixed-clock";
|
||||
clock-output-names = "fin_pll";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
|
||||
clock-controller@105e0000 {
|
||||
compatible = "samsung,exynos7-clock-top1";
|
||||
reg = <0x105e0000 0xb000>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&fin_pll>,
|
||||
<&clock_topc DOUT_SCLK_BUS0_PLL>,
|
||||
<&clock_topc DOUT_SCLK_BUS1_PLL>,
|
||||
<&clock_topc DOUT_SCLK_CC_PLL>,
|
||||
<&clock_topc DOUT_SCLK_MFC_PLL>;
|
||||
clock-names = "fin_pll",
|
||||
"dout_sclk_bus0_pll",
|
||||
"dout_sclk_bus1_pll",
|
||||
"dout_sclk_cc_pll",
|
||||
"dout_sclk_mfc_pll";
|
||||
};
|
||||
@ -0,0 +1,166 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/samsung,exynos7885-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Samsung Exynos7885 SoC clock controller
|
||||
|
||||
maintainers:
|
||||
- Dávid Virág <virag.david003@gmail.com>
|
||||
- Chanwoo Choi <cw00.choi@samsung.com>
|
||||
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
|
||||
- Sylwester Nawrocki <s.nawrocki@samsung.com>
|
||||
- Tomasz Figa <tomasz.figa@gmail.com>
|
||||
|
||||
description: |
|
||||
Exynos7885 clock controller is comprised of several CMU units, generating
|
||||
clocks for different domains. Those CMU units are modeled as separate device
|
||||
tree nodes, and might depend on each other. The root clock in that root tree
|
||||
is an external clock: OSCCLK (26 MHz). This external clock must be defined
|
||||
as a fixed-rate clock in dts.
|
||||
|
||||
CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
|
||||
dividers; all other leaf clocks (other CMUs) are usually derived from CMU_TOP.
|
||||
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume. All clocks available for usage
|
||||
in clock consumer nodes are defined as preprocessor macros in
|
||||
'dt-bindings/clock/exynos7885.h' header.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- samsung,exynos7885-cmu-top
|
||||
- samsung,exynos7885-cmu-core
|
||||
- samsung,exynos7885-cmu-peri
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
maxItems: 10
|
||||
|
||||
clock-names:
|
||||
minItems: 1
|
||||
maxItems: 10
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynos7885-cmu-top
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (26 MHz)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynos7885-cmu-core
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (26 MHz)
|
||||
- description: CMU_CORE bus clock (from CMU_TOP)
|
||||
- description: CCI clock (from CMU_TOP)
|
||||
- description: G3D clock (from CMU_TOP)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
- const: dout_core_bus
|
||||
- const: dout_core_cci
|
||||
- const: dout_core_g3d
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynos7885-cmu-peri
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (26 MHz)
|
||||
- description: CMU_PERI bus clock (from CMU_TOP)
|
||||
- description: SPI0 clock (from CMU_TOP)
|
||||
- description: SPI1 clock (from CMU_TOP)
|
||||
- description: UART0 clock (from CMU_TOP)
|
||||
- description: UART1 clock (from CMU_TOP)
|
||||
- description: UART2 clock (from CMU_TOP)
|
||||
- description: USI0 clock (from CMU_TOP)
|
||||
- description: USI1 clock (from CMU_TOP)
|
||||
- description: USI2 clock (from CMU_TOP)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
- const: dout_peri_bus
|
||||
- const: dout_peri_spi0
|
||||
- const: dout_peri_spi1
|
||||
- const: dout_peri_uart0
|
||||
- const: dout_peri_uart1
|
||||
- const: dout_peri_uart2
|
||||
- const: dout_peri_usi0
|
||||
- const: dout_peri_usi1
|
||||
- const: dout_peri_usi2
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- "#clock-cells"
|
||||
- clocks
|
||||
- clock-names
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
# Clock controller node for CMU_PERI
|
||||
- |
|
||||
#include <dt-bindings/clock/exynos7885.h>
|
||||
|
||||
cmu_peri: clock-controller@10010000 {
|
||||
compatible = "samsung,exynos7885-cmu-peri";
|
||||
reg = <0x10010000 0x8000>;
|
||||
#clock-cells = <1>;
|
||||
|
||||
clocks = <&oscclk>,
|
||||
<&cmu_top CLK_DOUT_PERI_BUS>,
|
||||
<&cmu_top CLK_DOUT_PERI_SPI0>,
|
||||
<&cmu_top CLK_DOUT_PERI_SPI1>,
|
||||
<&cmu_top CLK_DOUT_PERI_UART0>,
|
||||
<&cmu_top CLK_DOUT_PERI_UART1>,
|
||||
<&cmu_top CLK_DOUT_PERI_UART2>,
|
||||
<&cmu_top CLK_DOUT_PERI_USI0>,
|
||||
<&cmu_top CLK_DOUT_PERI_USI1>,
|
||||
<&cmu_top CLK_DOUT_PERI_USI2>;
|
||||
clock-names = "oscclk",
|
||||
"dout_peri_bus",
|
||||
"dout_peri_spi0",
|
||||
"dout_peri_spi1",
|
||||
"dout_peri_uart0",
|
||||
"dout_peri_uart1",
|
||||
"dout_peri_uart2",
|
||||
"dout_peri_usi0",
|
||||
"dout_peri_usi1",
|
||||
"dout_peri_usi2";
|
||||
};
|
||||
|
||||
...
|
||||
@ -32,6 +32,8 @@ properties:
|
||||
compatible:
|
||||
enum:
|
||||
- samsung,exynos850-cmu-top
|
||||
- samsung,exynos850-cmu-apm
|
||||
- samsung,exynos850-cmu-cmgp
|
||||
- samsung,exynos850-cmu-core
|
||||
- samsung,exynos850-cmu-dpu
|
||||
- samsung,exynos850-cmu-hsi
|
||||
@ -68,6 +70,42 @@ allOf:
|
||||
items:
|
||||
- const: oscclk
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynos850-cmu-apm
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (26 MHz)
|
||||
- description: CMU_APM bus clock (from CMU_TOP)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
- const: dout_clkcmu_apm_bus
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynos850-cmu-cmgp
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (26 MHz)
|
||||
- description: CMU_CMGP bus clock (from CMU_APM)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
- const: gout_clkcmu_cmgp_bus
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
|
||||
@ -0,0 +1,79 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/samsung,s5pv210-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Samsung S5P6442/S5PC110/S5PV210 SoC clock controller
|
||||
|
||||
maintainers:
|
||||
- Chanwoo Choi <cw00.choi@samsung.com>
|
||||
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
|
||||
- Sylwester Nawrocki <s.nawrocki@samsung.com>
|
||||
- Tomasz Figa <tomasz.figa@gmail.com>
|
||||
|
||||
description: |
|
||||
Expected external clocks, defined in DTS as fixed-rate clocks with a matching
|
||||
name::
|
||||
- "xxti" - external crystal oscillator connected to XXTI and XXTO pins of
|
||||
the SoC,
|
||||
- "xusbxti" - external crystal oscillator connected to XUSBXTI and XUSBXTO
|
||||
pins of the SoC,
|
||||
|
||||
All available clocks are defined as preprocessor macros in
|
||||
include/dt-bindings/clock/s5pv210.h header.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- samsung,s5pv210-clock
|
||||
- samsung,s5p6442-clock
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: xxti clock
|
||||
- description: xusbxti clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: xxti
|
||||
- const: xusbxti
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- "#clock-cells"
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/s5pv210.h>
|
||||
|
||||
xxti: clock-0 {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <0>;
|
||||
clock-output-names = "xxti";
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
xusbxti: clock-1 {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <0>;
|
||||
clock-output-names = "xusbxti";
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
clock-controller@e0100000 {
|
||||
compatible = "samsung,s5pv210-clock";
|
||||
reg = <0xe0100000 0x10000>;
|
||||
clock-names = "xxti", "xusbxti";
|
||||
clocks = <&xxti>, <&xusbxti>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
@ -0,0 +1,56 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/starfive,jh7100-clkgen.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: StarFive JH7100 Clock Generator
|
||||
|
||||
maintainers:
|
||||
- Geert Uytterhoeven <geert@linux-m68k.org>
|
||||
- Emil Renner Berthing <kernel@esmil.dk>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: starfive,jh7100-clkgen
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Main clock source (25 MHz)
|
||||
- description: Application-specific clock source (12-27 MHz)
|
||||
- description: RMII reference clock (50 MHz)
|
||||
- description: RGMII RX clock (125 MHz)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: osc_sys
|
||||
- const: osc_aud
|
||||
- const: gmac_rmii_ref
|
||||
- const: gmac_gr_mii_rxclk
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
description:
|
||||
See <dt-bindings/clock/starfive-jh7100.h> for valid indices.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#clock-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
clock-controller@11800000 {
|
||||
compatible = "starfive,jh7100-clkgen";
|
||||
reg = <0x11800000 0x10000>;
|
||||
clocks = <&osc_sys>, <&osc_aud>, <&gmac_rmii_ref>, <&gmac_gr_mii_rxclk>;
|
||||
clock-names = "osc_sys", "osc_aud", "gmac_rmii_ref", "gmac_gr_mii_rxclk";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
@ -0,0 +1,57 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/toshiba,tmpv770x-pipllct.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Toshiba Visconti5 TMPV770X PLL Controller Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
|
||||
|
||||
description:
|
||||
Toshia Visconti5 PLL controller which supports the PLLs on TMPV770X.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: toshiba,tmpv7708-pipllct
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
clocks:
|
||||
description: External reference clock (OSC2)
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- "#clock-cells"
|
||||
- clocks
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
||||
osc2_clk: osc2-clk {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <20000000>;
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
pipllct: clock-controller@24220000 {
|
||||
compatible = "toshiba,tmpv7708-pipllct";
|
||||
reg = <0 0x24220000 0 0x820>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&osc2_clk>;
|
||||
};
|
||||
};
|
||||
...
|
||||
@ -0,0 +1,52 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/toshiba,tmpv770x-pismu.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Toshiba Visconti5 TMPV770x SMU controller Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
|
||||
|
||||
description:
|
||||
Toshia Visconti5 SMU (System Management Unit) which supports the clock
|
||||
and resets on TMPV770x.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: toshiba,tmpv7708-pismu
|
||||
- const: syscon
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- "#clock-cells"
|
||||
- "#reset-cells"
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
pismu: syscon@24200000 {
|
||||
compatible = "toshiba,tmpv7708-pismu", "syscon";
|
||||
reg = <0 0x24200000 0 0x2140>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
};
|
||||
...
|
||||
@ -44,6 +44,16 @@ properties:
|
||||
- const: ahb
|
||||
- const: mod
|
||||
|
||||
dmas:
|
||||
items:
|
||||
- description: RX DMA Channel
|
||||
- description: TX DMA Channel
|
||||
|
||||
dma-names:
|
||||
items:
|
||||
- const: rx
|
||||
- const: tx
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
|
||||
43
sys/contrib/device-tree/Bindings/crypto/qcom,prng.yaml
Normal file
43
sys/contrib/device-tree/Bindings/crypto/qcom,prng.yaml
Normal file
@ -0,0 +1,43 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/crypto/qcom,prng.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Pseudo Random Number Generator
|
||||
|
||||
maintainers:
|
||||
- Vinod Koul <vkoul@kernel.org>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,prng # 8916 etc.
|
||||
- qcom,prng-ee # 8996 and later using EE
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: core
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
rng@f9bff000 {
|
||||
compatible = "qcom,prng";
|
||||
reg = <0xf9bff000 0x200>;
|
||||
clocks = <&clk 125>;
|
||||
clock-names = "core";
|
||||
};
|
||||
@ -10,6 +10,9 @@ title: Amlogic specific extensions to the Synopsys Designware HDMI Controller
|
||||
maintainers:
|
||||
- Neil Armstrong <narmstrong@baylibre.com>
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/sound/name-prefix.yaml#
|
||||
|
||||
description: |
|
||||
The Amlogic Meson Synopsys Designware Integration is composed of
|
||||
- A Synopsys DesignWare HDMI Controller IP
|
||||
@ -99,6 +102,8 @@ properties:
|
||||
"#sound-dai-cells":
|
||||
const: 0
|
||||
|
||||
sound-name-prefix: true
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
@ -78,6 +78,10 @@ properties:
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
amlogic,canvas:
|
||||
description: should point to a canvas provider node
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
description: phandle to the associated power domain
|
||||
@ -106,6 +110,7 @@ required:
|
||||
- port@1
|
||||
- "#address-cells"
|
||||
- "#size-cells"
|
||||
- amlogic,canvas
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
@ -118,6 +123,7 @@ examples:
|
||||
interrupts = <3>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
amlogic,canvas = <&canvas>;
|
||||
|
||||
/* CVBS VDAC output port */
|
||||
port@0 {
|
||||
|
||||
@ -43,12 +43,53 @@ properties:
|
||||
vdd33-supply:
|
||||
description: Regulator that provides the supply 3.3V power.
|
||||
|
||||
analogix,lane0-swing:
|
||||
$ref: /schemas/types.yaml#/definitions/uint8-array
|
||||
minItems: 1
|
||||
maxItems: 20
|
||||
description:
|
||||
an array of swing register setting for DP tx lane0 PHY.
|
||||
Registers 0~9 are Swing0_Pre0, Swing1_Pre0, Swing2_Pre0,
|
||||
Swing3_Pre0, Swing0_Pre1, Swing1_Pre1, Swing2_Pre1, Swing0_Pre2,
|
||||
Swing1_Pre2, Swing0_Pre3, they are for [Boost control] and
|
||||
[Swing control] setting.
|
||||
Registers 0~9, bit 3:0 is [Boost control], these bits control
|
||||
post cursor manual, increase the [Boost control] to increase
|
||||
Pre-emphasis value.
|
||||
Registers 0~9, bit 6:4 is [Swing control], these bits control
|
||||
swing manual, increase [Swing control] setting to add Vp-p value
|
||||
for each Swing, Pre.
|
||||
Registers 10~19 are Swing0_Pre0, Swing1_Pre0, Swing2_Pre0,
|
||||
Swing3_Pre0, Swing0_Pre1, Swing1_Pre1, Swing2_Pre1, Swing0_Pre2,
|
||||
Swing1_Pre2, Swing0_Pre3, they are for [R select control] and
|
||||
[R Termination control] setting.
|
||||
Registers 10~19, bit 4:0 is [R select control], these bits are
|
||||
compensation manual, increase it can enhance IO driven strength
|
||||
and Vp-p.
|
||||
Registers 10~19, bit 5:6 is [R termination control], these bits
|
||||
adjust 50ohm impedance of DP tx termination. 00:55 ohm,
|
||||
01:50 ohm(default), 10:45 ohm, 11:40 ohm.
|
||||
|
||||
analogix,lane1-swing:
|
||||
$ref: /schemas/types.yaml#/definitions/uint8-array
|
||||
minItems: 1
|
||||
maxItems: 20
|
||||
description:
|
||||
an array of swing register setting for DP tx lane1 PHY.
|
||||
DP TX lane1 swing register setting same with lane0
|
||||
swing, please refer lane0-swing property description.
|
||||
|
||||
analogix,audio-enable:
|
||||
type: boolean
|
||||
description: let the driver enable audio HDMI codec function or not.
|
||||
|
||||
ports:
|
||||
$ref: /schemas/graph.yaml#/properties/ports
|
||||
|
||||
properties:
|
||||
port@0:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
$ref: /schemas/graph.yaml#/$defs/port-base
|
||||
unevaluatedProperties: false
|
||||
description:
|
||||
Video port for MIPI DSI input.
|
||||
|
||||
@ -87,6 +128,9 @@ examples:
|
||||
vdd10-supply = <&pp1000_mipibrdg>;
|
||||
vdd18-supply = <&pp1800_mipibrdg>;
|
||||
vdd33-supply = <&pp3300_mipibrdg>;
|
||||
analogix,audio-enable;
|
||||
analogix,lane0-swing = /bits/ 8 <0x14 0x54 0x64 0x74>;
|
||||
analogix,lane1-swing = /bits/ 8 <0x14 0x54 0x64 0x74>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
|
||||
@ -7,7 +7,9 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
title: Analogix ANX7814 SlimPort (Full-HD Transmitter)
|
||||
|
||||
maintainers:
|
||||
- Enric Balletbo i Serra <enric.balletbo@collabora.com>
|
||||
- Andrzej Hajda <andrzej.hajda@intel.com>
|
||||
- Neil Armstrong <narmstrong@baylibre.com>
|
||||
- Robert Foss <robert.foss@linaro.org>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
||||
@ -8,7 +8,6 @@ title: ChromeOS EC ANX7688 HDMI to DP Converter through Type-C Port
|
||||
|
||||
maintainers:
|
||||
- Nicolas Boichat <drinkcat@chromium.org>
|
||||
- Enric Balletbo i Serra <enric.balletbo@collabora.com>
|
||||
|
||||
description: |
|
||||
ChromeOS EC ANX7688 is a display bridge that converts HDMI 2.0 to
|
||||
|
||||
@ -79,6 +79,14 @@ properties:
|
||||
- port@0
|
||||
- port@1
|
||||
|
||||
pclk-sample:
|
||||
description:
|
||||
Data sampling on rising or falling edge.
|
||||
enum:
|
||||
- 0 # Falling edge
|
||||
- 1 # Rising edge
|
||||
default: 0
|
||||
|
||||
powerdown-gpios:
|
||||
description:
|
||||
The GPIO used to control the power down line of this device.
|
||||
@ -86,21 +94,32 @@ properties:
|
||||
|
||||
power-supply: true
|
||||
|
||||
if:
|
||||
not:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: lvds-decoder
|
||||
then:
|
||||
properties:
|
||||
ports:
|
||||
allOf:
|
||||
- if:
|
||||
not:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: lvds-decoder
|
||||
then:
|
||||
properties:
|
||||
port@0:
|
||||
ports:
|
||||
properties:
|
||||
endpoint:
|
||||
port@0:
|
||||
properties:
|
||||
data-mapping: false
|
||||
endpoint:
|
||||
properties:
|
||||
data-mapping: false
|
||||
|
||||
- if:
|
||||
not:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: lvds-encoder
|
||||
then:
|
||||
properties:
|
||||
pclk-sample: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
106
sys/contrib/device-tree/Bindings/display/bridge/nxp,ptn3460.yaml
Normal file
106
sys/contrib/device-tree/Bindings/display/bridge/nxp,ptn3460.yaml
Normal file
@ -0,0 +1,106 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/bridge/nxp,ptn3460.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: NXP PTN3460 eDP to LVDS bridge
|
||||
|
||||
maintainers:
|
||||
- Sean Paul <seanpaul@chromium.org>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: nxp,ptn3460
|
||||
|
||||
reg:
|
||||
description: I2C address of the bridge
|
||||
maxItems: 1
|
||||
|
||||
edid-emulation:
|
||||
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||
description:
|
||||
The EDID emulation entry to use
|
||||
Value Resolution Description
|
||||
0 1024x768 NXP Generic
|
||||
1 1920x1080 NXP Generic
|
||||
2 1920x1080 NXP Generic
|
||||
3 1600x900 Samsung LTM200KT
|
||||
4 1920x1080 Samsung LTM230HT
|
||||
5 1366x768 NXP Generic
|
||||
6 1600x900 ChiMei M215HGE
|
||||
enum: [0, 1, 2, 3, 4, 5, 6]
|
||||
|
||||
powerdown-gpios:
|
||||
description: GPIO connected to the PD_N signal.
|
||||
maxItems: 1
|
||||
|
||||
reset-gpios:
|
||||
description: GPIO connected to the RST_N signal.
|
||||
maxItems: 1
|
||||
|
||||
ports:
|
||||
$ref: /schemas/graph.yaml#/properties/ports
|
||||
|
||||
properties:
|
||||
port@0:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description:
|
||||
Video port for LVDS output
|
||||
|
||||
port@1:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description:
|
||||
Video port for eDP input
|
||||
|
||||
required:
|
||||
- port@0
|
||||
- port@1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- edid-emulation
|
||||
- powerdown-gpios
|
||||
- reset-gpios
|
||||
- ports
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
i2c1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
bridge@20 {
|
||||
compatible = "nxp,ptn3460";
|
||||
reg = <0x20>;
|
||||
edid-emulation = <5>;
|
||||
powerdown-gpios = <&gpy2 5 GPIO_ACTIVE_HIGH>;
|
||||
reset-gpios = <&gpx1 5 GPIO_ACTIVE_LOW>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
bridge_out: endpoint {
|
||||
remote-endpoint = <&panel_in>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
bridge_in: endpoint {
|
||||
remote-endpoint = <&dp_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
...
|
||||
@ -8,7 +8,6 @@ title: MIPI DSI to eDP Video Format Converter Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- Nicolas Boichat <drinkcat@chromium.org>
|
||||
- Enric Balletbo i Serra <enric.balletbo@collabora.com>
|
||||
|
||||
description: |
|
||||
The PS8640 is a low power MIPI-to-eDP video format converter supporting
|
||||
|
||||
@ -0,0 +1,118 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/bridge/renesas,dsi-csi2-tx.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Renesas R-Car MIPI DSI/CSI-2 Encoder
|
||||
|
||||
maintainers:
|
||||
- Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
|
||||
|
||||
description: |
|
||||
This binding describes the MIPI DSI/CSI-2 encoder embedded in the Renesas
|
||||
R-Car V3U SoC. The encoder can operate in either DSI or CSI-2 mode, with up
|
||||
to four data lanes.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- renesas,r8a779a0-dsi-csi2-tx # for V3U
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Functional clock
|
||||
- description: DSI (and CSI-2) functional clock
|
||||
- description: PLL reference clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: fck
|
||||
- const: dsi
|
||||
- const: pll
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
ports:
|
||||
$ref: /schemas/graph.yaml#/properties/ports
|
||||
|
||||
properties:
|
||||
port@0:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: Parallel input port
|
||||
|
||||
port@1:
|
||||
$ref: /schemas/graph.yaml#/$defs/port-base
|
||||
unevaluatedProperties: false
|
||||
description: DSI/CSI-2 output port
|
||||
|
||||
properties:
|
||||
endpoint:
|
||||
$ref: /schemas/media/video-interfaces.yaml#
|
||||
unevaluatedProperties: false
|
||||
|
||||
properties:
|
||||
data-lanes:
|
||||
minItems: 1
|
||||
maxItems: 4
|
||||
|
||||
required:
|
||||
- data-lanes
|
||||
|
||||
required:
|
||||
- port@0
|
||||
- port@1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- power-domains
|
||||
- resets
|
||||
- ports
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/r8a779a0-cpg-mssr.h>
|
||||
#include <dt-bindings/power/r8a779a0-sysc.h>
|
||||
|
||||
dsi0: dsi-encoder@fed80000 {
|
||||
compatible = "renesas,r8a779a0-dsi-csi2-tx";
|
||||
reg = <0xfed80000 0x10000>;
|
||||
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
||||
clocks = <&cpg CPG_MOD 415>,
|
||||
<&cpg CPG_CORE R8A779A0_CLK_DSI>,
|
||||
<&cpg CPG_CORE R8A779A0_CLK_CP>;
|
||||
clock-names = "fck", "dsi", "pll";
|
||||
resets = <&cpg 415>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
dsi0_in: endpoint {
|
||||
remote-endpoint = <&du_out_dsi0>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
dsi0_out: endpoint {
|
||||
data-lanes = <1 2>;
|
||||
remote-endpoint = <&sn65dsi86_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
...
|
||||
110
sys/contrib/device-tree/Bindings/display/bridge/sil,sii9234.yaml
Normal file
110
sys/contrib/device-tree/Bindings/display/bridge/sil,sii9234.yaml
Normal file
@ -0,0 +1,110 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/bridge/sil,sii9234.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Silicon Image SiI9234 HDMI/MHL bridge
|
||||
|
||||
maintainers:
|
||||
- Maciej Purski <m.purski@samsung.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: sil,sii9234
|
||||
|
||||
reg:
|
||||
description: I2C address for TPI interface
|
||||
maxItems: 1
|
||||
|
||||
avcc12-supply:
|
||||
description: TMDS Analog Supply Voltage, 1.2V
|
||||
|
||||
avcc33-supply:
|
||||
description: MHL/USB Switch Supply Voltage, 3.3V
|
||||
|
||||
cvcc12-supply:
|
||||
description: Digital Core Supply Voltage, 1.2V
|
||||
|
||||
iovcc18-supply:
|
||||
description: I/O voltage supply, 1.8V
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
reset-gpios:
|
||||
description: GPIO connected to the reset pin.
|
||||
maxItems: 1
|
||||
|
||||
ports:
|
||||
$ref: /schemas/graph.yaml#/properties/ports
|
||||
|
||||
properties:
|
||||
port@0:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description:
|
||||
Video port for HDMI (encoder) input
|
||||
|
||||
port@1:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description:
|
||||
MHL to connector port
|
||||
|
||||
required:
|
||||
- port@0
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- avcc12-supply
|
||||
- avcc33-supply
|
||||
- cvcc12-supply
|
||||
- iovcc18-supply
|
||||
- interrupts
|
||||
- reset-gpios
|
||||
- ports
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
i2c1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
bridge@39 {
|
||||
compatible = "sil,sii9234";
|
||||
reg = <0x39>;
|
||||
avcc12-supply = <&vsil12>;
|
||||
avcc33-supply = <&vcc33mhl>;
|
||||
cvcc12-supply = <&vsil12>;
|
||||
iovcc18-supply = <&vcc18mhl>;
|
||||
interrupt-parent = <&gpf3>;
|
||||
interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reset-gpios = <&gpf3 4 GPIO_ACTIVE_LOW>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
mhl_to_hdmi: endpoint {
|
||||
remote-endpoint = <&hdmi_to_mhl>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
mhl_to_connector: endpoint {
|
||||
remote-endpoint = <&connector_to_mhl>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
...
|
||||
@ -17,6 +17,8 @@ properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,sc7180-dp
|
||||
- qcom,sc7280-dp
|
||||
- qcom,sc7280-edp
|
||||
- qcom,sc8180x-dp
|
||||
- qcom,sc8180x-edp
|
||||
|
||||
|
||||
@ -31,13 +31,11 @@ properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: Display AHB clock from gcc
|
||||
- description: Display AXI clock
|
||||
- description: Display core clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: iface
|
||||
- const: bus
|
||||
- const: core
|
||||
|
||||
interrupts:
|
||||
@ -160,9 +158,8 @@ examples:
|
||||
power-domains = <&dispcc MDSS_GDSC>;
|
||||
|
||||
clocks = <&gcc GCC_DISP_AHB_CLK>,
|
||||
<&gcc GCC_DISP_AXI_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_MDP_CLK>;
|
||||
clock-names = "iface", "bus", "core";
|
||||
clock-names = "iface", "core";
|
||||
|
||||
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
|
||||
@ -6,15 +6,12 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Asia Better Technology 3.0" (320x480 pixels) 24-bit IPS LCD panel
|
||||
|
||||
description: |
|
||||
The panel must obey the rules for a SPI slave device as specified in
|
||||
spi/spi-controller.yaml
|
||||
|
||||
maintainers:
|
||||
- Paul Cercueil <paul@crapouillou.net>
|
||||
|
||||
allOf:
|
||||
- $ref: panel-common.yaml#
|
||||
- $ref: /schemas/spi/spi-peripheral-props.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
||||
@ -0,0 +1,81 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/panel/boe,bf060y8m-aj0.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: BOE BF060Y8M-AJ0 5.99" 1080x2160 AMOLED Panel
|
||||
|
||||
maintainers:
|
||||
- AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
|
||||
|
||||
description: |
|
||||
This is a 5.99" 1080x2160 16.7M Color active matrix AMOLED
|
||||
video mode panel module on MIPI-DSI 4-Lane interface, GGRB
|
||||
pixel arrangement, 63 micrometers pitch, with an active
|
||||
area of 68.04 x 136.08 millimeters.
|
||||
Each pixel is divided into red and green dots, or blue and
|
||||
green dots, and two pixels share red or blue dots which are
|
||||
arranged in vertical stripe.
|
||||
The DriverIC for this panel module is SW43404.
|
||||
|
||||
allOf:
|
||||
- $ref: panel-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: boe,bf060y8m-aj0
|
||||
|
||||
elvdd-supply:
|
||||
description: EL Driving positive (VDD) supply (4.40-4.80V)
|
||||
elvss-supply:
|
||||
description: EL Driving negative (VSS) supply (-5.00V to -1.40V)
|
||||
vcc-supply:
|
||||
description: Core (TSP) voltage supply (2.70-3.60V)
|
||||
vci-supply:
|
||||
description: DriverIC Operation supply (2.60-3.60V)
|
||||
vddio-supply:
|
||||
description: I/O voltage supply (1.62-1.98V)
|
||||
|
||||
port: true
|
||||
reg: true
|
||||
reset-gpios: true
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- elvdd-supply
|
||||
- elvss-supply
|
||||
- vcc-supply
|
||||
- vci-supply
|
||||
- vddio-supply
|
||||
- reg
|
||||
- reset-gpios
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
dsi {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
panel@0 {
|
||||
compatible = "boe,bf060y8m-aj0";
|
||||
reg = <0>;
|
||||
|
||||
reset-gpios = <&tlmm 94 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
vcc-supply = <&disp_vcc_vreg>;
|
||||
vddio-supply = <&disp_vddio_vreg>;
|
||||
vci-supply = <&disp_vci_vreg>;
|
||||
elvdd-supply = <&disp_elvdd_vreg>;
|
||||
elvss-supply = <&disp_elvss_vreg>;
|
||||
|
||||
port {
|
||||
panel_in: endpoint {
|
||||
remote-endpoint = <&dsi0_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -0,0 +1,69 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/panel/ilitek,ili9163.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Ilitek ILI9163 display panels device tree bindings
|
||||
|
||||
maintainers:
|
||||
- Daniel Mack <daniel@zonque.org>
|
||||
|
||||
description:
|
||||
This binding is for display panels using an Ilitek ILI9163 controller in SPI
|
||||
mode.
|
||||
|
||||
allOf:
|
||||
- $ref: panel-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- newhaven,1.8-128160EF
|
||||
- const: ilitek,ili9163
|
||||
|
||||
spi-max-frequency:
|
||||
maximum: 32000000
|
||||
|
||||
dc-gpios:
|
||||
maxItems: 1
|
||||
description: Display data/command selection (D/CX)
|
||||
|
||||
backlight: true
|
||||
reg: true
|
||||
reset-gpios: true
|
||||
rotation: true
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- dc-gpios
|
||||
- reset-gpios
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
backlight: backlight {
|
||||
compatible = "gpio-backlight";
|
||||
gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
spi {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
display@0 {
|
||||
compatible = "newhaven,1.8-128160EF", "ilitek,ili9163";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <32000000>;
|
||||
dc-gpios = <&gpio0 24 GPIO_ACTIVE_HIGH>;
|
||||
reset-gpios = <&gpio0 25 GPIO_ACTIVE_HIGH>;
|
||||
rotation = <180>;
|
||||
backlight = <&backlight>;
|
||||
};
|
||||
};
|
||||
|
||||
...
|
||||
@ -15,11 +15,9 @@ description: |
|
||||
960 TFT source driver pins and 240 TFT gate driver pins, VCOM, VCOML and
|
||||
VCOMH outputs.
|
||||
|
||||
The panel must obey the rules for a SPI slave device as specified in
|
||||
spi/spi-controller.yaml
|
||||
|
||||
allOf:
|
||||
- $ref: panel-common.yaml#
|
||||
- $ref: /schemas/spi/spi-peripheral-props.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
||||
@ -9,24 +9,28 @@ title: Ilitek ILI9881c based MIPI-DSI panels
|
||||
maintainers:
|
||||
- Maxime Ripard <mripard@kernel.org>
|
||||
|
||||
allOf:
|
||||
- $ref: panel-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- bananapi,lhr050h41
|
||||
- feixin,k101-im2byl02
|
||||
- wanchanglong,w552946aba
|
||||
- const: ilitek,ili9881c
|
||||
|
||||
backlight: true
|
||||
power-supply: true
|
||||
reg: true
|
||||
reset-gpios: true
|
||||
rotation: true
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- power-supply
|
||||
- reg
|
||||
- reset-gpios
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
|
||||
@ -6,15 +6,12 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Innolux EJ030NA 3.0" (320x480 pixels) 24-bit TFT LCD panel
|
||||
|
||||
description: |
|
||||
The panel must obey the rules for a SPI slave device as specified in
|
||||
spi/spi-controller.yaml
|
||||
|
||||
maintainers:
|
||||
- Paul Cercueil <paul@crapouillou.net>
|
||||
|
||||
allOf:
|
||||
- $ref: panel-common.yaml#
|
||||
- $ref: /schemas/spi/spi-peripheral-props.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
||||
@ -35,6 +35,8 @@ properties:
|
||||
phandle of the gpio for power ic line
|
||||
Power IC supply enable, High active
|
||||
|
||||
port: true
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
@ -6,15 +6,12 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: King Display KD035G6-54NT 3.5" (320x240 pixels) 24-bit TFT LCD panel
|
||||
|
||||
description: |
|
||||
The panel must obey the rules for a SPI slave device as specified in
|
||||
spi/spi-controller.yaml
|
||||
|
||||
maintainers:
|
||||
- Paul Cercueil <paul@crapouillou.net>
|
||||
|
||||
allOf:
|
||||
- $ref: panel-common.yaml#
|
||||
- $ref: /schemas/spi/spi-peripheral-props.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
||||
@ -6,15 +6,12 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: LG.Philips LB035Q02 Panel
|
||||
|
||||
description: |
|
||||
The panel must obey the rules for a SPI slave device as specified in
|
||||
spi/spi-controller.yaml
|
||||
|
||||
maintainers:
|
||||
- Tomi Valkeinen <tomi.valkeinen@ti.com>
|
||||
|
||||
allOf:
|
||||
- $ref: panel-common.yaml#
|
||||
- $ref: /schemas/spi/spi-peripheral-props.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
||||
@ -0,0 +1,106 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/panel/novatek,nt35950.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Novatek NT35950-based display panels
|
||||
|
||||
maintainers:
|
||||
- AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
|
||||
|
||||
description: |
|
||||
The nt35950 IC from Novatek is a Driver IC used to drive MIPI-DSI panels,
|
||||
with Static RAM for content retention in command mode and also supports
|
||||
video mode with VESA Frame Buffer Compression or Display Stream Compression
|
||||
on single, or dual dsi port(s).
|
||||
This DDIC is also capable of upscaling an input image to the panel's native
|
||||
resolution, for example it can upscale a 1920x1080 input to 3840x2160 with
|
||||
either bilinear interpolation or pixel duplication.
|
||||
|
||||
allOf:
|
||||
- $ref: panel-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- sharp,ls055d1sx04
|
||||
- const: novatek,nt35950
|
||||
description: This indicates the panel manufacturer of the panel
|
||||
that is in turn using the NT35950 panel driver. The compatible
|
||||
string determines how the NT35950 panel driver shall be configured
|
||||
to work with the indicated panel. The novatek,nt35950 compatible shall
|
||||
always be provided as a fallback.
|
||||
|
||||
reset-gpios:
|
||||
maxItems: 1
|
||||
description: phandle of gpio for reset line - This should be 8mA, gpio
|
||||
can be configured using mux, pinctrl, pinctrl-names (active high)
|
||||
|
||||
avdd-supply:
|
||||
description: positive boost supply regulator
|
||||
avee-supply:
|
||||
description: negative boost supply regulator
|
||||
dvdd-supply:
|
||||
description: regulator that supplies the digital voltage
|
||||
vddio-supply:
|
||||
description: regulator that supplies the I/O voltage
|
||||
|
||||
backlight: true
|
||||
ports: true
|
||||
reg: true
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reset-gpios
|
||||
- avdd-supply
|
||||
- avee-supply
|
||||
- dvdd-supply
|
||||
- vddio-supply
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
dsi0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
panel@0 {
|
||||
compatible = "sharp,ls055d1sx04", "novatek,nt35950";
|
||||
reg = <0>;
|
||||
|
||||
backlight = <&pmi8998_wled>;
|
||||
reset-gpios = <&tlmm 94 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
avdd-supply = <&lab>;
|
||||
avee-supply = <&ibb>;
|
||||
dvdd-supply = <&disp_dvdd_vreg>;
|
||||
vddio-supply = <&vreg_l14a_1p85>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
panel_in0: endpoint {
|
||||
remote-endpoint = <&dsi0_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
panel_in1: endpoint {
|
||||
remote-endpoint = <&dsi1_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
...
|
||||
@ -34,7 +34,7 @@ properties:
|
||||
description: phandle of gpio for reset line - This should be 8mA, gpio
|
||||
can be configured using mux, pinctrl, pinctrl-names (active high)
|
||||
|
||||
vddio-supply:
|
||||
vddi0-supply:
|
||||
description: phandle of the regulator that provides the supply voltage
|
||||
Power IC supply
|
||||
|
||||
@ -75,8 +75,6 @@ examples:
|
||||
|
||||
reset-gpios = <&tlmm 6 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
port {
|
||||
tianma_nt36672a_in_0: endpoint {
|
||||
remote-endpoint = <&dsi0_out>;
|
||||
|
||||
@ -35,6 +35,8 @@ properties:
|
||||
- boe,tv080wum-nl0
|
||||
# Innolux P079ZCA 7.85" 768x1024 TFT LCD panel
|
||||
- innolux,p079zca
|
||||
# JDI FHD_R63452 1080x1920 5.2" IPS LCD Panel
|
||||
- jdi,fhd-r63452
|
||||
# Khadas TS050 5" 1080x1920 LCD panel
|
||||
- khadas,ts050
|
||||
# Kingdisplay KD097D04 9.7" 1536x2048 TFT LCD panel
|
||||
|
||||
@ -290,6 +290,8 @@ properties:
|
||||
- starry,kr070pe2t
|
||||
# Starry 12.2" (1920x1200 pixels) TFT LCD panel
|
||||
- starry,kr122ea0sra
|
||||
# Team Source Display Technology TST043015CMHX 4.3" WQVGA TFT LCD panel
|
||||
- team-source-display,tst043015cmhx
|
||||
# Tianma Micro-electronics TM070JDHG30 7.0" WXGA TFT LCD panel
|
||||
- tianma,tm070jdhg30
|
||||
# Tianma Micro-electronics TM070JVHG33 7.0" WXGA TFT LCD panel
|
||||
|
||||
@ -6,15 +6,12 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Samsung LD9040 AMOLED LCD parallel RGB panel with SPI control bus
|
||||
|
||||
description: |
|
||||
The panel must obey the rules for a SPI slave device as specified in
|
||||
spi/spi-controller.yaml
|
||||
|
||||
maintainers:
|
||||
- Andrzej Hajda <a.hajda@samsung.com>
|
||||
|
||||
allOf:
|
||||
- $ref: panel-common.yaml#
|
||||
- $ref: /schemas/spi/spi-peripheral-props.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
@ -63,8 +60,6 @@ examples:
|
||||
|
||||
lcd@0 {
|
||||
compatible = "samsung,ld9040";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
reg = <0>;
|
||||
vdd3-supply = <&ldo7_reg>;
|
||||
|
||||
@ -12,6 +12,7 @@ maintainers:
|
||||
allOf:
|
||||
- $ref: panel-common.yaml#
|
||||
- $ref: /schemas/leds/backlight/common.yaml#
|
||||
- $ref: /schemas/spi/spi-peripheral-props.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
||||
@ -6,15 +6,12 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Sitronix ST7789V RGB panel with SPI control bus
|
||||
|
||||
description: |
|
||||
The panel must obey the rules for a SPI slave device as specified in
|
||||
spi/spi-controller.yaml
|
||||
|
||||
maintainers:
|
||||
- Maxime Ripard <mripard@kernel.org>
|
||||
|
||||
allOf:
|
||||
- $ref: panel-common.yaml#
|
||||
- $ref: /schemas/spi/spi-peripheral-props.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
||||
@ -6,15 +6,12 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Sony ACX565AKM SDI Panel
|
||||
|
||||
description: |
|
||||
The panel must obey the rules for a SPI slave device as specified in
|
||||
spi/spi-controller.yaml
|
||||
|
||||
maintainers:
|
||||
- Tomi Valkeinen <tomi.valkeinen@ti.com>
|
||||
|
||||
allOf:
|
||||
- $ref: panel-common.yaml#
|
||||
- $ref: /schemas/spi/spi-peripheral-props.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
||||
@ -0,0 +1,72 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/panel/sony,tulip-truly-nt35521.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Sony Tulip Truly NT35521 5.24" 1280x720 MIPI-DSI Panel
|
||||
|
||||
maintainers:
|
||||
- Shawn Guo <shawn.guo@linaro.org>
|
||||
|
||||
description: |
|
||||
The Sony Tulip Truly NT35521 is a 5.24" 1280x720 MIPI-DSI panel, which
|
||||
can be found no Sony Xperia M4 phone. The panel backlight is managed
|
||||
through DSI link.
|
||||
|
||||
allOf:
|
||||
- $ref: panel-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: sony,tulip-truly-nt35521
|
||||
|
||||
reg: true
|
||||
|
||||
positive5-supply:
|
||||
description: Positive 5V supply
|
||||
|
||||
negative5-supply:
|
||||
description: Negative 5V supply
|
||||
|
||||
reset-gpios: true
|
||||
|
||||
enable-gpios: true
|
||||
|
||||
port: true
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- positive5-supply
|
||||
- negative5-supply
|
||||
- reset-gpios
|
||||
- enable-gpios
|
||||
- port
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
dsi {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
panel@0 {
|
||||
compatible = "sony,tulip-truly-nt35521";
|
||||
reg = <0>;
|
||||
positive5-supply = <&positive5_reg>;
|
||||
negative5-supply = <&negative5_reg>;
|
||||
reset-gpios = <&msmgpio 25 GPIO_ACTIVE_LOW>;
|
||||
enable-gpios = <&msmgpio 10 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
port {
|
||||
panel_in: endpoint {
|
||||
remote-endpoint = <&dsi0_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
...
|
||||
@ -6,16 +6,13 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Toppoly TD Panels
|
||||
|
||||
description: |
|
||||
The panel must obey the rules for a SPI slave device as specified in
|
||||
spi/spi-controller.yaml
|
||||
|
||||
maintainers:
|
||||
- Marek Belisko <marek@goldelico.com>
|
||||
- H. Nikolaus Schaller <hns@goldelico.com>
|
||||
|
||||
allOf:
|
||||
- $ref: panel-common.yaml#
|
||||
- $ref: /schemas/spi/spi-peripheral-props.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
||||
@ -26,14 +26,6 @@ properties:
|
||||
clock-names:
|
||||
const: hclk
|
||||
|
||||
pinctrl-0:
|
||||
maxItems: 2
|
||||
|
||||
pinctrl-names:
|
||||
const: default
|
||||
description:
|
||||
Switch the iomux for the HPD/I2C pins to HDMI function.
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
|
||||
@ -83,13 +83,25 @@ properties:
|
||||
format:
|
||||
description: >
|
||||
Format of the framebuffer:
|
||||
* `a1r5g5b5` - 16-bit pixels, d[15]=a, d[14:10]=r, d[9:5]=g, d[4:0]=b
|
||||
* `a2r10g10b10` - 32-bit pixels, d[31:30]=a, d[29:20]=r, d[19:10]=g, d[9:0]=b
|
||||
* `a8b8g8r8` - 32-bit pixels, d[31:24]=a, d[23:16]=b, d[15:8]=g, d[7:0]=r
|
||||
* `a8r8g8b8` - 32-bit pixels, d[31:24]=a, d[23:16]=r, d[15:8]=g, d[7:0]=b
|
||||
* `r5g6b5` - 16-bit pixels, d[15:11]=r, d[10:5]=g, d[4:0]=b
|
||||
* `r5g5b5a1` - 16-bit pixels, d[15:11]=r, d[10:6]=g, d[5:1]=b d[1:0]=a
|
||||
* `r8g8b8` - 24-bit pixels, d[23:16]=r, d[15:8]=g, d[7:0]=b
|
||||
* `x1r5g5b5` - 16-bit pixels, d[14:10]=r, d[9:5]=g, d[4:0]=b
|
||||
* `x2r10g10b10` - 32-bit pixels, d[29:20]=r, d[19:10]=g, d[9:0]=b
|
||||
* `x8r8g8b8` - 32-bit pixels, d[23:16]=r, d[15:8]=g, d[7:0]=b
|
||||
enum:
|
||||
- a1r5g5b5
|
||||
- a2r10g10b10
|
||||
- a8b8g8r8
|
||||
- a8r8g8b8
|
||||
- r5g6b5
|
||||
- r5g5b5a1
|
||||
- r8g8b8
|
||||
- x1r5g5b5
|
||||
- x2r10g10b10
|
||||
- x8r8g8b8
|
||||
|
||||
|
||||
@ -0,0 +1,64 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/sprd/sprd,display-subsystem.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Unisoc DRM master device
|
||||
|
||||
maintainers:
|
||||
- Kevin Tang <kevin.tang@unisoc.com>
|
||||
|
||||
description: |
|
||||
The Unisoc DRM master device is a virtual device needed to list all
|
||||
DPU devices or other display interface nodes that comprise the
|
||||
graphics subsystem.
|
||||
|
||||
Unisoc's display pipeline have several components as below description,
|
||||
multi display controllers and corresponding physical interfaces.
|
||||
For different display scenarios, dpu0 and dpu1 maybe binding to different
|
||||
encoder.
|
||||
|
||||
E.g:
|
||||
dpu0 and dpu1 both binding to DSI for dual mipi-dsi display;
|
||||
dpu0 binding to DSI for primary display, and dpu1 binding to DP for external display;
|
||||
|
||||
+-----------------------------------------+
|
||||
| |
|
||||
| +---------+ |
|
||||
+----+ | +----+ +---------+ |DPHY/CPHY| | +------+
|
||||
| +----->+dpu0+--->+MIPI|DSI +--->+Combo +----->+Panel0|
|
||||
|AXI | | +----+ +---------+ +---------+ | +------+
|
||||
| | | ^ |
|
||||
| | | | |
|
||||
| | | +-----------+ |
|
||||
| | | | |
|
||||
|APB | | +--+-+ +-----------+ +---+ | +------+
|
||||
| +----->+dpu1+--->+DisplayPort+--->+PHY+--------->+Panel1|
|
||||
| | | +----+ +-----------+ +---+ | +------+
|
||||
+----+ | |
|
||||
+-----------------------------------------+
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: sprd,display-subsystem
|
||||
|
||||
ports:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
description:
|
||||
Should contain a list of phandles pointing to display interface port
|
||||
of DPU devices.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- ports
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
display-subsystem {
|
||||
compatible = "sprd,display-subsystem";
|
||||
ports = <&dpu_out>;
|
||||
};
|
||||
|
||||
@ -0,0 +1,77 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/sprd/sprd,sharkl3-dpu.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Unisoc Sharkl3 Display Processor Unit (DPU)
|
||||
|
||||
maintainers:
|
||||
- Kevin Tang <kevin.tang@unisoc.com>
|
||||
|
||||
description: |
|
||||
DPU (Display Processor Unit) is the Display Controller for the Unisoc SoCs
|
||||
which transfers the image data from a video memory buffer to an internal
|
||||
LCD interface.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: sprd,sharkl3-dpu
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
minItems: 2
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: clk_src_128m
|
||||
- const: clk_src_384m
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
iommus:
|
||||
maxItems: 1
|
||||
|
||||
port:
|
||||
type: object
|
||||
description:
|
||||
A port node with endpoint definitions as defined in
|
||||
Documentation/devicetree/bindings/media/video-interfaces.txt.
|
||||
That port should be the output endpoint, usually output to
|
||||
the associated DSI.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- clocks
|
||||
- clock-names
|
||||
- port
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/clock/sprd,sc9860-clk.h>
|
||||
dpu: dpu@63000000 {
|
||||
compatible = "sprd,sharkl3-dpu";
|
||||
reg = <0x63000000 0x1000>;
|
||||
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "clk_src_128m", "clk_src_384m";
|
||||
|
||||
clocks = <&pll CLK_TWPLL_128M>,
|
||||
<&pll CLK_TWPLL_384M>;
|
||||
|
||||
dpu_port: port {
|
||||
dpu_out: endpoint {
|
||||
remote-endpoint = <&dsi_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -0,0 +1,88 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/sprd/sprd,sharkl3-dsi-host.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Unisoc MIPI DSI Controller
|
||||
|
||||
maintainers:
|
||||
- Kevin Tang <kevin.tang@unisoc.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: sprd,sharkl3-dsi-host
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 2
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: clk_src_96m
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
ports:
|
||||
type: object
|
||||
|
||||
properties:
|
||||
"#address-cells":
|
||||
const: 1
|
||||
|
||||
"#size-cells":
|
||||
const: 0
|
||||
|
||||
port@0:
|
||||
type: object
|
||||
description:
|
||||
A port node with endpoint definitions as defined in
|
||||
Documentation/devicetree/bindings/media/video-interfaces.txt.
|
||||
That port should be the input endpoint, usually coming from
|
||||
the associated DPU.
|
||||
|
||||
required:
|
||||
- "#address-cells"
|
||||
- "#size-cells"
|
||||
- port@0
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- clocks
|
||||
- clock-names
|
||||
- ports
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/clock/sprd,sc9860-clk.h>
|
||||
dsi: dsi@63100000 {
|
||||
compatible = "sprd,sharkl3-dsi-host";
|
||||
reg = <0x63100000 0x1000>;
|
||||
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "clk_src_96m";
|
||||
clocks = <&pll CLK_TWPLL_96M>;
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
dsi_in: endpoint {
|
||||
remote-endpoint = <&dpu_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -110,7 +110,7 @@ examples:
|
||||
};
|
||||
};
|
||||
|
||||
panel-dsi@0 {
|
||||
panel@0 {
|
||||
compatible = "orisetech,otm8009a";
|
||||
reg = <0>;
|
||||
reset-gpios = <&gpioe 4 GPIO_ACTIVE_LOW>;
|
||||
@ -125,4 +125,3 @@ examples:
|
||||
};
|
||||
|
||||
...
|
||||
|
||||
|
||||
@ -19,6 +19,19 @@ Required properties:
|
||||
See ../reset/reset.txt for details.
|
||||
- reset-names: Must include the following entries:
|
||||
- host1x
|
||||
- mc
|
||||
|
||||
Optional properties:
|
||||
- operating-points-v2: See ../bindings/opp/opp.txt for details.
|
||||
- power-domains: Phandle to HEG or core power domain.
|
||||
|
||||
For each opp entry in 'operating-points-v2' table of host1x and its modules:
|
||||
- opp-supported-hw: One bitfield indicating:
|
||||
On Tegra20: SoC process ID mask
|
||||
On Tegra30+: SoC speedo ID mask
|
||||
|
||||
A bitwise AND is performed against the value and if any bit
|
||||
matches, the OPP gets enabled.
|
||||
|
||||
Each host1x client module having to perform DMA through the Memory Controller
|
||||
should have the interconnect endpoints set to the Memory Client and External
|
||||
@ -45,6 +58,8 @@ of the following host1x client modules:
|
||||
- interconnect-names: Must include name of the interconnect path for each
|
||||
interconnect entry. Consult TRM documentation for information about
|
||||
available memory clients, see MEMORY CONTROLLER section.
|
||||
- operating-points-v2: See ../bindings/opp/opp.txt for details.
|
||||
- power-domains: Phandle to MPE power domain.
|
||||
|
||||
- vi: video input
|
||||
|
||||
@ -128,6 +143,8 @@ of the following host1x client modules:
|
||||
- interconnect-names: Must include name of the interconnect path for each
|
||||
interconnect entry. Consult TRM documentation for information about
|
||||
available memory clients, see MEMORY CONTROLLER section.
|
||||
- operating-points-v2: See ../bindings/opp/opp.txt for details.
|
||||
- power-domains: Phandle to VENC power domain.
|
||||
|
||||
- epp: encoder pre-processor
|
||||
|
||||
@ -147,6 +164,8 @@ of the following host1x client modules:
|
||||
- interconnect-names: Must include name of the interconnect path for each
|
||||
interconnect entry. Consult TRM documentation for information about
|
||||
available memory clients, see MEMORY CONTROLLER section.
|
||||
- operating-points-v2: See ../bindings/opp/opp.txt for details.
|
||||
- power-domains: Phandle to HEG or core power domain.
|
||||
|
||||
- isp: image signal processor
|
||||
|
||||
@ -166,6 +185,7 @@ of the following host1x client modules:
|
||||
- interconnect-names: Must include name of the interconnect path for each
|
||||
interconnect entry. Consult TRM documentation for information about
|
||||
available memory clients, see MEMORY CONTROLLER section.
|
||||
- power-domains: Phandle to VENC or core power domain.
|
||||
|
||||
- gr2d: 2D graphics engine
|
||||
|
||||
@ -179,12 +199,15 @@ of the following host1x client modules:
|
||||
See ../reset/reset.txt for details.
|
||||
- reset-names: Must include the following entries:
|
||||
- 2d
|
||||
- mc
|
||||
|
||||
Optional properties:
|
||||
- interconnects: Must contain entry for the GR2D memory clients.
|
||||
- interconnect-names: Must include name of the interconnect path for each
|
||||
interconnect entry. Consult TRM documentation for information about
|
||||
available memory clients, see MEMORY CONTROLLER section.
|
||||
- operating-points-v2: See ../bindings/opp/opp.txt for details.
|
||||
- power-domains: Phandle to HEG or core power domain.
|
||||
|
||||
- gr3d: 3D graphics engine
|
||||
|
||||
@ -203,12 +226,16 @@ of the following host1x client modules:
|
||||
- reset-names: Must include the following entries:
|
||||
- 3d
|
||||
- 3d2 (Only required on SoCs with two 3D clocks)
|
||||
- mc
|
||||
- mc2 (Only required on SoCs with two 3D clocks)
|
||||
|
||||
Optional properties:
|
||||
- interconnects: Must contain entry for the GR3D memory clients.
|
||||
- interconnect-names: Must include name of the interconnect path for each
|
||||
interconnect entry. Consult TRM documentation for information about
|
||||
available memory clients, see MEMORY CONTROLLER section.
|
||||
- operating-points-v2: See ../bindings/opp/opp.txt for details.
|
||||
- power-domains: Phandles to 3D or core power domain.
|
||||
|
||||
- dc: display controller
|
||||
|
||||
@ -241,6 +268,8 @@ of the following host1x client modules:
|
||||
- interconnect-names: Must include name of the interconnect path for each
|
||||
interconnect entry. Consult TRM documentation for information about
|
||||
available memory clients, see MEMORY CONTROLLER section.
|
||||
- operating-points-v2: See ../bindings/opp/opp.txt for details.
|
||||
- power-domains: Phandle to core power domain.
|
||||
|
||||
- hdmi: High Definition Multimedia Interface
|
||||
|
||||
@ -267,6 +296,7 @@ of the following host1x client modules:
|
||||
- nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
|
||||
- nvidia,edid: supplies a binary EDID blob
|
||||
- nvidia,panel: phandle of a display panel
|
||||
- operating-points-v2: See ../bindings/opp/opp.txt for details.
|
||||
|
||||
- tvo: TV encoder output
|
||||
|
||||
@ -277,6 +307,10 @@ of the following host1x client modules:
|
||||
- clocks: Must contain one entry, for the module clock.
|
||||
See ../clocks/clock-bindings.txt for details.
|
||||
|
||||
Optional properties:
|
||||
- operating-points-v2: See ../bindings/opp/opp.txt for details.
|
||||
- power-domains: Phandle to core power domain.
|
||||
|
||||
- dsi: display serial interface
|
||||
|
||||
Required properties:
|
||||
@ -305,6 +339,7 @@ of the following host1x client modules:
|
||||
- nvidia,panel: phandle of a display panel
|
||||
- nvidia,ganged-mode: contains a phandle to a second DSI controller to gang
|
||||
up with in order to support up to 8 data lanes
|
||||
- operating-points-v2: See ../bindings/opp/opp.txt for details.
|
||||
|
||||
- sor: serial output resource
|
||||
|
||||
@ -408,6 +443,8 @@ Example:
|
||||
clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
|
||||
resets = <&tegra_car 28>;
|
||||
reset-names = "host1x";
|
||||
operating-points-v2 = <&dvfs_opp_table>;
|
||||
power-domains = <&domain>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
@ -421,6 +458,8 @@ Example:
|
||||
clocks = <&tegra_car TEGRA20_CLK_MPE>;
|
||||
resets = <&tegra_car 60>;
|
||||
reset-names = "mpe";
|
||||
operating-points-v2 = <&dvfs_opp_table>;
|
||||
power-domains = <&domain>;
|
||||
};
|
||||
|
||||
vi@54080000 {
|
||||
@ -429,6 +468,7 @@ Example:
|
||||
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
|
||||
assigned-clocks = <&tegra_car TEGRA210_CLK_VI>;
|
||||
assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
|
||||
operating-points-v2 = <&dvfs_opp_table>;
|
||||
|
||||
clocks = <&tegra_car TEGRA210_CLK_VI>;
|
||||
power-domains = <&pd_venc>;
|
||||
@ -510,6 +550,8 @@ Example:
|
||||
clocks = <&tegra_car TEGRA20_CLK_EPP>;
|
||||
resets = <&tegra_car 19>;
|
||||
reset-names = "epp";
|
||||
operating-points-v2 = <&dvfs_opp_table>;
|
||||
power-domains = <&domain>;
|
||||
};
|
||||
|
||||
isp {
|
||||
@ -528,6 +570,8 @@ Example:
|
||||
clocks = <&tegra_car TEGRA20_CLK_GR2D>;
|
||||
resets = <&tegra_car 21>;
|
||||
reset-names = "2d";
|
||||
operating-points-v2 = <&dvfs_opp_table>;
|
||||
power-domains = <&domain>;
|
||||
};
|
||||
|
||||
gr3d {
|
||||
@ -536,6 +580,8 @@ Example:
|
||||
clocks = <&tegra_car TEGRA20_CLK_GR3D>;
|
||||
resets = <&tegra_car 24>;
|
||||
reset-names = "3d";
|
||||
operating-points-v2 = <&dvfs_opp_table>;
|
||||
power-domains = <&domain>;
|
||||
};
|
||||
|
||||
dc@54200000 {
|
||||
@ -547,6 +593,8 @@ Example:
|
||||
clock-names = "dc", "parent";
|
||||
resets = <&tegra_car 27>;
|
||||
reset-names = "dc";
|
||||
operating-points-v2 = <&dvfs_opp_table>;
|
||||
power-domains = <&domain>;
|
||||
|
||||
interconnects = <&mc TEGRA20_MC_DISPLAY0A &emc>,
|
||||
<&mc TEGRA20_MC_DISPLAY0B &emc>,
|
||||
@ -571,6 +619,8 @@ Example:
|
||||
clock-names = "dc", "parent";
|
||||
resets = <&tegra_car 26>;
|
||||
reset-names = "dc";
|
||||
operating-points-v2 = <&dvfs_opp_table>;
|
||||
power-domains = <&domain>;
|
||||
|
||||
interconnects = <&mc TEGRA20_MC_DISPLAY0AB &emc>,
|
||||
<&mc TEGRA20_MC_DISPLAY0BB &emc>,
|
||||
@ -596,6 +646,7 @@ Example:
|
||||
resets = <&tegra_car 51>;
|
||||
reset-names = "hdmi";
|
||||
status = "disabled";
|
||||
operating-points-v2 = <&dvfs_opp_table>;
|
||||
};
|
||||
|
||||
tvo {
|
||||
@ -604,6 +655,7 @@ Example:
|
||||
interrupts = <0 76 0x04>;
|
||||
clocks = <&tegra_car TEGRA20_CLK_TVO>;
|
||||
status = "disabled";
|
||||
operating-points-v2 = <&dvfs_opp_table>;
|
||||
};
|
||||
|
||||
dsi {
|
||||
@ -615,6 +667,7 @@ Example:
|
||||
resets = <&tegra_car 48>;
|
||||
reset-names = "dsi";
|
||||
status = "disabled";
|
||||
operating-points-v2 = <&dvfs_opp_table>;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
83
sys/contrib/device-tree/Bindings/dma/arm,pl330.yaml
Normal file
83
sys/contrib/device-tree/Bindings/dma/arm,pl330.yaml
Normal file
@ -0,0 +1,83 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/dma/arm,pl330.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: ARM PrimeCell PL330 DMA Controller
|
||||
|
||||
maintainers:
|
||||
- Vinod Koul <vkoul@kernel.org>
|
||||
|
||||
description:
|
||||
The ARM PrimeCell PL330 DMA controller can move blocks of memory contents
|
||||
between memory and peripherals or memory to memory.
|
||||
|
||||
# We need a select here so we don't match all nodes with 'arm,primecell'
|
||||
select:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: arm,pl330
|
||||
required:
|
||||
- compatible
|
||||
|
||||
allOf:
|
||||
- $ref: dma-controller.yaml#
|
||||
- $ref: /schemas/arm/primecell.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- arm,pl330
|
||||
- const: arm,primecell
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
minItems: 1
|
||||
maxItems: 32
|
||||
description: A single combined interrupt or an interrupt per event
|
||||
|
||||
'#dma-cells':
|
||||
const: 1
|
||||
description: Contains the DMA request number for the consumer
|
||||
|
||||
arm,pl330-broken-no-flushp:
|
||||
type: boolean
|
||||
description: quirk for avoiding to execute DMAFLUSHP
|
||||
|
||||
arm,pl330-periph-burst:
|
||||
type: boolean
|
||||
description: quirk for performing burst transfer only
|
||||
|
||||
dma-coherent: true
|
||||
|
||||
resets:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
|
||||
reset-names:
|
||||
minItems: 1
|
||||
items:
|
||||
- const: dma
|
||||
- const: dma-ocp
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
dma-controller@12680000 {
|
||||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x12680000 0x1000>;
|
||||
interrupts = <99>;
|
||||
#dma-cells = <1>;
|
||||
};
|
||||
...
|
||||
@ -10,6 +10,7 @@ maintainers:
|
||||
- Vinod Koul <vkoul@kernel.org>
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/arm/primecell.yaml#
|
||||
- $ref: "dma-controller.yaml#"
|
||||
|
||||
# We need a select here so we don't match all nodes with 'arm,primecell'
|
||||
@ -89,6 +90,9 @@ properties:
|
||||
- 64
|
||||
description: bus width used for memcpy in bits. FTDMAC020 also accept 64 bits
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- reg
|
||||
- interrupts
|
||||
|
||||
@ -24,10 +24,10 @@ examples:
|
||||
dma: dma-controller@48000000 {
|
||||
compatible = "ti,omap-sdma";
|
||||
reg = <0x48000000 0x1000>;
|
||||
interrupts = <0 12 0x4
|
||||
0 13 0x4
|
||||
0 14 0x4
|
||||
0 15 0x4>;
|
||||
interrupts = <0 12 0x4>,
|
||||
<0 13 0x4>,
|
||||
<0 14 0x4>,
|
||||
<0 15 0x4>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <32>;
|
||||
dma-requests = <127>;
|
||||
|
||||
@ -14,15 +14,23 @@ allOf:
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- ingenic,jz4740-dma
|
||||
- ingenic,jz4725b-dma
|
||||
- ingenic,jz4760-dma
|
||||
- ingenic,jz4760b-dma
|
||||
- ingenic,jz4770-dma
|
||||
- ingenic,jz4780-dma
|
||||
- ingenic,x1000-dma
|
||||
- ingenic,x1830-dma
|
||||
oneOf:
|
||||
- enum:
|
||||
- ingenic,jz4740-dma
|
||||
- ingenic,jz4725b-dma
|
||||
- ingenic,jz4760-dma
|
||||
- ingenic,jz4760-bdma
|
||||
- ingenic,jz4760-mdma
|
||||
- ingenic,jz4760b-dma
|
||||
- ingenic,jz4760b-bdma
|
||||
- ingenic,jz4760b-mdma
|
||||
- ingenic,jz4770-dma
|
||||
- ingenic,jz4780-dma
|
||||
- ingenic,x1000-dma
|
||||
- ingenic,x1830-dma
|
||||
- items:
|
||||
- const: ingenic,jz4770-bdma
|
||||
- const: ingenic,jz4760b-bdma
|
||||
|
||||
reg:
|
||||
items:
|
||||
@ -36,13 +44,19 @@ properties:
|
||||
maxItems: 1
|
||||
|
||||
"#dma-cells":
|
||||
const: 2
|
||||
enum: [2, 3]
|
||||
description: >
|
||||
DMA clients must use the format described in dma.txt, giving a phandle
|
||||
to the DMA controller plus the following 2 integer cells:
|
||||
to the DMA controller plus the following integer cells:
|
||||
|
||||
- Request type: The DMA request type for transfers to/from the
|
||||
device on the allocated channel, as defined in the SoC documentation.
|
||||
- Request type: The DMA request type specifies the device endpoint that
|
||||
will be the source or destination of the DMA transfer.
|
||||
If "#dma-cells" is 2, the request type is a single cell, and the
|
||||
direction will be unidirectional (either RX or TX but not both).
|
||||
If "#dma-cells" is 3, the request type has two cells; the first
|
||||
one corresponds to the host to device direction (TX), the second one
|
||||
corresponds to the device to host direction (RX). The DMA channel is
|
||||
then bidirectional.
|
||||
|
||||
- Channel: If set to 0xffffffff, any available channel will be allocated
|
||||
for the client. Otherwise, the exact channel specified will be used.
|
||||
|
||||
@ -44,6 +44,10 @@ properties:
|
||||
- items:
|
||||
- const: renesas,dmac-r8a779a0 # R-Car V3U
|
||||
|
||||
- items:
|
||||
- const: renesas,dmac-r8a779f0 # R-Car S4-8
|
||||
- const: renesas,rcar-gen4-dmac
|
||||
|
||||
reg: true
|
||||
|
||||
interrupts:
|
||||
@ -118,6 +122,7 @@ if:
|
||||
contains:
|
||||
enum:
|
||||
- renesas,dmac-r8a779a0
|
||||
- renesas,rcar-gen4-dmac
|
||||
then:
|
||||
properties:
|
||||
reg:
|
||||
|
||||
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Reference in New Issue
Block a user