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Add in descriptions for TX descriptor fields ctl8-11 - these fields

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control the antenna control bits for the four TX series and the
TPC settings for TX series 1, 2, 3.

The specifics:

* The TPC setting for TX series 0 is handled in ctl0.

* TPC is currently disabled, so the per-packet TX power is
  set via the global per-rate TX power register, not per packet.

* The antenna control bits don't matter for AR5416 and later
  so they should stay 0 (which they currently do); they may
  be set for Kite but as there's no TX diversity supported
  at the moment (it requires the NIC to be built with an
  external antenna switch, matching how antenna diversity
  is done on legacy NICs), so again keep them 0.

This is in preparation for supporting per-rate TPC on the
AR5416 and later. The Kite (and soon to come Kiwi) code
sets ctl8-11 to 0x0, which doesn't have any effect at
the moment. When TPC is enabled it would result in the
second, third and fourth TX series attmpts to be done with
a TX power of 0. This commit doesn't change that; it'll
be followed up with some commits to properly set the TPC
registers appropriately.
This commit is contained in:
Adrian Chadd 2011-05-24 05:34:45 +00:00
parent 5c59afe04b
commit e808ca4454
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=222240
1 changed files with 23 additions and 0 deletions
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23
sys/dev/ath/ath_hal/ar5416/ar5416desc.h
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@ -205,6 +205,29 @@ struct ar5416_desc {
#define AR_STBC2 0x40000000
#define AR_STBC3 0x80000000
/* ds_ctl8 */
#define AR_AntCtl0 0x00ffffff
#define AR_AntCtl0_S 0
/* Xmit 0 TPC is AR_XmitPower in ctl0 */
/* ds_ctl9 */
#define AR_AntCtl1 0x00ffffff
#define AR_AntCtl1_S 0
#define AR_XmitPower1 0xff000000
#define AR_XmitPower1_S 24
/* ds_ctl10 */
#define AR_AntCtl2 0x00ffffff
#define AR_AntCtl2_S 0
#define AR_XmitPower2 0xff000000
#define AR_XmitPower2_S 24
/* ds_ctl11 */
#define AR_AntCtl3 0x00ffffff
#define AR_AntCtl3_S 0
#define AR_XmitPower3 0xff000000
#define AR_XmitPower3_S 24
/*************
* TX Status *
*************/