e808ca4454
control the antenna control bits for the four TX series and the TPC settings for TX series 1, 2, 3. The specifics: * The TPC setting for TX series 0 is handled in ctl0. * TPC is currently disabled, so the per-packet TX power is set via the global per-rate TX power register, not per packet. * The antenna control bits don't matter for AR5416 and later so they should stay 0 (which they currently do); they may be set for Kite but as there's no TX diversity supported at the moment (it requires the NIC to be built with an external antenna switch, matching how antenna diversity is done on legacy NICs), so again keep them 0. This is in preparation for supporting per-rate TPC on the AR5416 and later. The Kite (and soon to come Kiwi) code sets ctl8-11 to 0x0, which doesn't have any effect at the moment. When TPC is enabled it would result in the second, third and fourth TX series attmpts to be done with a TX power of 0. This commit doesn't change that; it'll be followed up with some commits to properly set the TPC registers appropriately.
421 lines
12 KiB
C
421 lines
12 KiB
C
/*
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* Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
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* Copyright (c) 2002-2008 Atheros Communications, Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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* $FreeBSD$
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*/
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#ifndef _ATH_AR5416_DESC_H_
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#define _ATH_AR5416_DESC_H
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/*
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* Hardware-specific descriptor structures.
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*/
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#include "ah_desc.h"
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/* XXX Need to replace this with a dynamic
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* method of determining Owl2 if possible
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*/
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#define _get_index(_ah) ( IS_5416V1(_ah) ? -4 : 0 )
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#define AR5416_DS_TXSTATUS(_ah, _ads) \
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((uint32_t*)(&(_ads)->u.tx.status[_get_index(_ah)]))
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#define AR5416_DS_TXSTATUS_CONST(_ah, _ads) \
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((const uint32_t*)(&(_ads)->u.tx.status[_get_index(_ah)]))
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#define AR5416_NUM_TX_STATUS 10 /* Number of TX status words */
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/* Clear the whole descriptor */
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#define AR5416_DESC_TX_CTL_SZ sizeof(struct ar5416_tx_desc)
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struct ar5416_tx_desc { /* tx desc has 12 control words + 10 status words */
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uint32_t ctl2;
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uint32_t ctl3;
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uint32_t ctl4;
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uint32_t ctl5;
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uint32_t ctl6;
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uint32_t ctl7;
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uint32_t ctl8;
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uint32_t ctl9;
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uint32_t ctl10;
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uint32_t ctl11;
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uint32_t status[AR5416_NUM_TX_STATUS];
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};
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struct ar5416_rx_desc { /* rx desc has 2 control words + 9 status words */
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uint32_t status0;
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uint32_t status1;
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uint32_t status2;
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uint32_t status3;
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uint32_t status4;
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uint32_t status5;
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uint32_t status6;
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uint32_t status7;
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uint32_t status8;
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};
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struct ar5416_desc {
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uint32_t ds_link; /* link pointer */
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uint32_t ds_data; /* data buffer pointer */
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uint32_t ds_ctl0; /* DMA control 0 */
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uint32_t ds_ctl1; /* DMA control 1 */
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union {
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struct ar5416_tx_desc tx;
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struct ar5416_rx_desc rx;
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} u;
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} __packed;
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#define AR5416DESC(_ds) ((struct ar5416_desc *)(_ds))
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#define AR5416DESC_CONST(_ds) ((const struct ar5416_desc *)(_ds))
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#define ds_ctl2 u.tx.ctl2
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#define ds_ctl3 u.tx.ctl3
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#define ds_ctl4 u.tx.ctl4
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#define ds_ctl5 u.tx.ctl5
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#define ds_ctl6 u.tx.ctl6
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#define ds_ctl7 u.tx.ctl7
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#define ds_ctl8 u.tx.ctl8
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#define ds_ctl9 u.tx.ctl9
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#define ds_ctl10 u.tx.ctl10
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#define ds_ctl11 u.tx.ctl11
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#define ds_rxstatus0 u.rx.status0
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#define ds_rxstatus1 u.rx.status1
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#define ds_rxstatus2 u.rx.status2
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#define ds_rxstatus3 u.rx.status3
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#define ds_rxstatus4 u.rx.status4
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#define ds_rxstatus5 u.rx.status5
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#define ds_rxstatus6 u.rx.status6
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#define ds_rxstatus7 u.rx.status7
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#define ds_rxstatus8 u.rx.status8
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/***********
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* TX Desc *
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***********/
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/* ds_ctl0 */
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#define AR_FrameLen 0x00000fff
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#define AR_VirtMoreFrag 0x00001000
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#define AR_TxCtlRsvd00 0x0000e000
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#define AR_XmitPower 0x003f0000
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#define AR_XmitPower_S 16
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#define AR_RTSEnable 0x00400000
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#define AR_VEOL 0x00800000
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#define AR_ClrDestMask 0x01000000
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#define AR_TxCtlRsvd01 0x1e000000
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#define AR_TxIntrReq 0x20000000
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#define AR_DestIdxValid 0x40000000
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#define AR_CTSEnable 0x80000000
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/* ds_ctl1 */
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#define AR_BufLen 0x00000fff
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#define AR_TxMore 0x00001000
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#define AR_DestIdx 0x000fe000
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#define AR_DestIdx_S 13
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#define AR_FrameType 0x00f00000
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#define AR_FrameType_S 20
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#define AR_NoAck 0x01000000
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#define AR_InsertTS 0x02000000
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#define AR_CorruptFCS 0x04000000
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#define AR_ExtOnly 0x08000000
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#define AR_ExtAndCtl 0x10000000
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#define AR_MoreAggr 0x20000000
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#define AR_IsAggr 0x40000000
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#define AR_MoreRifs 0x80000000
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/* ds_ctl2 */
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#define AR_BurstDur 0x00007fff
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#define AR_BurstDur_S 0
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#define AR_DurUpdateEn 0x00008000
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#define AR_XmitDataTries0 0x000f0000
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#define AR_XmitDataTries0_S 16
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#define AR_XmitDataTries1 0x00f00000
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#define AR_XmitDataTries1_S 20
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#define AR_XmitDataTries2 0x0f000000
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#define AR_XmitDataTries2_S 24
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#define AR_XmitDataTries3 0xf0000000
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#define AR_XmitDataTries3_S 28
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/* ds_ctl3 */
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#define AR_XmitRate0 0x000000ff
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#define AR_XmitRate0_S 0
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#define AR_XmitRate1 0x0000ff00
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#define AR_XmitRate1_S 8
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#define AR_XmitRate2 0x00ff0000
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#define AR_XmitRate2_S 16
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#define AR_XmitRate3 0xff000000
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#define AR_XmitRate3_S 24
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/* ds_ctl4 */
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#define AR_PacketDur0 0x00007fff
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#define AR_PacketDur0_S 0
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#define AR_RTSCTSQual0 0x00008000
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#define AR_PacketDur1 0x7fff0000
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#define AR_PacketDur1_S 16
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#define AR_RTSCTSQual1 0x80000000
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/* ds_ctl5 */
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#define AR_PacketDur2 0x00007fff
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#define AR_PacketDur2_S 0
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#define AR_RTSCTSQual2 0x00008000
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#define AR_PacketDur3 0x7fff0000
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#define AR_PacketDur3_S 16
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#define AR_RTSCTSQual3 0x80000000
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/* ds_ctl6 */
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#define AR_AggrLen 0x0000ffff
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#define AR_AggrLen_S 0
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#define AR_TxCtlRsvd60 0x00030000
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#define AR_PadDelim 0x03fc0000
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#define AR_PadDelim_S 18
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#define AR_EncrType 0x0c000000
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#define AR_EncrType_S 26
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#define AR_TxCtlRsvd61 0xf0000000
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/* ds_ctl7 */
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#define AR_2040_0 0x00000001
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#define AR_GI0 0x00000002
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#define AR_ChainSel0 0x0000001c
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#define AR_ChainSel0_S 2
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#define AR_2040_1 0x00000020
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#define AR_GI1 0x00000040
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#define AR_ChainSel1 0x00000380
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#define AR_ChainSel1_S 7
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#define AR_2040_2 0x00000400
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#define AR_GI2 0x00000800
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#define AR_ChainSel2 0x00007000
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#define AR_ChainSel2_S 12
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#define AR_2040_3 0x00008000
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#define AR_GI3 0x00010000
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#define AR_ChainSel3 0x000e0000
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#define AR_ChainSel3_S 17
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#define AR_RTSCTSRate 0x0ff00000
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#define AR_RTSCTSRate_S 20
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#define AR_STBC0 0x10000000
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#define AR_STBC1 0x20000000
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#define AR_STBC2 0x40000000
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#define AR_STBC3 0x80000000
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/* ds_ctl8 */
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#define AR_AntCtl0 0x00ffffff
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#define AR_AntCtl0_S 0
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/* Xmit 0 TPC is AR_XmitPower in ctl0 */
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/* ds_ctl9 */
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#define AR_AntCtl1 0x00ffffff
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#define AR_AntCtl1_S 0
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#define AR_XmitPower1 0xff000000
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#define AR_XmitPower1_S 24
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/* ds_ctl10 */
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#define AR_AntCtl2 0x00ffffff
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#define AR_AntCtl2_S 0
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#define AR_XmitPower2 0xff000000
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#define AR_XmitPower2_S 24
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/* ds_ctl11 */
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#define AR_AntCtl3 0x00ffffff
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#define AR_AntCtl3_S 0
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#define AR_XmitPower3 0xff000000
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#define AR_XmitPower3_S 24
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/*************
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* TX Status *
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*************/
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/* ds_status0 */
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#define AR_TxRSSIAnt00 0x000000ff
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#define AR_TxRSSIAnt00_S 0
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#define AR_TxRSSIAnt01 0x0000ff00
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#define AR_TxRSSIAnt01_S 8
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#define AR_TxRSSIAnt02 0x00ff0000
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#define AR_TxRSSIAnt02_S 16
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#define AR_TxStatusRsvd00 0x3f000000
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#define AR_TxBaStatus 0x40000000
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#define AR_TxStatusRsvd01 0x80000000
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/* ds_status1 */
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#define AR_FrmXmitOK 0x00000001
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#define AR_ExcessiveRetries 0x00000002
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#define AR_FIFOUnderrun 0x00000004
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#define AR_Filtered 0x00000008
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#define AR_RTSFailCnt 0x000000f0
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#define AR_RTSFailCnt_S 4
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#define AR_DataFailCnt 0x00000f00
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#define AR_DataFailCnt_S 8
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#define AR_VirtRetryCnt 0x0000f000
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#define AR_VirtRetryCnt_S 12
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#define AR_TxDelimUnderrun 0x00010000
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#define AR_TxDelimUnderrun_S 13
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#define AR_TxDataUnderrun 0x00020000
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#define AR_TxDataUnderrun_S 14
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#define AR_DescCfgErr 0x00040000
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#define AR_DescCfgErr_S 15
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#define AR_TxTimerExpired 0x00080000
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#define AR_TxStatusRsvd10 0xfff00000
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/* ds_status2 */
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#define AR_SendTimestamp(_ptr) (_ptr)[2]
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/* ds_status3 */
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#define AR_BaBitmapLow(_ptr) (_ptr)[3]
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/* ds_status4 */
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#define AR_BaBitmapHigh(_ptr) (_ptr)[4]
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/* ds_status5 */
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#define AR_TxRSSIAnt10 0x000000ff
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#define AR_TxRSSIAnt10_S 0
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#define AR_TxRSSIAnt11 0x0000ff00
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#define AR_TxRSSIAnt11_S 8
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#define AR_TxRSSIAnt12 0x00ff0000
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#define AR_TxRSSIAnt12_S 16
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#define AR_TxRSSICombined 0xff000000
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#define AR_TxRSSICombined_S 24
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/* ds_status6 */
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#define AR_TxEVM0(_ptr) (_ptr)[6]
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/* ds_status7 */
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#define AR_TxEVM1(_ptr) (_ptr)[7]
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/* ds_status8 */
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#define AR_TxEVM2(_ptr) (_ptr)[8]
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/* ds_status9 */
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#define AR_TxDone 0x00000001
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#define AR_SeqNum 0x00001ffe
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#define AR_SeqNum_S 1
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#define AR_TxStatusRsvd80 0x0001e000
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#define AR_TxOpExceeded 0x00020000
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#define AR_TxStatusRsvd81 0x001c0000
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#define AR_FinalTxIdx 0x00600000
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#define AR_FinalTxIdx_S 21
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#define AR_TxStatusRsvd82 0x01800000
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#define AR_PowerMgmt 0x02000000
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#define AR_TxStatusRsvd83 0xfc000000
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/***********
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* RX Desc *
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***********/
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/* ds_ctl0 */
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#define AR_RxCTLRsvd00 0xffffffff
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/* ds_ctl1 */
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#define AR_BufLen 0x00000fff
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#define AR_RxCtlRsvd00 0x00001000
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#define AR_RxIntrReq 0x00002000
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#define AR_RxCtlRsvd01 0xffffc000
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/*************
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* Rx Status *
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*************/
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/* ds_status0 */
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#define AR_RxRSSIAnt00 0x000000ff
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#define AR_RxRSSIAnt00_S 0
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#define AR_RxRSSIAnt01 0x0000ff00
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#define AR_RxRSSIAnt01_S 8
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#define AR_RxRSSIAnt02 0x00ff0000
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#define AR_RxRSSIAnt02_S 16
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/* Rev specific */
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/* Owl 1.x only */
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#define AR_RxStatusRsvd00 0xff000000
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/* Owl 2.x only */
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#define AR_RxRate 0xff000000
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#define AR_RxRate_S 24
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/* ds_status1 */
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#define AR_DataLen 0x00000fff
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#define AR_RxMore 0x00001000
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#define AR_NumDelim 0x003fc000
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#define AR_NumDelim_S 14
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#define AR_RxStatusRsvd10 0xff800000
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/* ds_status2 */
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#define AR_RcvTimestamp ds_rxstatus2
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/* ds_status3 */
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#define AR_GI 0x00000001
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#define AR_2040 0x00000002
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/* Rev specific */
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/* Owl 1.x only */
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#define AR_RxRateV1 0x000003fc
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#define AR_RxRateV1_S 2
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#define AR_Parallel40 0x00000400
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#define AR_RxStatusRsvd30 0xfffff800
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/* Owl 2.x only */
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#define AR_DupFrame 0x00000004
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#define AR_RxAntenna 0xffffff00
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#define AR_RxAntenna_S 8
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/* ds_status4 */
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#define AR_RxRSSIAnt10 0x000000ff
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#define AR_RxRSSIAnt10_S 0
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#define AR_RxRSSIAnt11 0x0000ff00
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#define AR_RxRSSIAnt11_S 8
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#define AR_RxRSSIAnt12 0x00ff0000
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#define AR_RxRSSIAnt12_S 16
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#define AR_RxRSSICombined 0xff000000
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#define AR_RxRSSICombined_S 24
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/* ds_status5 */
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#define AR_RxEVM0 ds_rxstatus5
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/* ds_status6 */
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#define AR_RxEVM1 ds_rxstatus6
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/* ds_status7 */
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#define AR_RxEVM2 ds_rxstatus7
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/* ds_status8 */
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#define AR_RxDone 0x00000001
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#define AR_RxFrameOK 0x00000002
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#define AR_CRCErr 0x00000004
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#define AR_DecryptCRCErr 0x00000008
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#define AR_PHYErr 0x00000010
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#define AR_MichaelErr 0x00000020
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#define AR_PreDelimCRCErr 0x00000040
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#define AR_RxStatusRsvd70 0x00000080
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#define AR_RxKeyIdxValid 0x00000100
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#define AR_KeyIdx 0x0000fe00
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#define AR_KeyIdx_S 9
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#define AR_PHYErrCode 0x0000ff00
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#define AR_PHYErrCode_S 8
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#define AR_RxMoreAggr 0x00010000
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#define AR_RxAggr 0x00020000
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#define AR_PostDelimCRCErr 0x00040000
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#define AR_RxStatusRsvd71 0x2ff80000
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#define AR_HiRxChain 0x10000000
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#define AR_DecryptBusyErr 0x40000000
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#define AR_KeyMiss 0x80000000
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#define TXCTL_OFFSET(ah) 2
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#define TXCTL_NUMWORDS(ah) (AR_SREV_5416_V20_OR_LATER(ah) ? 12 : 8)
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#define TXSTATUS_OFFSET(ah) (AR_SREV_5416_V20_OR_LATER(ah) ? 14 : 10)
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#define TXSTATUS_NUMWORDS(ah) 10
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#define RXCTL_OFFSET(ah) 3
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#define RXCTL_NUMWORDS(ah) 1
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#define RXSTATUS_OFFSET(ah) 4
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#define RXSTATUS_NUMWORDS(ah) 9
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#define RXSTATUS_RATE(ah, ads) \
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(AR_SREV_5416_V20_OR_LATER(ah) ? \
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MS((ads)->ds_rxstatus0, AR_RxRate) : \
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((ads)->ds_rxstatus3 >> 2) & 0xFF)
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#define RXSTATUS_DUPLICATE(ah, ads) \
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(AR_SREV_5416_V20_OR_LATER(ah) ? \
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MS((ads)->ds_rxstatus3, AR_Parallel40) : \
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((ads)->ds_rxstatus3 >> 10) & 0x1)
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#endif /* _ATH_AR5416_DESC_H_ */
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