Stop calling cpu_dcache_wb_range from PTE_SYNC.

We set the shareability attributes in TCR_EL1 on boot. These tell the
hardware the pagetables are in cached memory so there is no need to flush
the entries from the cache to memory.

This has about 4.2% improvement in system time and 2.7% improvement in
user time for a buildkernel -j48 on a ThunderX.

Keep the old code for now to allow for further comparisons.

sys/arm64/arm64/pmap.c

@@ -504,7 +504,11 @@ pmap_l3_valid(pt_entry_t l3)
 
 CTASSERT(L1_BLOCK == L2_BLOCK);
 
+#if 0
 #define	PTE_SYNC(pte)	cpu_dcache_wb_range((vm_offset_t)pte, sizeof(*pte))
+#else
+#define	PTE_SYNC(pte)	(void)0
+#endif
 
 /*
  * Checks if the page is dirty. We currently lack proper tracking of this on