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The Intel Pentium Pro's performance counters are 40 bits wide. The Intel

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manuals specifically say that reading the counters using the rdmsr
instruction returns a 64 bit value of which the higher 24 bits are
undefined. The code that reads the counters should then clear the
high 24 bits.

PR:		 i386/10632
This commit is contained in:
Alan Cox 1999-05-11 01:54:52 +00:00
parent 476702b3c4
commit eb27b1567e
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=46945
1 changed files with 3 additions and 3 deletions
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6
sys/i386/i386/perfmon.c
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@ -26,7 +26,7 @@
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $Id: perfmon.c,v 1.16 1998/12/07 21:58:18 archie Exp $
* $Id: perfmon.c,v 1.17 1999/01/12 00:19:32 eivind Exp $
*/
#include <sys/param.h>
@ -160,7 +160,7 @@ perfmon_stop(int pmc)
if (perfmon_inuse & (1 << pmc)) {
disable_intr();
pmc_shadow[pmc] = rdmsr(msr_pmc[pmc]);
pmc_shadow[pmc] = rdmsr(msr_pmc[pmc]) & 0xffffffffffULL;
ctl_shadow[pmc] &= ~(PMCF_EN << 16);
writectl(pmc);
enable_intr();
@ -177,7 +177,7 @@ perfmon_read(int pmc, quad_t *val)
if (perfmon_inuse & (1 << pmc)) {
if (ctl_shadow[pmc] & (PMCF_EN << 16))
*val = rdmsr(msr_pmc[pmc]);
*val = rdmsr(msr_pmc[pmc]) & 0xffffffffffULL;
else
*val = pmc_shadow[pmc];
return 0;