Mark all inline asms that read the floating-point control or status
registers as volatile. Instructions that *wrote* to FP state were already marked volatile, but apparently gcc has license to move non-volatile asms past volatile asms. This broke amd64's feupdateenv at -O2 due to a WAR conflict between fnstsw and fldenv there.
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Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=140219
@ -56,7 +56,7 @@ typedef __uint16_t fexcept_t;
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#define _FPUSW_SHIFT 51
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#define __excb() __asm __volatile("excb")
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#define __mf_fpcr(__cw) __asm ("mf_fpcr %0" : "=f" (*(__cw)))
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#define __mf_fpcr(__cw) __asm __volatile("mf_fpcr %0" : "=f" (*(__cw)))
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#define __mt_fpcr(__cw) __asm __volatile("mt_fpcr %0" : : "f" (__cw))
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union __fpcr {
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@ -79,9 +79,9 @@ extern const fenv_t __fe_dfl_env;
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#define __fldcw(__cw) __asm __volatile("fldcw %0" : : "m" (__cw))
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#define __fldenv(__env) __asm __volatile("fldenv %0" : : "m" (__env))
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#define __fnclex() __asm __volatile("fnclex")
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#define __fnstenv(__env) __asm("fnstenv %0" : "=m" (*(__env)))
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#define __fnstcw(__cw) __asm("fnstcw %0" : "=m" (*(__cw)))
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#define __fnstsw(__sw) __asm("fnstsw %0" : "=am" (*(__sw)))
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#define __fnstenv(__env) __asm __volatile("fnstenv %0" : "=m" (*(__env)))
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#define __fnstcw(__cw) __asm __volatile("fnstcw %0" : "=m" (*(__cw)))
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#define __fnstsw(__sw) __asm __volatile("fnstsw %0" : "=am" (*(__sw)))
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#define __fwait() __asm __volatile("fwait")
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#define __ldmxcsr(__csr) __asm __volatile("ldmxcsr %0" : : "m" (__csr))
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#define __stmxcsr(__csr) __asm __volatile("stmxcsr %0" : "=m" (*(__csr)))
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@ -54,7 +54,7 @@ extern const fenv_t __fe_dfl_env;
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#define _ENABLE_MASK (FE_ALL_EXCEPT << _FPUSW_SHIFT)
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#ifdef ARM_HARD_FLOAT
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#define __rfs(__fpsr) __asm("rfs %0" : "=r" (*(__fpsr)))
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#define __rfs(__fpsr) __asm __volatile("rfs %0" : "=r" (*(__fpsr)))
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#define __wfs(__fpsr) __asm __volatile("wfs %0" : : "r" (__fpsr))
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#else
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#define __rfs(__fpsr)
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@ -68,9 +68,9 @@ extern const fenv_t __fe_dfl_env;
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#define __fldcw(__cw) __asm __volatile("fldcw %0" : : "m" (__cw))
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#define __fldenv(__env) __asm __volatile("fldenv %0" : : "m" (__env))
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#define __fnclex() __asm __volatile("fnclex")
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#define __fnstenv(__env) __asm("fnstenv %0" : "=m" (*(__env)))
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#define __fnstcw(__cw) __asm("fnstcw %0" : "=m" (*(__cw)))
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#define __fnstsw(__sw) __asm("fnstsw %0" : "=am" (*(__sw)))
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#define __fnstenv(__env) __asm __volatile("fnstenv %0" : "=m" (*(__env)))
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#define __fnstcw(__cw) __asm __volatile("fnstcw %0" : "=m" (*(__cw)))
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#define __fnstsw(__sw) __asm __volatile("fnstsw %0" : "=am" (*(__sw)))
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#define __fwait() __asm __volatile("fwait")
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static __inline int
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@ -60,7 +60,7 @@ extern const fenv_t __fe_dfl_env;
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#define _FPUSW_SHIFT 13
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#define __stfpsr(__r) __asm("mov %0=ar.fpsr" : "=r" (*(__r)))
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#define __stfpsr(__r) __asm __volatile("mov %0=ar.fpsr" : "=r" (*(__r)))
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#define __ldfpsr(__r) __asm __volatile("mov ar.fpsr=%0" : : "r" (__r))
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static __inline int
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@ -82,7 +82,7 @@ extern const fenv_t __fe_dfl_env;
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#define _ENABLE_MASK ((FE_DIVBYZERO | FE_INEXACT | FE_INVALID | \
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FE_OVERFLOW | FE_UNDERFLOW) >> _FPUSW_SHIFT)
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#define __mffs(__env) __asm("mffs %0" : "=f" (*(__env)))
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#define __mffs(__env) __asm __volatile("mffs %0" : "=f" (*(__env)))
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#define __mtfsf(__env) __asm __volatile("mtfsf 255,%0" : : "f" (__env))
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union __fpscr {
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@ -68,7 +68,7 @@ extern const fenv_t __fe_dfl_env;
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#define _ENABLE_MASK (FE_ALL_EXCEPT << _FPUSW_SHIFT)
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#define __ldxfsr(__r) __asm __volatile("ldx %0, %%fsr" : : "m" (__r))
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#define __stxfsr(__r) __asm("stx %%fsr, %0" : "=m" (*(__r)))
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#define __stxfsr(__r) __asm __volatile("stx %%fsr, %0" : "=m" (*(__r)))
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static __inline int
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feclearexcept(int __excepts)
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