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Mark all inline asms that read the floating-point control or status

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registers as volatile.  Instructions that *wrote* to FP state were
already marked volatile, but apparently gcc has license to move
non-volatile asms past volatile asms.  This broke amd64's feupdateenv
at -O2 due to a WAR conflict between fnstsw and fldenv there.
This commit is contained in:
David Schultz 2005-01-14 07:09:23 +00:00
parent f66b047888
commit f365db00e5
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=140219
7 changed files with 11 additions and 11 deletions
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2
lib/msun/alpha/fenv.h
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@ -56,7 +56,7 @@ typedef __uint16_t fexcept_t;
#define _FPUSW_SHIFT 51
#define __excb() __asm __volatile("excb")
#define __mf_fpcr(__cw) __asm ("mf_fpcr %0" : "=f" (*(__cw)))
#define __mf_fpcr(__cw) __asm __volatile("mf_fpcr %0" : "=f" (*(__cw)))
#define __mt_fpcr(__cw) __asm __volatile("mt_fpcr %0" : : "f" (__cw))
union __fpcr {

6
lib/msun/amd64/fenv.h
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@ -79,9 +79,9 @@ extern const fenv_t __fe_dfl_env;
#define __fldcw(__cw) __asm __volatile("fldcw %0" : : "m" (__cw))
#define __fldenv(__env) __asm __volatile("fldenv %0" : : "m" (__env))
#define __fnclex() __asm __volatile("fnclex")
#define __fnstenv(__env) __asm("fnstenv %0" : "=m" (*(__env)))
#define __fnstcw(__cw) __asm("fnstcw %0" : "=m" (*(__cw)))
#define __fnstsw(__sw) __asm("fnstsw %0" : "=am" (*(__sw)))
#define __fnstenv(__env) __asm __volatile("fnstenv %0" : "=m" (*(__env)))
#define __fnstcw(__cw) __asm __volatile("fnstcw %0" : "=m" (*(__cw)))
#define __fnstsw(__sw) __asm __volatile("fnstsw %0" : "=am" (*(__sw)))
#define __fwait() __asm __volatile("fwait")
#define __ldmxcsr(__csr) __asm __volatile("ldmxcsr %0" : : "m" (__csr))
#define __stmxcsr(__csr) __asm __volatile("stmxcsr %0" : "=m" (*(__csr)))

2
lib/msun/arm/fenv.h
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@ -54,7 +54,7 @@ extern const fenv_t __fe_dfl_env;
#define _ENABLE_MASK (FE_ALL_EXCEPT << _FPUSW_SHIFT)
#ifdef ARM_HARD_FLOAT
#define __rfs(__fpsr) __asm("rfs %0" : "=r" (*(__fpsr)))
#define __rfs(__fpsr) __asm __volatile("rfs %0" : "=r" (*(__fpsr)))
#define __wfs(__fpsr) __asm __volatile("wfs %0" : : "r" (__fpsr))
#else
#define __rfs(__fpsr)

6
lib/msun/i387/fenv.h
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@ -68,9 +68,9 @@ extern const fenv_t __fe_dfl_env;
#define __fldcw(__cw) __asm __volatile("fldcw %0" : : "m" (__cw))
#define __fldenv(__env) __asm __volatile("fldenv %0" : : "m" (__env))
#define __fnclex() __asm __volatile("fnclex")
#define __fnstenv(__env) __asm("fnstenv %0" : "=m" (*(__env)))
#define __fnstcw(__cw) __asm("fnstcw %0" : "=m" (*(__cw)))
#define __fnstsw(__sw) __asm("fnstsw %0" : "=am" (*(__sw)))
#define __fnstenv(__env) __asm __volatile("fnstenv %0" : "=m" (*(__env)))
#define __fnstcw(__cw) __asm __volatile("fnstcw %0" : "=m" (*(__cw)))
#define __fnstsw(__sw) __asm __volatile("fnstsw %0" : "=am" (*(__sw)))
#define __fwait() __asm __volatile("fwait")
static __inline int

2
lib/msun/ia64/fenv.h
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@ -60,7 +60,7 @@ extern const fenv_t __fe_dfl_env;
#define _FPUSW_SHIFT 13
#define __stfpsr(__r) __asm("mov %0=ar.fpsr" : "=r" (*(__r)))
#define __stfpsr(__r) __asm __volatile("mov %0=ar.fpsr" : "=r" (*(__r)))
#define __ldfpsr(__r) __asm __volatile("mov ar.fpsr=%0" : : "r" (__r))
static __inline int

2
lib/msun/powerpc/fenv.h
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@ -82,7 +82,7 @@ extern const fenv_t __fe_dfl_env;
#define _ENABLE_MASK ((FE_DIVBYZERO | FE_INEXACT | FE_INVALID | \
FE_OVERFLOW | FE_UNDERFLOW) >> _FPUSW_SHIFT)
#define __mffs(__env) __asm("mffs %0" : "=f" (*(__env)))
#define __mffs(__env) __asm __volatile("mffs %0" : "=f" (*(__env)))
#define __mtfsf(__env) __asm __volatile("mtfsf 255,%0" : : "f" (__env))
union __fpscr {

2
lib/msun/sparc64/fenv.h
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@ -68,7 +68,7 @@ extern const fenv_t __fe_dfl_env;
#define _ENABLE_MASK (FE_ALL_EXCEPT << _FPUSW_SHIFT)
#define __ldxfsr(__r) __asm __volatile("ldx %0, %%fsr" : : "m" (__r))
#define __stxfsr(__r) __asm("stx %%fsr, %0" : "=m" (*(__r)))
#define __stxfsr(__r) __asm __volatile("stx %%fsr, %0" : "=m" (*(__r)))
static __inline int
feclearexcept(int __excepts)