Update to Linux 4.10
This commit is contained in:
parent
c7716441be
commit
ff018dbf5b
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/vendor/device-tree/dist/; revision=314847 svn path=/vendor/device-tree/4.10/; revision=314848; tag=vendor/device-tree/4.10
@ -61,7 +61,9 @@ Required Properties:
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- #address-cells: must be 1
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- #size-cells: must be 1
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- interrupts : Should be single bit error interrupt, then double bit error
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interrupt. Note the rising edge type.
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interrupt.
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- interrupt-controller : boolean indicator that ECC Manager is an interrupt controller
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- #interrupt-cells : must be set to 2.
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- ranges : standard definition, should translate from local addresses
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Subcomponents:
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@ -70,11 +72,64 @@ L2 Cache ECC
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Required Properties:
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- compatible : Should be "altr,socfpga-a10-l2-ecc"
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- reg : Address and size for ECC error interrupt clear registers.
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- interrupts : Should be single bit error interrupt, then double bit error
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interrupt, in this order.
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On-Chip RAM ECC
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Required Properties:
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- compatible : Should be "altr,socfpga-a10-ocram-ecc"
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- reg : Address and size for ECC block registers.
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- interrupts : Should be single bit error interrupt, then double bit error
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interrupt, in this order.
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Ethernet FIFO ECC
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Required Properties:
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- compatible : Should be "altr,socfpga-eth-mac-ecc"
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- reg : Address and size for ECC block registers.
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- altr,ecc-parent : phandle to parent Ethernet node.
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- interrupts : Should be single bit error interrupt, then double bit error
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interrupt, in this order.
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NAND FIFO ECC
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Required Properties:
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- compatible : Should be "altr,socfpga-nand-ecc"
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- reg : Address and size for ECC block registers.
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- altr,ecc-parent : phandle to parent NAND node.
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- interrupts : Should be single bit error interrupt, then double bit error
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interrupt, in this order.
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DMA FIFO ECC
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Required Properties:
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- compatible : Should be "altr,socfpga-dma-ecc"
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- reg : Address and size for ECC block registers.
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- altr,ecc-parent : phandle to parent DMA node.
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- interrupts : Should be single bit error interrupt, then double bit error
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interrupt, in this order.
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USB FIFO ECC
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Required Properties:
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- compatible : Should be "altr,socfpga-usb-ecc"
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- reg : Address and size for ECC block registers.
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- altr,ecc-parent : phandle to parent USB node.
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- interrupts : Should be single bit error interrupt, then double bit error
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interrupt, in this order.
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QSPI FIFO ECC
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Required Properties:
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- compatible : Should be "altr,socfpga-qspi-ecc"
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- reg : Address and size for ECC block registers.
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- altr,ecc-parent : phandle to parent QSPI node.
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- interrupts : Should be single bit error interrupt, then double bit error
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interrupt, in this order.
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SDMMC FIFO ECC
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Required Properties:
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- compatible : Should be "altr,socfpga-sdmmc-ecc"
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- reg : Address and size for ECC block registers.
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- altr,ecc-parent : phandle to parent SD/MMC node.
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- interrupts : Should be single bit error interrupt, then double bit error
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interrupt, in this order for port A, and then single bit error interrupt,
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then double bit error interrupt in this order for port B.
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Example:
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@ -85,15 +140,94 @@ Example:
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#size-cells = <1>;
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interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <2>;
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ranges;
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l2-ecc@ffd06010 {
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compatible = "altr,socfpga-a10-l2-ecc";
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reg = <0xffd06010 0x4>;
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interrupts = <0 IRQ_TYPE_LEVEL_HIGH>,
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<32 IRQ_TYPE_LEVEL_HIGH>;
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};
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ocram-ecc@ff8c3000 {
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compatible = "altr,socfpga-a10-ocram-ecc";
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reg = <0xff8c3000 0x90>;
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interrupts = <1 IRQ_TYPE_LEVEL_HIGH>,
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<33 IRQ_TYPE_LEVEL_HIGH> ;
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};
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emac0-rx-ecc@ff8c0800 {
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compatible = "altr,socfpga-eth-mac-ecc";
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reg = <0xff8c0800 0x400>;
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altr,ecc-parent = <&gmac0>;
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interrupts = <4 IRQ_TYPE_LEVEL_HIGH>,
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<36 IRQ_TYPE_LEVEL_HIGH>;
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};
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emac0-tx-ecc@ff8c0c00 {
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compatible = "altr,socfpga-eth-mac-ecc";
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reg = <0xff8c0c00 0x400>;
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altr,ecc-parent = <&gmac0>;
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interrupts = <5 IRQ_TYPE_LEVEL_HIGH>,
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<37 IRQ_TYPE_LEVEL_HIGH>;
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};
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nand-buf-ecc@ff8c2000 {
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compatible = "altr,socfpga-nand-ecc";
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reg = <0xff8c2000 0x400>;
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altr,ecc-parent = <&nand>;
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interrupts = <11 IRQ_TYPE_LEVEL_HIGH>,
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<43 IRQ_TYPE_LEVEL_HIGH>;
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};
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nand-rd-ecc@ff8c2400 {
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compatible = "altr,socfpga-nand-ecc";
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reg = <0xff8c2400 0x400>;
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altr,ecc-parent = <&nand>;
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interrupts = <13 IRQ_TYPE_LEVEL_HIGH>,
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<45 IRQ_TYPE_LEVEL_HIGH>;
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};
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nand-wr-ecc@ff8c2800 {
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compatible = "altr,socfpga-nand-ecc";
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reg = <0xff8c2800 0x400>;
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altr,ecc-parent = <&nand>;
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interrupts = <12 IRQ_TYPE_LEVEL_HIGH>,
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<44 IRQ_TYPE_LEVEL_HIGH>;
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};
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dma-ecc@ff8c8000 {
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compatible = "altr,socfpga-dma-ecc";
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reg = <0xff8c8000 0x400>;
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altr,ecc-parent = <&pdma>;
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interrupts = <10 IRQ_TYPE_LEVEL_HIGH>,
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<42 IRQ_TYPE_LEVEL_HIGH>;
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usb0-ecc@ff8c8800 {
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compatible = "altr,socfpga-usb-ecc";
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reg = <0xff8c8800 0x400>;
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altr,ecc-parent = <&usb0>;
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interrupts = <2 IRQ_TYPE_LEVEL_HIGH>,
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<34 IRQ_TYPE_LEVEL_HIGH>;
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};
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qspi-ecc@ff8c8400 {
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compatible = "altr,socfpga-qspi-ecc";
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reg = <0xff8c8400 0x400>;
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altr,ecc-parent = <&qspi>;
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interrupts = <14 IRQ_TYPE_LEVEL_HIGH>,
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<46 IRQ_TYPE_LEVEL_HIGH>;
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};
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sdmmc-ecc@ff8c2c00 {
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compatible = "altr,socfpga-sdmmc-ecc";
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reg = <0xff8c2c00 0x400>;
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altr,ecc-parent = <&mmc>;
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interrupts = <15 IRQ_TYPE_LEVEL_HIGH>,
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<47 IRQ_TYPE_LEVEL_HIGH>,
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<16 IRQ_TYPE_LEVEL_HIGH>,
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<48 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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20
Bindings/arm/amlogic,scpi.txt
Normal file
20
Bindings/arm/amlogic,scpi.txt
Normal file
@ -0,0 +1,20 @@
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System Control and Power Interface (SCPI) Message Protocol
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(in addition to the standard binding in [0])
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----------------------------------------------------------
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Required properties
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- compatible : should be "amlogic,meson-gxbb-scpi"
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AMLOGIC SRAM and Shared Memory for SCPI
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------------------------------------
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Required properties:
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- compatible : should be "amlogic,meson-gxbb-sram"
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Each sub-node represents the reserved area for SCPI.
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Required sub-node properties:
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- compatible : should be "amlogic,meson-gxbb-scp-shmem" for SRAM based shared
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memory on Amlogic GXBB SoC.
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[0] Documentation/devicetree/bindings/arm/arm,scpi.txt
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@ -17,6 +17,18 @@ Boards with the Amlogic Meson GXBaby SoC shall have the following properties:
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Required root node property:
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compatible: "amlogic,meson-gxbb";
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Boards with the Amlogic Meson GXL S905X SoC shall have the following properties:
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Required root node property:
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compatible: "amlogic,s905x", "amlogic,meson-gxl";
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Boards with the Amlogic Meson GXL S905D SoC shall have the following properties:
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Required root node property:
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compatible: "amlogic,s905d", "amlogic,meson-gxl";
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Boards with the Amlogic Meson GXM S912 SoC shall have the following properties:
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Required root node property:
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compatible: "amlogic,s912", "amlogic,meson-gxm";
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Board compatible values:
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- "geniatech,atv1200" (Meson6)
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- "minix,neo-x8" (Meson8)
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@ -28,3 +40,10 @@ Board compatible values:
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- "hardkernel,odroid-c2" (Meson gxbb)
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- "amlogic,p200" (Meson gxbb)
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- "amlogic,p201" (Meson gxbb)
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- "amlogic,p212" (Meson gxl s905x)
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- "amlogic,p230" (Meson gxl s905d)
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- "amlogic,p231" (Meson gxl s905d)
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- "amlogic,q200" (Meson gxm s912)
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- "amlogic,q201" (Meson gxm s912)
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- "nexbox,a95x" (Meson gxbb or Meson gxl s905x)
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- "nexbox,a1" (Meson gxm s912)
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@ -25,6 +25,12 @@ to deliver its interrupts via SPIs.
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- always-on : a boolean property. If present, the timer is powered through an
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always-on power domain, therefore it never loses context.
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- fsl,erratum-a008585 : A boolean property. Indicates the presence of
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QorIQ erratum A-008585, which says that reading the counter is
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unreliable unless the same value is returned by back-to-back reads.
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This also affects writes to the tval register, due to the implicit
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counter read.
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** Optional properties:
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- arm,cpu-registers-not-fw-configured : Firmware does not initialize
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@ -32,6 +38,11 @@ to deliver its interrupts via SPIs.
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architecturally-defined reset values. Only supported for 32-bit
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systems which follow the ARMv7 architected reset values.
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- arm,no-tick-in-suspend : The main counter does not tick when the system is in
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low-power system suspend on some SoCs. This behavior does not match the
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Architecture Reference Manual's specification that the system counter "must
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be implemented in an always-on power domain."
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Example:
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@ -7,7 +7,10 @@ by Linux to initiate various system control and power operations.
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Required properties:
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- compatible : should be "arm,scpi"
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- compatible : should be
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* "arm,scpi" : For implementations complying to SCPI v1.0 or above
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* "arm,scpi-pre-1.0" : For implementations complying to all
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unversioned releases prior to SCPI v1.0
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- mboxes: List of phandle and mailbox channel specifiers
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All the channels reserved by remote SCP firmware for use by
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SCPI message protocol should be specified in any order
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@ -59,18 +62,14 @@ SRAM and Shared Memory for SCPI
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A small area of SRAM is reserved for SCPI communication between application
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processors and SCP.
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Required properties:
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- compatible : should be "arm,juno-sram-ns" for Non-secure SRAM on Juno
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The rest of the properties should follow the generic mmio-sram description
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found in ../../sram/sram.txt
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The properties should follow the generic mmio-sram description found in [3]
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Each sub-node represents the reserved area for SCPI.
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Required sub-node properties:
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- reg : The base offset and size of the reserved area with the SRAM
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- compatible : should be "arm,juno-scp-shmem" for Non-secure SRAM based
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shared memory on Juno platforms
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- compatible : should be "arm,scp-shmem" for Non-secure SRAM based
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shared memory
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Sensor bindings for the sensors based on SCPI Message Protocol
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--------------------------------------------------------------
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@ -81,16 +80,37 @@ Required properties:
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- #thermal-sensor-cells: should be set to 1. This property follows the
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thermal device tree bindings[2].
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Valid cell values are raw identifiers (Sensor
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ID) as used by the firmware. Refer to
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platform documentation for your
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implementation for the IDs to use. For Juno
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R0 and Juno R1 refer to [3].
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Valid cell values are raw identifiers (Sensor ID)
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as used by the firmware. Refer to platform details
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for your implementation for the IDs to use.
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Power domain bindings for the power domains based on SCPI Message Protocol
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------------------------------------------------------------
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This binding uses the generic power domain binding[4].
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PM domain providers
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===================
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Required properties:
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- #power-domain-cells : Should be 1. Contains the device or the power
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domain ID value used by SCPI commands.
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- num-domains: Total number of power domains provided by SCPI. This is
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needed as the SCPI message protocol lacks a mechanism to
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query this information at runtime.
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PM domain consumers
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===================
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Required properties:
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- power-domains : A phandle and PM domain specifier as defined by bindings of
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the power controller specified by phandle.
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[0] http://infocenter.arm.com/help/topic/com.arm.doc.dui0922b/index.html
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[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
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[2] Documentation/devicetree/bindings/thermal/thermal.txt
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[3] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0922b/apas03s22.html
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[3] Documentation/devicetree/bindings/sram/sram.txt
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[4] Documentation/devicetree/bindings/power/power_domain.txt
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Example:
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@ -144,6 +164,12 @@ scpi_protocol: scpi@2e000000 {
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compatible = "arm,scpi-sensors";
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#thermal-sensor-cells = <1>;
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};
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scpi_devpd: scpi-power-domains {
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compatible = "arm,scpi-power-domains";
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num-domains = <2>;
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#power-domain-cells = <1>;
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};
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};
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cpu@0 {
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@ -156,6 +182,7 @@ hdlcd@7ff60000 {
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...
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reg = <0 0x7ff60000 0 0x1000>;
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clocks = <&scpi_clk 4>;
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power-domains = <&scpi_devpd 1>;
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};
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thermal-zones {
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@ -186,3 +213,7 @@ The thermal-sensors property in the soc_thermal node uses the
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temperature sensor provided by SCP firmware to setup a thermal
|
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zone. The ID "3" is the sensor identifier for the temperature sensor
|
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as used by the firmware.
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The num-domains property in scpi-power-domains domain specifies that
|
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SCPI provides 2 power domains. The hdlcd node uses the power domain with
|
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domain ID 1.
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|
@ -148,11 +148,12 @@ Example:
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/dts-v1/;
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#include <dt-bindings/interrupt-controller/irq.h>
|
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#include "skeleton.dtsi"
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|
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/ {
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model = "ARM RealView PB1176 with device tree";
|
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compatible = "arm,realview-pb1176";
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#address-cells = <1>;
|
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#size-cells = <1>;
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soc {
|
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#address-cells = <1>;
|
||||
|
@ -225,3 +225,19 @@ required properties:
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compatible = "atmel,sama5d3-sfr", "syscon";
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reg = <0xf0038000 0x60>;
|
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};
|
||||
|
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Security Module (SECUMOD)
|
||||
|
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The Security Module macrocell provides all necessary secure functions to avoid
|
||||
voltage, temperature, frequency and mechanical attacks on the chip. It also
|
||||
embeds secure memories that can be scrambled
|
||||
|
||||
required properties:
|
||||
- compatible: Should be "atmel,<chip>-secumod", "syscon".
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<chip> can be "sama5d2".
|
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- reg: Should contain registers location and length
|
||||
|
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secumod@fc040000 {
|
||||
compatible = "atmel,sama5d2-secumod", "syscon";
|
||||
reg = <0xfc040000 0x100>;
|
||||
};
|
||||
|
@ -5,7 +5,7 @@ CPUs in the following Broadcom SoCs:
|
||||
BCM11130, BCM11140, BCM11351, BCM28145, BCM28155, BCM21664
|
||||
|
||||
The enable method is specified by defining the following required
|
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properties in the "cpus" device tree node:
|
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properties in the "cpu" device tree node:
|
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- enable-method = "brcm,bcm11351-cpu-method";
|
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- secondary-boot-reg = <...>;
|
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|
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@ -19,8 +19,6 @@ Example:
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cpus {
|
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#address-cells = <1>;
|
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#size-cells = <0>;
|
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enable-method = "brcm,bcm11351-cpu-method";
|
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secondary-boot-reg = <0x3500417c>;
|
||||
|
||||
cpu0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
@ -32,5 +30,7 @@ Example:
|
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device_type = "cpu";
|
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compatible = "arm,cortex-a9";
|
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reg = <1>;
|
||||
enable-method = "brcm,bcm11351-cpu-method";
|
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secondary-boot-reg = <0x3500417c>;
|
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};
|
||||
};
|
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|
36
Bindings/arm/bcm/brcm,bcm23550-cpu-method.txt
Normal file
36
Bindings/arm/bcm/brcm,bcm23550-cpu-method.txt
Normal file
@ -0,0 +1,36 @@
|
||||
Broadcom Kona Family CPU Enable Method
|
||||
--------------------------------------
|
||||
This binding defines the enable method used for starting secondary
|
||||
CPUs in the following Broadcom SoCs:
|
||||
BCM23550
|
||||
|
||||
The enable method is specified by defining the following required
|
||||
properties in the "cpu" device tree node:
|
||||
- enable-method = "brcm,bcm23550";
|
||||
- secondary-boot-reg = <...>;
|
||||
|
||||
The secondary-boot-reg property is a u32 value that specifies the
|
||||
physical address of the register used to request the ROM holding pen
|
||||
code release a secondary CPU. The value written to the register is
|
||||
formed by encoding the target CPU id into the low bits of the
|
||||
physical start address it should jump to.
|
||||
|
||||
Example:
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
cpu1: cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
reg = <1>;
|
||||
enable-method = "brcm,bcm23550";
|
||||
secondary-boot-reg = <0x3500417c>;
|
||||
};
|
||||
};
|
15
Bindings/arm/bcm/brcm,bcm23550.txt
Normal file
15
Bindings/arm/bcm/brcm,bcm23550.txt
Normal file
@ -0,0 +1,15 @@
|
||||
Broadcom BCM23550 device tree bindings
|
||||
--------------------------------------
|
||||
|
||||
This document describes the device tree bindings for boards with the BCM23550
|
||||
SoC.
|
||||
|
||||
Required root node property:
|
||||
- compatible: brcm,bcm23550
|
||||
|
||||
Example:
|
||||
/ {
|
||||
model = "BCM23550 SoC";
|
||||
compatible = "brcm,bcm23550";
|
||||
[...]
|
||||
}
|
@ -30,10 +30,18 @@ Raspberry Pi 2 Model B
|
||||
Required root node properties:
|
||||
compatible = "raspberrypi,2-model-b", "brcm,bcm2836";
|
||||
|
||||
Raspberry Pi 3 Model B
|
||||
Required root node properties:
|
||||
compatible = "raspberrypi,3-model-b", "brcm,bcm2837";
|
||||
|
||||
Raspberry Pi Compute Module
|
||||
Required root node properties:
|
||||
compatible = "raspberrypi,compute-module", "brcm,bcm2835";
|
||||
|
||||
Raspberry Pi Zero
|
||||
Required root node properties:
|
||||
compatible = "raspberrypi,model-zero", "brcm,bcm2835";
|
||||
|
||||
Generic BCM2835 board
|
||||
Required root node properties:
|
||||
compatible = "brcm,bcm2835";
|
||||
|
9
Bindings/arm/bcm/brcm,ns2.txt
Normal file
9
Bindings/arm/bcm/brcm,ns2.txt
Normal file
@ -0,0 +1,9 @@
|
||||
Broadcom North Star 2 (NS2) device tree bindings
|
||||
------------------------------------------------
|
||||
|
||||
Boards with NS2 shall have the following properties:
|
||||
|
||||
Required root node property:
|
||||
|
||||
NS2 SVK board
|
||||
compatible = "brcm,ns2-svk", "brcm,ns2";
|
@ -12,14 +12,33 @@ its hardware characteristcs.
|
||||
|
||||
* compatible: These have to be supplemented with "arm,primecell" as
|
||||
drivers are using the AMBA bus interface. Possible values include:
|
||||
- "arm,coresight-etb10", "arm,primecell";
|
||||
- "arm,coresight-tpiu", "arm,primecell";
|
||||
- "arm,coresight-tmc", "arm,primecell";
|
||||
- "arm,coresight-funnel", "arm,primecell";
|
||||
- "arm,coresight-etm3x", "arm,primecell";
|
||||
- "arm,coresight-etm4x", "arm,primecell";
|
||||
- "qcom,coresight-replicator1x", "arm,primecell";
|
||||
- "arm,coresight-stm", "arm,primecell"; [1]
|
||||
- Embedded Trace Buffer (version 1.0):
|
||||
"arm,coresight-etb10", "arm,primecell";
|
||||
|
||||
- Trace Port Interface Unit:
|
||||
"arm,coresight-tpiu", "arm,primecell";
|
||||
|
||||
- Trace Memory Controller, used for Embedded Trace Buffer(ETB),
|
||||
Embedded Trace FIFO(ETF) and Embedded Trace Router(ETR)
|
||||
configuration. The configuration mode (ETB, ETF, ETR) is
|
||||
discovered at boot time when the device is probed.
|
||||
"arm,coresight-tmc", "arm,primecell";
|
||||
|
||||
- Trace Funnel:
|
||||
"arm,coresight-funnel", "arm,primecell";
|
||||
|
||||
- Embedded Trace Macrocell (version 3.x) and
|
||||
Program Flow Trace Macrocell:
|
||||
"arm,coresight-etm3x", "arm,primecell";
|
||||
|
||||
- Embedded Trace Macrocell (version 4.x):
|
||||
"arm,coresight-etm4x", "arm,primecell";
|
||||
|
||||
- Qualcomm Configurable Replicator (version 1.x):
|
||||
"qcom,coresight-replicator1x", "arm,primecell";
|
||||
|
||||
- System Trace Macrocell:
|
||||
"arm,coresight-stm", "arm,primecell"; [1]
|
||||
|
||||
* reg: physical base address and length of the register
|
||||
set(s) of the component.
|
||||
|
236
Bindings/arm/cpu-capacity.txt
Normal file
236
Bindings/arm/cpu-capacity.txt
Normal file
@ -0,0 +1,236 @@
|
||||
==========================================
|
||||
ARM CPUs capacity bindings
|
||||
==========================================
|
||||
|
||||
==========================================
|
||||
1 - Introduction
|
||||
==========================================
|
||||
|
||||
ARM systems may be configured to have cpus with different power/performance
|
||||
characteristics within the same chip. In this case, additional information has
|
||||
to be made available to the kernel for it to be aware of such differences and
|
||||
take decisions accordingly.
|
||||
|
||||
==========================================
|
||||
2 - CPU capacity definition
|
||||
==========================================
|
||||
|
||||
CPU capacity is a number that provides the scheduler information about CPUs
|
||||
heterogeneity. Such heterogeneity can come from micro-architectural differences
|
||||
(e.g., ARM big.LITTLE systems) or maximum frequency at which CPUs can run
|
||||
(e.g., SMP systems with multiple frequency domains). Heterogeneity in this
|
||||
context is about differing performance characteristics; this binding tries to
|
||||
capture a first-order approximation of the relative performance of CPUs.
|
||||
|
||||
CPU capacities are obtained by running a suitable benchmark. This binding makes
|
||||
no guarantees on the validity or suitability of any particular benchmark, the
|
||||
final capacity should, however, be:
|
||||
|
||||
* A "single-threaded" or CPU affine benchmark
|
||||
* Divided by the running frequency of the CPU executing the benchmark
|
||||
* Not subject to dynamic frequency scaling of the CPU
|
||||
|
||||
For the time being we however advise usage of the Dhrystone benchmark. What
|
||||
above thus becomes:
|
||||
|
||||
CPU capacities are obtained by running the Dhrystone benchmark on each CPU at
|
||||
max frequency (with caches enabled). The obtained DMIPS score is then divided
|
||||
by the frequency (in MHz) at which the benchmark has been run, so that
|
||||
DMIPS/MHz are obtained. Such values are then normalized w.r.t. the highest
|
||||
score obtained in the system.
|
||||
|
||||
==========================================
|
||||
3 - capacity-dmips-mhz
|
||||
==========================================
|
||||
|
||||
capacity-dmips-mhz is an optional cpu node [1] property: u32 value
|
||||
representing CPU capacity expressed in normalized DMIPS/MHz. At boot time, the
|
||||
maximum frequency available to the cpu is then used to calculate the capacity
|
||||
value internally used by the kernel.
|
||||
|
||||
capacity-dmips-mhz property is all-or-nothing: if it is specified for a cpu
|
||||
node, it has to be specified for every other cpu nodes, or the system will
|
||||
fall back to the default capacity value for every CPU. If cpufreq is not
|
||||
available, final capacities are calculated by directly using capacity-dmips-
|
||||
mhz values (normalized w.r.t. the highest value found while parsing the DT).
|
||||
|
||||
===========================================
|
||||
4 - Examples
|
||||
===========================================
|
||||
|
||||
Example 1 (ARM 64-bit, 6-cpu system, two clusters):
|
||||
capacities-dmips-mhz are scaled w.r.t. 1024 (cpu@0 and cpu@1)
|
||||
supposing cluster0@max-freq=1100 and custer1@max-freq=850,
|
||||
final capacities are 1024 for cluster0 and 446 for cluster1
|
||||
|
||||
cpus {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu-map {
|
||||
cluster0 {
|
||||
core0 {
|
||||
cpu = <&A57_0>;
|
||||
};
|
||||
core1 {
|
||||
cpu = <&A57_1>;
|
||||
};
|
||||
};
|
||||
|
||||
cluster1 {
|
||||
core0 {
|
||||
cpu = <&A53_0>;
|
||||
};
|
||||
core1 {
|
||||
cpu = <&A53_1>;
|
||||
};
|
||||
core2 {
|
||||
cpu = <&A53_2>;
|
||||
};
|
||||
core3 {
|
||||
cpu = <&A53_3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
idle-states {
|
||||
entry-method = "arm,psci";
|
||||
|
||||
CPU_SLEEP_0: cpu-sleep-0 {
|
||||
compatible = "arm,idle-state";
|
||||
arm,psci-suspend-param = <0x0010000>;
|
||||
local-timer-stop;
|
||||
entry-latency-us = <100>;
|
||||
exit-latency-us = <250>;
|
||||
min-residency-us = <150>;
|
||||
};
|
||||
|
||||
CLUSTER_SLEEP_0: cluster-sleep-0 {
|
||||
compatible = "arm,idle-state";
|
||||
arm,psci-suspend-param = <0x1010000>;
|
||||
local-timer-stop;
|
||||
entry-latency-us = <800>;
|
||||
exit-latency-us = <700>;
|
||||
min-residency-us = <2500>;
|
||||
};
|
||||
};
|
||||
|
||||
A57_0: cpu@0 {
|
||||
compatible = "arm,cortex-a57","arm,armv8";
|
||||
reg = <0x0 0x0>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&A57_L2>;
|
||||
clocks = <&scpi_dvfs 0>;
|
||||
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
|
||||
capacity-dmips-mhz = <1024>;
|
||||
};
|
||||
|
||||
A57_1: cpu@1 {
|
||||
compatible = "arm,cortex-a57","arm,armv8";
|
||||
reg = <0x0 0x1>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&A57_L2>;
|
||||
clocks = <&scpi_dvfs 0>;
|
||||
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
|
||||
capacity-dmips-mhz = <1024>;
|
||||
};
|
||||
|
||||
A53_0: cpu@100 {
|
||||
compatible = "arm,cortex-a53","arm,armv8";
|
||||
reg = <0x0 0x100>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&A53_L2>;
|
||||
clocks = <&scpi_dvfs 1>;
|
||||
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
|
||||
capacity-dmips-mhz = <578>;
|
||||
};
|
||||
|
||||
A53_1: cpu@101 {
|
||||
compatible = "arm,cortex-a53","arm,armv8";
|
||||
reg = <0x0 0x101>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&A53_L2>;
|
||||
clocks = <&scpi_dvfs 1>;
|
||||
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
|
||||
capacity-dmips-mhz = <578>;
|
||||
};
|
||||
|
||||
A53_2: cpu@102 {
|
||||
compatible = "arm,cortex-a53","arm,armv8";
|
||||
reg = <0x0 0x102>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&A53_L2>;
|
||||
clocks = <&scpi_dvfs 1>;
|
||||
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
|
||||
capacity-dmips-mhz = <578>;
|
||||
};
|
||||
|
||||
A53_3: cpu@103 {
|
||||
compatible = "arm,cortex-a53","arm,armv8";
|
||||
reg = <0x0 0x103>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&A53_L2>;
|
||||
clocks = <&scpi_dvfs 1>;
|
||||
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
|
||||
capacity-dmips-mhz = <578>;
|
||||
};
|
||||
|
||||
A57_L2: l2-cache0 {
|
||||
compatible = "cache";
|
||||
};
|
||||
|
||||
A53_L2: l2-cache1 {
|
||||
compatible = "cache";
|
||||
};
|
||||
};
|
||||
|
||||
Example 2 (ARM 32-bit, 4-cpu system, two clusters,
|
||||
cpus 0,1@1GHz, cpus 2,3@500MHz):
|
||||
capacities-dmips-mhz are scaled w.r.t. 2 (cpu@0 and cpu@1), this means that first
|
||||
cpu@0 and cpu@1 are twice fast than cpu@2 and cpu@3 (at the same frequency)
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <0>;
|
||||
capacity-dmips-mhz = <2>;
|
||||
};
|
||||
|
||||
cpu1: cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <1>;
|
||||
capacity-dmips-mhz = <2>;
|
||||
};
|
||||
|
||||
cpu2: cpu@2 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <0x100>;
|
||||
capacity-dmips-mhz = <1>;
|
||||
};
|
||||
|
||||
cpu3: cpu@3 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <0x101>;
|
||||
capacity-dmips-mhz = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
===========================================
|
||||
5 - References
|
||||
===========================================
|
||||
|
||||
[1] ARM Linux Kernel documentation - CPUs bindings
|
||||
Documentation/devicetree/bindings/arm/cpus.txt
|
@ -178,6 +178,7 @@ nodes to be present and contain the properties described below.
|
||||
"marvell,pj4b"
|
||||
"marvell,sheeva-v5"
|
||||
"nvidia,tegra132-denver"
|
||||
"nvidia,tegra186-denver"
|
||||
"qcom,krait"
|
||||
"qcom,kryo"
|
||||
"qcom,scorpion"
|
||||
@ -193,6 +194,8 @@ nodes to be present and contain the properties described below.
|
||||
"allwinner,sun6i-a31"
|
||||
"allwinner,sun8i-a23"
|
||||
"arm,realview-smp"
|
||||
"brcm,bcm11351-cpu-method"
|
||||
"brcm,bcm23550"
|
||||
"brcm,bcm-nsp-smp"
|
||||
"brcm,brahma-b15"
|
||||
"marvell,armada-375-smp"
|
||||
@ -204,6 +207,7 @@ nodes to be present and contain the properties described below.
|
||||
"qcom,gcc-msm8660"
|
||||
"qcom,kpss-acc-v1"
|
||||
"qcom,kpss-acc-v2"
|
||||
"renesas,apmu"
|
||||
"rockchip,rk3036-smp"
|
||||
"rockchip,rk3066-smp"
|
||||
"ste,dbx500-smp"
|
||||
@ -238,6 +242,14 @@ nodes to be present and contain the properties described below.
|
||||
# List of phandles to idle state nodes supported
|
||||
by this cpu [3].
|
||||
|
||||
- capacity-dmips-mhz
|
||||
Usage: Optional
|
||||
Value type: <u32>
|
||||
Definition:
|
||||
# u32 value representing CPU capacity [3] in
|
||||
DMIPS/MHz, relative to highest capacity-dmips-mhz
|
||||
in the system.
|
||||
|
||||
- rockchip,pmu
|
||||
Usage: optional for systems that have an "enable-method"
|
||||
property value of "rockchip,rk3066-smp"
|
||||
@ -461,3 +473,5 @@ cpus {
|
||||
[2] arm/msm/qcom,kpss-acc.txt
|
||||
[3] ARM Linux kernel documentation - idle states bindings
|
||||
Documentation/devicetree/bindings/arm/idle-states.txt
|
||||
[3] ARM Linux kernel documentation - cpu capacity bindings
|
||||
Documentation/devicetree/bindings/arm/cpu-capacity.txt
|
||||
|
@ -5,6 +5,10 @@ DA850/OMAP-L138/AM18x Evaluation Module (EVM) board
|
||||
Required root node properties:
|
||||
- compatible = "ti,da850-evm", "ti,da850";
|
||||
|
||||
DA850/OMAP-L138/AM18x L138/C6748 Development Kit (LCDK) board
|
||||
Required root node properties:
|
||||
- compatible = "ti,da850-lcdk", "ti,da850";
|
||||
|
||||
EnBW AM1808 based CMC board
|
||||
Required root node properties:
|
||||
- compatible = "enbw,cmc", "ti,da850;
|
||||
|
@ -97,7 +97,7 @@ Freescale LS1021A Platform Device Tree Bindings
|
||||
Required root node compatible properties:
|
||||
- compatible = "fsl,ls1021a";
|
||||
|
||||
Freescale LS1021A SoC-specific Device Tree Bindings
|
||||
Freescale SoC-specific Device Tree Bindings
|
||||
-------------------------------------------
|
||||
|
||||
Freescale SCFG
|
||||
@ -105,7 +105,11 @@ Freescale SCFG
|
||||
configuration and status registers for the chip. Such as getting PEX port
|
||||
status.
|
||||
Required properties:
|
||||
- compatible: should be "fsl,ls1021a-scfg"
|
||||
- compatible: Should contain a chip-specific compatible string,
|
||||
Chip-specific strings are of the form "fsl,<chip>-scfg",
|
||||
The following <chip>s are known to be supported:
|
||||
ls1021a, ls1043a, ls1046a, ls2080a.
|
||||
|
||||
- reg: should contain base address and length of SCFG memory-mapped registers
|
||||
|
||||
Example:
|
||||
@ -119,7 +123,11 @@ Freescale DCFG
|
||||
configuration and status for the device. Such as setting the secondary
|
||||
core start address and release the secondary core from holdoff and startup.
|
||||
Required properties:
|
||||
- compatible: should be "fsl,ls1021a-dcfg"
|
||||
- compatible: Should contain a chip-specific compatible string,
|
||||
Chip-specific strings are of the form "fsl,<chip>-dcfg",
|
||||
The following <chip>s are known to be supported:
|
||||
ls1021a, ls1043a, ls1046a, ls2080a.
|
||||
|
||||
- reg : should contain base address and length of DCFG memory-mapped registers
|
||||
|
||||
Example:
|
||||
@ -131,6 +139,10 @@ Example:
|
||||
Freescale ARMv8 based Layerscape SoC family Device Tree Bindings
|
||||
----------------------------------------------------------------
|
||||
|
||||
LS1043A SoC
|
||||
Required root node properties:
|
||||
- compatible = "fsl,ls1043a";
|
||||
|
||||
LS1043A ARMv8 based RDB Board
|
||||
Required root node properties:
|
||||
- compatible = "fsl,ls1043a-rdb", "fsl,ls1043a";
|
||||
@ -139,6 +151,22 @@ LS1043A ARMv8 based QDS Board
|
||||
Required root node properties:
|
||||
- compatible = "fsl,ls1043a-qds", "fsl,ls1043a";
|
||||
|
||||
LS1046A SoC
|
||||
Required root node properties:
|
||||
- compatible = "fsl,ls1046a";
|
||||
|
||||
LS1046A ARMv8 based QDS Board
|
||||
Required root node properties:
|
||||
- compatible = "fsl,ls1046a-qds", "fsl,ls1046a";
|
||||
|
||||
LS1046A ARMv8 based RDB Board
|
||||
Required root node properties:
|
||||
- compatible = "fsl,ls1046a-rdb", "fsl,ls1046a";
|
||||
|
||||
LS2080A SoC
|
||||
Required root node properties:
|
||||
- compatible = "fsl,ls2080a";
|
||||
|
||||
LS2080A ARMv8 based Simulator model
|
||||
Required root node properties:
|
||||
- compatible = "fsl,ls2080a-simu", "fsl,ls2080a";
|
||||
|
14
Bindings/arm/hisilicon/hi3519-sysctrl.txt
Normal file
14
Bindings/arm/hisilicon/hi3519-sysctrl.txt
Normal file
@ -0,0 +1,14 @@
|
||||
* Hisilicon Hi3519 System Controller Block
|
||||
|
||||
This bindings use the following binding:
|
||||
Documentation/devicetree/bindings/mfd/syscon.txt
|
||||
|
||||
Required properties:
|
||||
- compatible: "hisilicon,hi3519-sysctrl".
|
||||
- reg: the register region of this block
|
||||
|
||||
Examples:
|
||||
sysctrl: system-controller@12010000 {
|
||||
compatible = "hisilicon,hi3519-sysctrl", "syscon";
|
||||
reg = <0x12010000 0x1000>;
|
||||
};
|
@ -28,6 +28,10 @@ HiP06 D03 Board
|
||||
Required root node properties:
|
||||
- compatible = "hisilicon,hip06-d03";
|
||||
|
||||
HiP07 D05 Board
|
||||
Required root node properties:
|
||||
- compatible = "hisilicon,hip07-d05";
|
||||
|
||||
Hisilicon system controller
|
||||
|
||||
Required properties:
|
||||
@ -175,38 +179,55 @@ Example:
|
||||
};
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
Hisilicon HiP05 PCIe-SAS system controller
|
||||
Hisilicon HiP05/HiP06 PCIe-SAS sub system controller
|
||||
|
||||
Required properties:
|
||||
- compatible : "hisilicon,pcie-sas-subctrl", "syscon";
|
||||
- reg : Register address and size
|
||||
|
||||
The HiP05 PCIe-SAS system controller is shared by PCIe and SAS controllers in
|
||||
HiP05 Soc to implement some basic configurations.
|
||||
The PCIe-SAS sub system controller is shared by PCIe and SAS controllers in
|
||||
HiP05 or HiP06 Soc to implement some basic configurations.
|
||||
|
||||
Example:
|
||||
/* for HiP05 PCIe-SAS system */
|
||||
pcie_sas: system_controller@0xb0000000 {
|
||||
/* for HiP05 PCIe-SAS sub system */
|
||||
pcie_sas: system_controller@b0000000 {
|
||||
compatible = "hisilicon,pcie-sas-subctrl", "syscon";
|
||||
reg = <0xb0000000 0x10000>;
|
||||
};
|
||||
|
||||
Hisilicon HiP05 PERISUB system controller
|
||||
Hisilicon HiP05/HiP06 PERI sub system controller
|
||||
|
||||
Required properties:
|
||||
- compatible : "hisilicon,hip05-perisubc", "syscon";
|
||||
- compatible : "hisilicon,peri-subctrl", "syscon";
|
||||
- reg : Register address and size
|
||||
|
||||
The HiP05 PERISUB system controller is shared by peripheral controllers in
|
||||
HiP05 Soc to implement some basic configurations. The peripheral
|
||||
The PERI sub system controller is shared by peripheral controllers in
|
||||
HiP05 or HiP06 Soc to implement some basic configurations. The peripheral
|
||||
controllers include mdio, ddr, iic, uart, timer and so on.
|
||||
|
||||
Example:
|
||||
/* for HiP05 perisub-ctrl-c system */
|
||||
/* for HiP05 sub peri system */
|
||||
peri_c_subctrl: syscon@80000000 {
|
||||
compatible = "hisilicon,hip05-perisubc", "syscon";
|
||||
compatible = "hisilicon,peri-subctrl", "syscon";
|
||||
reg = <0x0 0x80000000 0x0 0x10000>;
|
||||
};
|
||||
|
||||
Hisilicon HiP05/HiP06 DSA sub system controller
|
||||
|
||||
Required properties:
|
||||
- compatible : "hisilicon,dsa-subctrl", "syscon";
|
||||
- reg : Register address and size
|
||||
|
||||
The DSA sub system controller is shared by peripheral controllers in
|
||||
HiP05 or HiP06 Soc to implement some basic configurations.
|
||||
|
||||
Example:
|
||||
/* for HiP05 dsa sub system */
|
||||
pcie_sas: system_controller@a0000000 {
|
||||
compatible = "hisilicon,dsa-subctrl", "syscon";
|
||||
reg = <0xa0000000 0x10000>;
|
||||
};
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
Hisilicon CPU controller
|
||||
|
||||
|
26
Bindings/arm/juno,scpi.txt
Normal file
26
Bindings/arm/juno,scpi.txt
Normal file
@ -0,0 +1,26 @@
|
||||
System Control and Power Interface (SCPI) Message Protocol
|
||||
(in addition to the standard binding in [0])
|
||||
|
||||
Juno SRAM and Shared Memory for SCPI
|
||||
------------------------------------
|
||||
|
||||
Required properties:
|
||||
- compatible : should be "arm,juno-sram-ns" for Non-secure SRAM
|
||||
|
||||
Each sub-node represents the reserved area for SCPI.
|
||||
|
||||
Required sub-node properties:
|
||||
- reg : The base offset and size of the reserved area with the SRAM
|
||||
- compatible : should be "arm,juno-scp-shmem" for Non-secure SRAM based
|
||||
shared memory on Juno platforms
|
||||
|
||||
Sensor bindings for the sensors based on SCPI Message Protocol
|
||||
--------------------------------------------------------------
|
||||
Required properties:
|
||||
- compatible : should be "arm,scpi-sensors".
|
||||
- #thermal-sensor-cells: should be set to 1.
|
||||
For Juno R0 and Juno R1 refer to [1] for the
|
||||
sensor identifiers
|
||||
|
||||
[0] Documentation/devicetree/bindings/arm/arm,scpi.txt
|
||||
[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0922b/apas03s22.html
|
81
Bindings/arm/keystone/ti,sci.txt
Normal file
81
Bindings/arm/keystone/ti,sci.txt
Normal file
@ -0,0 +1,81 @@
|
||||
Texas Instruments System Control Interface (TI-SCI) Message Protocol
|
||||
--------------------------------------------------------------------
|
||||
|
||||
Texas Instrument's processors including those belonging to Keystone generation
|
||||
of processors have separate hardware entity which is now responsible for the
|
||||
management of the System on Chip (SoC) system. These include various system
|
||||
level functions as well.
|
||||
|
||||
An example of such an SoC is K2G, which contains the system control hardware
|
||||
block called Power Management Micro Controller (PMMC). This hardware block is
|
||||
initialized early into boot process and provides services to Operating Systems
|
||||
on multiple processors including ones running Linux.
|
||||
|
||||
See http://processors.wiki.ti.com/index.php/TISCI for protocol definition.
|
||||
|
||||
TI-SCI controller Device Node:
|
||||
=============================
|
||||
|
||||
The TI-SCI node describes the Texas Instrument's System Controller entity node.
|
||||
This parent node may optionally have additional children nodes which describe
|
||||
specific functionality such as clocks, power domain, reset or additional
|
||||
functionality as may be required for the SoC. This hierarchy also describes the
|
||||
relationship between the TI-SCI parent node to the child node.
|
||||
|
||||
Required properties:
|
||||
-------------------
|
||||
- compatible: should be "ti,k2g-sci"
|
||||
- mbox-names:
|
||||
"rx" - Mailbox corresponding to receive path
|
||||
"tx" - Mailbox corresponding to transmit path
|
||||
|
||||
- mboxes: Mailboxes corresponding to the mbox-names. Each value of the mboxes
|
||||
property should contain a phandle to the mailbox controller device
|
||||
node and an args specifier that will be the phandle to the intended
|
||||
sub-mailbox child node to be used for communication.
|
||||
|
||||
See Documentation/devicetree/bindings/mailbox/mailbox.txt for more details
|
||||
about the generic mailbox controller and client driver bindings. Also see
|
||||
Documentation/devicetree/bindings/mailbox/ti,message-manager.txt for typical
|
||||
controller that is used to communicate with this System controllers.
|
||||
|
||||
Optional Properties:
|
||||
-------------------
|
||||
- reg-names:
|
||||
debug_messages - Map the Debug message region
|
||||
- reg: register space corresponding to the debug_messages
|
||||
- ti,system-reboot-controller: If system reboot can be triggered by SoC reboot
|
||||
|
||||
Example (K2G):
|
||||
-------------
|
||||
pmmc: pmmc {
|
||||
compatible = "ti,k2g-sci";
|
||||
mbox-names = "rx", "tx";
|
||||
mboxes= <&msgmgr &msgmgr_proxy_pmmc_rx>,
|
||||
<&msgmgr &msgmgr_proxy_pmmc_tx>;
|
||||
reg-names = "debug_messages";
|
||||
reg = <0x02921800 0x800>;
|
||||
};
|
||||
|
||||
|
||||
TI-SCI Client Device Node:
|
||||
=========================
|
||||
|
||||
Client nodes are maintained as children of the relevant TI-SCI device node.
|
||||
|
||||
Example (K2G):
|
||||
-------------
|
||||
pmmc: pmmc {
|
||||
compatible = "ti,k2g-sci";
|
||||
...
|
||||
|
||||
my_clk_node: clk_node {
|
||||
...
|
||||
...
|
||||
};
|
||||
|
||||
my_pd_node: pd_node {
|
||||
...
|
||||
...
|
||||
};
|
||||
};
|
@ -86,10 +86,10 @@ Optional properties:
|
||||
firmware)
|
||||
- arm,dynamic-clock-gating : L2 dynamic clock gating. Value: <0> (forcibly
|
||||
disable), <1> (forcibly enable), property absent (OS specific behavior,
|
||||
preferrably retain firmware settings)
|
||||
preferably retain firmware settings)
|
||||
- arm,standby-mode: L2 standby mode enable. Value <0> (forcibly disable),
|
||||
<1> (forcibly enable), property absent (OS specific behavior,
|
||||
preferrably retain firmware settings)
|
||||
preferably retain firmware settings)
|
||||
|
||||
Example:
|
||||
|
||||
|
@ -8,8 +8,19 @@ Required root node property:
|
||||
|
||||
- compatible: must contain "marvell,armada390"
|
||||
|
||||
In addition, boards using the Marvell Armada 398 SoC shall have the
|
||||
following property before the previous one:
|
||||
In addition, boards using the Marvell Armada 395 SoC shall have the
|
||||
following property before the common "marvell,armada390" one:
|
||||
|
||||
Required root node property:
|
||||
|
||||
compatible: must contain "marvell,armada395"
|
||||
|
||||
Example:
|
||||
|
||||
compatible = "marvell,a395-gp", "marvell,armada395", "marvell,armada390";
|
||||
|
||||
Boards using the Marvell Armada 398 SoC shall have the following
|
||||
property before the common "marvell,armada390" one:
|
||||
|
||||
Required root node property:
|
||||
|
||||
|
25
Bindings/arm/marvell/marvell,orion5x.txt
Normal file
25
Bindings/arm/marvell/marvell,orion5x.txt
Normal file
@ -0,0 +1,25 @@
|
||||
Marvell Orion SoC Family Device Tree Bindings
|
||||
---------------------------------------------
|
||||
|
||||
Boards with a SoC of the Marvell Orion family, eg 88f5181
|
||||
|
||||
* Required root node properties:
|
||||
compatible: must contain "marvell,orion5x"
|
||||
|
||||
In addition, the above compatible shall be extended with the specific
|
||||
SoC. Currently known SoC compatibles are:
|
||||
|
||||
"marvell,orion5x-88f5181"
|
||||
"marvell,orion5x-88f5182"
|
||||
|
||||
And in addition, the compatible shall be extended with the specific
|
||||
board. Currently known boards are:
|
||||
|
||||
"buffalo,lsgl"
|
||||
"buffalo,lswsgl"
|
||||
"buffalo,lswtgl"
|
||||
"lacie,ethernet-disk-mini-v2"
|
||||
"lacie,d2-network"
|
||||
"marvell,rd-88f5182-nas"
|
||||
"maxtor,shared-storage-2"
|
||||
"netgear,wnr854t"
|
@ -10,6 +10,7 @@ compatible: Must contain one of
|
||||
"mediatek,mt6580"
|
||||
"mediatek,mt6589"
|
||||
"mediatek,mt6592"
|
||||
"mediatek,mt6755"
|
||||
"mediatek,mt6795"
|
||||
"mediatek,mt7623"
|
||||
"mediatek,mt8127"
|
||||
@ -31,6 +32,9 @@ Supported boards:
|
||||
- Evaluation board for MT6592:
|
||||
Required root node properties:
|
||||
- compatible = "mediatek,mt6592-evb", "mediatek,mt6592";
|
||||
- Evaluation phone for MT6755(Helio P10):
|
||||
Required root node properties:
|
||||
- compatible = "mediatek,mt6755-evb", "mediatek,mt6755";
|
||||
- Evaluation board for MT6795(Helio X10):
|
||||
Required root node properties:
|
||||
- compatible = "mediatek,mt6795-evb", "mediatek,mt6795";
|
||||
|
@ -5,7 +5,8 @@ The Mediatek apmixedsys controller provides the PLLs to the system.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: Should be:
|
||||
- compatible: Should be one of:
|
||||
- "mediatek,mt2701-apmixedsys"
|
||||
- "mediatek,mt8135-apmixedsys"
|
||||
- "mediatek,mt8173-apmixedsys"
|
||||
- #clock-cells: Must be 1
|
||||
|
22
Bindings/arm/mediatek/mediatek,bdpsys.txt
Normal file
22
Bindings/arm/mediatek/mediatek,bdpsys.txt
Normal file
@ -0,0 +1,22 @@
|
||||
Mediatek bdpsys controller
|
||||
============================
|
||||
|
||||
The Mediatek bdpsys controller provides various clocks to the system.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: Should be:
|
||||
- "mediatek,mt2701-bdpsys", "syscon"
|
||||
- #clock-cells: Must be 1
|
||||
|
||||
The bdpsys controller uses the common clk binding from
|
||||
Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
The available clocks are defined in dt-bindings/clock/mt*-clk.h.
|
||||
|
||||
Example:
|
||||
|
||||
bdpsys: clock-controller@1c000000 {
|
||||
compatible = "mediatek,mt2701-bdpsys", "syscon";
|
||||
reg = <0 0x1c000000 0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
22
Bindings/arm/mediatek/mediatek,ethsys.txt
Normal file
22
Bindings/arm/mediatek/mediatek,ethsys.txt
Normal file
@ -0,0 +1,22 @@
|
||||
Mediatek ethsys controller
|
||||
============================
|
||||
|
||||
The Mediatek ethsys controller provides various clocks to the system.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: Should be:
|
||||
- "mediatek,mt2701-ethsys", "syscon"
|
||||
- #clock-cells: Must be 1
|
||||
|
||||
The ethsys controller uses the common clk binding from
|
||||
Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
The available clocks are defined in dt-bindings/clock/mt*-clk.h.
|
||||
|
||||
Example:
|
||||
|
||||
ethsys: clock-controller@1b000000 {
|
||||
compatible = "mediatek,mt2701-ethsys", "syscon";
|
||||
reg = <0 0x1b000000 0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
24
Bindings/arm/mediatek/mediatek,hifsys.txt
Normal file
24
Bindings/arm/mediatek/mediatek,hifsys.txt
Normal file
@ -0,0 +1,24 @@
|
||||
Mediatek hifsys controller
|
||||
============================
|
||||
|
||||
The Mediatek hifsys controller provides various clocks and reset
|
||||
outputs to the system.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: Should be:
|
||||
- "mediatek,mt2701-hifsys", "syscon"
|
||||
- #clock-cells: Must be 1
|
||||
|
||||
The hifsys controller uses the common clk binding from
|
||||
Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
The available clocks are defined in dt-bindings/clock/mt*-clk.h.
|
||||
|
||||
Example:
|
||||
|
||||
hifsys: clock-controller@1a000000 {
|
||||
compatible = "mediatek,mt2701-hifsys", "syscon";
|
||||
reg = <0 0x1a000000 0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
@ -5,7 +5,8 @@ The Mediatek imgsys controller provides various clocks to the system.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: Should be:
|
||||
- compatible: Should be one of:
|
||||
- "mediatek,mt2701-imgsys", "syscon"
|
||||
- "mediatek,mt8173-imgsys", "syscon"
|
||||
- #clock-cells: Must be 1
|
||||
|
||||
|
@ -6,7 +6,8 @@ outputs to the system.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: Should be:
|
||||
- compatible: Should be one of:
|
||||
- "mediatek,mt2701-infracfg", "syscon"
|
||||
- "mediatek,mt8135-infracfg", "syscon"
|
||||
- "mediatek,mt8173-infracfg", "syscon"
|
||||
- #clock-cells: Must be 1
|
||||
|
@ -5,7 +5,8 @@ The Mediatek mmsys controller provides various clocks to the system.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: Should be:
|
||||
- compatible: Should be one of:
|
||||
- "mediatek,mt2701-mmsys", "syscon"
|
||||
- "mediatek,mt8173-mmsys", "syscon"
|
||||
- #clock-cells: Must be 1
|
||||
|
||||
|
@ -6,7 +6,8 @@ outputs to the system.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: Should be:
|
||||
- compatible: Should be one of:
|
||||
- "mediatek,mt2701-pericfg", "syscon"
|
||||
- "mediatek,mt8135-pericfg", "syscon"
|
||||
- "mediatek,mt8173-pericfg", "syscon"
|
||||
- #clock-cells: Must be 1
|
||||
|
@ -5,7 +5,8 @@ The Mediatek topckgen controller provides various clocks to the system.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: Should be:
|
||||
- compatible: Should be one of:
|
||||
- "mediatek,mt2701-topckgen"
|
||||
- "mediatek,mt8135-topckgen"
|
||||
- "mediatek,mt8173-topckgen"
|
||||
- #clock-cells: Must be 1
|
||||
|
@ -5,7 +5,8 @@ The Mediatek vdecsys controller provides various clocks to the system.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: Should be:
|
||||
- compatible: Should be one of:
|
||||
- "mediatek,mt2701-vdecsys", "syscon"
|
||||
- "mediatek,mt8173-vdecsys", "syscon"
|
||||
- #clock-cells: Must be 1
|
||||
|
||||
|
@ -1,5 +1,9 @@
|
||||
Olimex i.MX Platforms Device Tree Bindings
|
||||
------------------------------------------
|
||||
Olimex Device Tree Bindings
|
||||
---------------------------
|
||||
|
||||
SAM9-L9260 Board
|
||||
Required root node properties:
|
||||
- compatible = "olimex,sam9-l9260", "atmel,at91sam9260";
|
||||
|
||||
i.MX23 Olinuxino Low Cost Board
|
||||
Required root node properties:
|
||||
|
@ -86,6 +86,9 @@ SoCs:
|
||||
- DRA722
|
||||
compatible = "ti,dra722", "ti,dra72", "ti,dra7"
|
||||
|
||||
- DRA718
|
||||
compatible = "ti,dra718", "ti,dra722", "ti,dra72", "ti,dra7"
|
||||
|
||||
- AM5728
|
||||
compatible = "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7"
|
||||
|
||||
@ -175,8 +178,20 @@ Boards:
|
||||
- AM5728 IDK
|
||||
compatible = "ti,am5728-idk", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7"
|
||||
|
||||
- AM5718 IDK
|
||||
compatible = "ti,am5718-idk", "ti,am5718", "ti,dra7"
|
||||
|
||||
- DRA742 EVM: Software Development Board for DRA742
|
||||
compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7"
|
||||
|
||||
- DRA722 EVM: Software Development Board for DRA722
|
||||
compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7"
|
||||
|
||||
- DRA718 EVM: Software Development Board for DRA718
|
||||
compatible = "ti,dra718-evm", "ti,dra718", "ti,dra722", "ti,dra72", "ti,dra7"
|
||||
|
||||
- DM3730 Logic PD Torpedo + Wireless: Commercial System on Module with WiFi and Bluetooth
|
||||
compatible = "logicpd,dm3730-torpedo-devkit", "ti,omap3630", "ti,omap3"
|
||||
|
||||
- DM3730 Logic PD SOM-LV: Commercial System on Module with WiFi and Bluetooth
|
||||
compatible = "logicpd,dm3730-som-lv-devkit", "ti,omap3630", "ti,omap3"
|
||||
|
@ -5,5 +5,10 @@ Boards with the OX810SE SoC shall have the following properties:
|
||||
Required root node property:
|
||||
compatible: "oxsemi,ox810se"
|
||||
|
||||
Boards with the OX820 SoC shall have the following properties:
|
||||
Required root node property:
|
||||
compatible: "oxsemi,ox820"
|
||||
|
||||
Board compatible values:
|
||||
- "wd,mbwe" (OX810SE)
|
||||
- "cloudengines,pogoplugv3" (OX820)
|
||||
|
@ -39,7 +39,9 @@ Optional properties:
|
||||
When using a PPI, specifies a list of phandles to CPU
|
||||
nodes corresponding to the set of CPUs which have
|
||||
a PMU of this type signalling the PPI listed in the
|
||||
interrupts property.
|
||||
interrupts property, unless this is already specified
|
||||
by the PPI interrupt specifier itself (in which case
|
||||
the interrupt-affinity property shouldn't be present).
|
||||
|
||||
This property should be present when there is more than
|
||||
a single SPI.
|
||||
|
@ -21,7 +21,10 @@ The 'SoC' element must be one of the following strings:
|
||||
apq8096
|
||||
msm8916
|
||||
msm8974
|
||||
msm8992
|
||||
msm8994
|
||||
msm8996
|
||||
mdm9615
|
||||
|
||||
The 'board' element must be one of the following strings:
|
||||
|
||||
|
@ -25,12 +25,20 @@ Rockchip platforms device tree bindings
|
||||
Required root node properties:
|
||||
- compatible = "radxa,rock2-square", "rockchip,rk3288";
|
||||
|
||||
- Rikomagic MK808 v1 board:
|
||||
Required root node properties:
|
||||
- compatible = "rikomagic,mk808", "rockchip,rk3066a";
|
||||
|
||||
- Firefly Firefly-RK3288 board:
|
||||
Required root node properties:
|
||||
- compatible = "firefly,firefly-rk3288", "rockchip,rk3288";
|
||||
or
|
||||
- compatible = "firefly,firefly-rk3288-beta", "rockchip,rk3288";
|
||||
|
||||
- Firefly Firefly-RK3288 Reload board:
|
||||
Required root node properties:
|
||||
- compatible = "firefly,firefly-rk3288-reload", "rockchip,rk3288";
|
||||
|
||||
- ChipSPARK PopMetal-RK3288 board:
|
||||
Required root node properties:
|
||||
- compatible = "chipspark,popmetal-rk3288", "rockchip,rk3288";
|
||||
@ -95,6 +103,18 @@ Rockchip platforms device tree bindings
|
||||
Required root node properties:
|
||||
- compatible = "mqmaker,miqi", "rockchip,rk3288";
|
||||
|
||||
- Rockchip PX3 Evaluation board:
|
||||
Required root node properties:
|
||||
- compatible = "rockchip,px3-evb", "rockchip,px3", "rockchip,rk3188";
|
||||
|
||||
- Rockchip PX5 Evaluation board:
|
||||
Required root node properties:
|
||||
- compatible = "rockchip,px5-evb", "rockchip,px5", "rockchip,rk3368";
|
||||
|
||||
- Rockchip RK1108 Evaluation board
|
||||
Required root node properties:
|
||||
- compatible = "rockchip,rk1108-evb", "rockchip,rk1108";
|
||||
|
||||
- Rockchip RK3368 evb:
|
||||
Required root node properties:
|
||||
- compatible = "rockchip,rk3368-evb-act8846", "rockchip,rk3368";
|
||||
@ -107,6 +127,17 @@ Rockchip platforms device tree bindings
|
||||
Required root node properties:
|
||||
- compatible = "rockchip,rk3228-evb", "rockchip,rk3228";
|
||||
|
||||
- Rockchip RK3229 Evaluation board:
|
||||
- compatible = "rockchip,rk3229-evb", "rockchip,rk3229";
|
||||
|
||||
- Rockchip RK3288 Fennec board:
|
||||
Required root node properties:
|
||||
- compatible = "rockchip,rk3288-fennec", "rockchip,rk3288";
|
||||
|
||||
- Rockchip RK3399 evb:
|
||||
Required root node properties:
|
||||
- compatible = "rockchip,rk3399-evb", "rockchip,rk3399";
|
||||
|
||||
- Tronsmart Orion R68 Meta
|
||||
Required root node properties:
|
||||
- compatible = "tronsmart,orion-r68-meta", "rockchip,rk3368";
|
||||
|
@ -10,6 +10,7 @@ Properties:
|
||||
- "samsung,exynos5260-pmu" - for Exynos5260 SoC.
|
||||
- "samsung,exynos5410-pmu" - for Exynos5410 SoC,
|
||||
- "samsung,exynos5420-pmu" - for Exynos5420 SoC.
|
||||
- "samsung,exynos5433-pmu" - for Exynos5433 SoC.
|
||||
- "samsung,exynos7-pmu" - for Exynos7 SoC.
|
||||
second value must be always "syscon".
|
||||
|
||||
|
@ -15,6 +15,8 @@ Required root node properties:
|
||||
- "samsung,xyref5260" - for Exynos5260-based Samsung board.
|
||||
- "samsung,smdk5410" - for Exynos5410-based Samsung SMDK5410 eval board.
|
||||
- "samsung,smdk5420" - for Exynos5420-based Samsung SMDK5420 eval board.
|
||||
- "samsung,tm2" - for Exynos5433-based Samsung TM2 board.
|
||||
- "samsung,tm2e" - for Exynos5433-based Samsung TM2E board.
|
||||
- "samsung,sd5v1" - for Exynos5440-based Samsung board.
|
||||
- "samsung,ssdk5440" - for Exynos5440-based Samsung board.
|
||||
|
||||
@ -22,6 +24,9 @@ Required root node properties:
|
||||
* FriendlyARM
|
||||
- "friendlyarm,tiny4412" - for Exynos4412-based FriendlyARM
|
||||
TINY4412 board.
|
||||
* TOPEET
|
||||
- "topeet,itop4412-elite" - for Exynos4412-based TOPEET
|
||||
Elite base board.
|
||||
|
||||
* Google
|
||||
- "google,pi" - for Exynos5800-based Google Peach Pi
|
||||
@ -47,6 +52,7 @@ Required root node properties:
|
||||
- "hardkernel,odroid-u3" - for Exynos4412-based Hardkernel Odroid U3.
|
||||
- "hardkernel,odroid-x" - for Exynos4412-based Hardkernel Odroid X.
|
||||
- "hardkernel,odroid-x2" - for Exynos4412-based Hardkernel Odroid X2.
|
||||
- "hardkernel,odroid-xu" - for Exynos5410-based Hardkernel Odroid XU.
|
||||
- "hardkernel,odroid-xu3" - for Exynos5422-based Hardkernel Odroid XU3.
|
||||
- "hardkernel,odroid-xu3-lite" - for Exynos5422-based Hardkernel
|
||||
Odroid XU3 Lite board.
|
||||
|
@ -13,6 +13,10 @@ SoCs:
|
||||
compatible = "renesas,r8a73a4"
|
||||
- R-Mobile A1 (R8A77400)
|
||||
compatible = "renesas,r8a7740"
|
||||
- RZ/G1M (R8A77430)
|
||||
compatible = "renesas,r8a7743"
|
||||
- RZ/G1E (R8A77450)
|
||||
compatible = "renesas,r8a7745"
|
||||
- R-Car M1A (R8A77781)
|
||||
compatible = "renesas,r8a7778"
|
||||
- R-Car H1 (R8A77790)
|
||||
@ -29,22 +33,28 @@ SoCs:
|
||||
compatible = "renesas,r8a7794"
|
||||
- R-Car H3 (R8A77950)
|
||||
compatible = "renesas,r8a7795"
|
||||
- R-Car M3-W (R8A77960)
|
||||
compatible = "renesas,r8a7796"
|
||||
|
||||
|
||||
Boards:
|
||||
|
||||
- Alt
|
||||
- Alt (RTP0RC7794SEB00010S)
|
||||
compatible = "renesas,alt", "renesas,r8a7794"
|
||||
- APE6-EVM
|
||||
compatible = "renesas,ape6evm", "renesas,r8a73a4"
|
||||
- Atmark Techno Armadillo-800 EVA
|
||||
compatible = "renesas,armadillo800eva"
|
||||
- Blanche (RTP0RC7792SEB00010S)
|
||||
compatible = "renesas,blanche", "renesas,r8a7792"
|
||||
- BOCK-W
|
||||
compatible = "renesas,bockw", "renesas,r8a7778"
|
||||
- Genmai (RTK772100BC00000BR)
|
||||
compatible = "renesas,genmai", "renesas,r7s72100"
|
||||
- Gose
|
||||
- Gose (RTP0RC7793SEB00010S)
|
||||
compatible = "renesas,gose", "renesas,r8a7793"
|
||||
- H3ULCB (R-Car Starter Kit Premier, RTP0RC7795SKB00010S)
|
||||
compatible = "renesas,h3ulcb", "renesas,r8a7795";
|
||||
- Henninger
|
||||
compatible = "renesas,henninger", "renesas,r8a7791"
|
||||
- Koelsch (RTP0RC7791SEB00010S)
|
||||
@ -55,11 +65,41 @@ Boards:
|
||||
compatible = "renesas,kzm9g", "renesas,sh73a0"
|
||||
- Lager (RTP0RC7790SEB00010S)
|
||||
compatible = "renesas,lager", "renesas,r8a7790"
|
||||
- Marzen
|
||||
- M3ULCB (R-Car Starter Kit Pro, RTP0RC7796SKB00010S)
|
||||
compatible = "renesas,m3ulcb", "renesas,r8a7796";
|
||||
- Marzen (R0P7779A00010S)
|
||||
compatible = "renesas,marzen", "renesas,r8a7779"
|
||||
- Porter (M2-LCDP)
|
||||
compatible = "renesas,porter", "renesas,r8a7791"
|
||||
- RSKRZA1 (YR0K77210C000BE)
|
||||
compatible = "renesas,rskrza1", "renesas,r7s72100"
|
||||
- Salvator-X (RTP0RC7795SIPB0010S)
|
||||
compatible = "renesas,salvator-x", "renesas,r8a7795";
|
||||
- Salvator-X
|
||||
compatible = "renesas,salvator-x", "renesas,r8a7796";
|
||||
- SILK (RTP0RC7794LCB00011S)
|
||||
compatible = "renesas,silk", "renesas,r8a7794"
|
||||
- SK-RZG1E (YR8A77450S000BE)
|
||||
compatible = "renesas,sk-rzg1e", "renesas,r8a7745"
|
||||
- SK-RZG1M (YR8A77430S000BE)
|
||||
compatible = "renesas,sk-rzg1m", "renesas,r8a7743"
|
||||
- Wheat
|
||||
compatible = "renesas,wheat", "renesas,r8a7792"
|
||||
|
||||
|
||||
Most Renesas ARM SoCs have a Product Register that allows to retrieve SoC
|
||||
product and revision information. If present, a device node for this register
|
||||
should be added.
|
||||
|
||||
Required properties:
|
||||
- compatible: Must be "renesas,prr".
|
||||
- reg: Base address and length of the register block.
|
||||
|
||||
|
||||
Examples
|
||||
--------
|
||||
|
||||
prr: chipid@ff000044 {
|
||||
compatible = "renesas,prr";
|
||||
reg = <0 0xff000044 0 4>;
|
||||
};
|
||||
|
@ -14,3 +14,5 @@ using one of the following compatible strings:
|
||||
allwinner,sun8i-a83t
|
||||
allwinner,sun8i-h3
|
||||
allwinner,sun9i-a80
|
||||
allwinner,sun50i-a64
|
||||
nextthing,gr8
|
||||
|
12
Bindings/arm/swir.txt
Normal file
12
Bindings/arm/swir.txt
Normal file
@ -0,0 +1,12 @@
|
||||
Sierra Wireless Modules device tree bindings
|
||||
--------------------------------------------
|
||||
|
||||
Supported Modules :
|
||||
- WP8548 : Includes MDM9615 and PM8018 in a module
|
||||
|
||||
Sierra Wireless modules shall have the following properties :
|
||||
Required root node property
|
||||
- compatible: "swir,wp8548" for the WP8548 CF3 Module
|
||||
|
||||
Board compatible values:
|
||||
- "swir,mangoh-green-wp8548" for the mangOH green board with the WP8548 module
|
@ -4,3 +4,9 @@ Technologic Systems Platforms Device Tree Bindings
|
||||
TS-4800 board
|
||||
Required root node properties:
|
||||
- compatible = "technologic,imx51-ts4800", "fsl,imx51";
|
||||
|
||||
TS-4900 is a System-on-Module based on the Freescale i.MX6 System-on-Chip.
|
||||
It can be mounted on a carrier board providing additional peripheral connectors.
|
||||
Required root node properties:
|
||||
- compatible = "technologic,imx6dl-ts4900", "fsl,imx6dl"
|
||||
- compatible = "technologic,imx6q-ts4900", "fsl,imx6q"
|
||||
|
@ -32,7 +32,11 @@ board-specific compatible values:
|
||||
nvidia,whistler
|
||||
toradex,apalis_t30
|
||||
toradex,apalis_t30-eval
|
||||
toradex,apalis-tk1
|
||||
toradex,apalis-tk1-eval
|
||||
toradex,colibri_t20-512
|
||||
toradex,colibri_t30
|
||||
toradex,colibri_t30-eval-v3
|
||||
toradex,iris
|
||||
|
||||
Trusted Foundations
|
||||
|
@ -11,10 +11,32 @@ the following properties:
|
||||
memory where the grant table should be mapped to, using an
|
||||
HYPERVISOR_memory_op hypercall. The memory region is large enough to map
|
||||
the whole grant table (it is larger or equal to gnttab_max_grant_frames()).
|
||||
This property is unnecessary when booting Dom0 using ACPI.
|
||||
|
||||
- interrupts: the interrupt used by Xen to inject event notifications.
|
||||
A GIC node is also required.
|
||||
This property is unnecessary when booting Dom0 using ACPI.
|
||||
|
||||
To support UEFI on Xen ARM virtual platforms, Xen populates the FDT "uefi" node
|
||||
under /hypervisor with following parameters:
|
||||
|
||||
________________________________________________________________________________
|
||||
Name | Size | Description
|
||||
================================================================================
|
||||
xen,uefi-system-table | 64-bit | Guest physical address of the UEFI System
|
||||
| | Table.
|
||||
--------------------------------------------------------------------------------
|
||||
xen,uefi-mmap-start | 64-bit | Guest physical address of the UEFI memory
|
||||
| | map.
|
||||
--------------------------------------------------------------------------------
|
||||
xen,uefi-mmap-size | 32-bit | Size in bytes of the UEFI memory map
|
||||
| | pointed to in previous entry.
|
||||
--------------------------------------------------------------------------------
|
||||
xen,uefi-mmap-desc-size | 32-bit | Size in bytes of each entry in the UEFI
|
||||
| | memory map.
|
||||
--------------------------------------------------------------------------------
|
||||
xen,uefi-mmap-desc-ver | 32-bit | Version of the mmap descriptor format.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
Example (assuming #address-cells = <2> and #size-cells = <2>):
|
||||
|
||||
@ -22,4 +44,17 @@ hypervisor {
|
||||
compatible = "xen,xen-4.3", "xen,xen";
|
||||
reg = <0 0xb0000000 0 0x20000>;
|
||||
interrupts = <1 15 0xf08>;
|
||||
uefi {
|
||||
xen,uefi-system-table = <0xXXXXXXXX>;
|
||||
xen,uefi-mmap-start = <0xXXXXXXXX>;
|
||||
xen,uefi-mmap-size = <0xXXXXXXXX>;
|
||||
xen,uefi-mmap-desc-size = <0xXXXXXXXX>;
|
||||
xen,uefi-mmap-desc-ver = <0xXXXXXXXX>;
|
||||
};
|
||||
};
|
||||
|
||||
The format and meaning of the "xen,uefi-*" parameters are similar to those in
|
||||
Documentation/arm/uefi.txt, which are provided by the regular UEFI stub. However
|
||||
they differ because they are provided by the Xen hypervisor, together with a set
|
||||
of UEFI runtime services implemented via hypercalls, see
|
||||
http://xenbits.xen.org/docs/unstable/hypercall/x86_64/include,public,platform.h.html.
|
||||
|
@ -13,3 +13,27 @@ Low power management required properties:
|
||||
|
||||
Bus matrix required properties:
|
||||
- compatible = "zte,zx-bus-matrix"
|
||||
|
||||
|
||||
---------------------------------------
|
||||
- ZX296718 SoC:
|
||||
Required root node properties:
|
||||
- compatible = "zte,zx296718"
|
||||
|
||||
ZX296718 EVB board:
|
||||
- "zte,zx296718-evb"
|
||||
|
||||
System management required properties:
|
||||
- compatible = "zte,zx296718-aon-sysctrl"
|
||||
- compatible = "zte,zx296718-sysctrl"
|
||||
|
||||
Example:
|
||||
aon_sysctrl: aon-sysctrl@116000 {
|
||||
compatible = "zte,zx296718-aon-sysctrl", "syscon";
|
||||
reg = <0x116000 0x1000>;
|
||||
};
|
||||
|
||||
sysctrl: sysctrl@1463000 {
|
||||
compatible = "zte,zx296718-sysctrl", "syscon";
|
||||
reg = <0x1463000 0x1000>;
|
||||
};
|
||||
|
@ -3,7 +3,7 @@ Binding for Freescale QorIQ AHCI SATA Controller
|
||||
Required properties:
|
||||
- reg: Physical base address and size of the controller's register area.
|
||||
- compatible: Compatibility string. Must be 'fsl,<chip>-ahci', where
|
||||
chip could be ls1021a, ls2080a, ls1043a etc.
|
||||
chip could be ls1021a, ls1043a, ls1046a, ls2080a etc.
|
||||
- clocks: Input clock specifier. Refer to common clock bindings.
|
||||
- interrupts: Interrupt specifier. Refer to interrupt binding.
|
||||
|
||||
|
@ -10,6 +10,7 @@ PHYs.
|
||||
Required properties:
|
||||
- compatible : compatible string, one of:
|
||||
- "allwinner,sun4i-a10-ahci"
|
||||
- "brcm,iproc-ahci"
|
||||
- "hisilicon,hisi-ahci"
|
||||
- "cavium,octeon-7130-ahci"
|
||||
- "ibm,476gtr-ahci"
|
||||
|
@ -18,21 +18,6 @@ Optional properties:
|
||||
|
||||
Example:
|
||||
|
||||
/* Example for stih416 */
|
||||
sata0: sata@fe380000 {
|
||||
compatible = "st,ahci";
|
||||
reg = <0xfe380000 0x1000>;
|
||||
interrupts = <GIC_SPI 157 IRQ_TYPE_NONE>;
|
||||
interrupt-names = "hostc";
|
||||
phys = <&phy_port0 PHY_TYPE_SATA>;
|
||||
phy-names = "ahci_phy";
|
||||
resets = <&powerdown STIH416_SATA0_POWERDOWN>,
|
||||
<&softreset STIH416_SATA0_SOFTRESET>;
|
||||
reset-names = "pwr-dwn", "sw-rst";
|
||||
clocks = <&clk_s_a0_ls CLK_ICN_REG>;
|
||||
clock-names = "ahci_clk";
|
||||
};
|
||||
|
||||
/* Example for stih407 family silicon */
|
||||
sata0: sata@9b20000 {
|
||||
compatible = "st,ahci";
|
||||
|
37
Bindings/ata/brcm,sata-brcm.txt
Normal file
37
Bindings/ata/brcm,sata-brcm.txt
Normal file
@ -0,0 +1,37 @@
|
||||
* Broadcom SATA3 AHCI Controller
|
||||
|
||||
SATA nodes are defined to describe on-chip Serial ATA controllers.
|
||||
Each SATA controller should have its own node.
|
||||
|
||||
Required properties:
|
||||
- compatible : should be one or more of
|
||||
"brcm,bcm7425-ahci"
|
||||
"brcm,bcm7445-ahci"
|
||||
"brcm,bcm-nsp-ahci"
|
||||
"brcm,sata3-ahci"
|
||||
- reg : register mappings for AHCI and SATA_TOP_CTRL
|
||||
- reg-names : "ahci" and "top-ctrl"
|
||||
- interrupts : interrupt mapping for SATA IRQ
|
||||
|
||||
Also see ahci-platform.txt.
|
||||
|
||||
Example:
|
||||
|
||||
sata@f045a000 {
|
||||
compatible = "brcm,bcm7445-ahci", "brcm,sata3-ahci";
|
||||
reg = <0xf045a000 0xa9c>, <0xf0458040 0x24>;
|
||||
reg-names = "ahci", "top-ctrl";
|
||||
interrupts = <0 30 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
sata0: sata-port@0 {
|
||||
reg = <0>;
|
||||
phys = <&sata_phy 0>;
|
||||
};
|
||||
|
||||
sata1: sata-port@1 {
|
||||
reg = <1>;
|
||||
phys = <&sata_phy 1>;
|
||||
};
|
||||
};
|
17
Bindings/auxdisplay/img-ascii-lcd.txt
Normal file
17
Bindings/auxdisplay/img-ascii-lcd.txt
Normal file
@ -0,0 +1,17 @@
|
||||
Binding for ASCII LCD displays on Imagination Technologies boards
|
||||
|
||||
Required properties:
|
||||
- compatible : should be one of:
|
||||
"img,boston-lcd"
|
||||
"mti,malta-lcd"
|
||||
"mti,sead3-lcd"
|
||||
|
||||
Required properties for "img,boston-lcd":
|
||||
- reg : memory region locating the device registers
|
||||
|
||||
Required properties for "mti,malta-lcd" or "mti,sead3-lcd":
|
||||
- regmap: phandle of the system controller containing the LCD registers
|
||||
- offset: offset in bytes to the LCD registers within the system controller
|
||||
|
||||
The layout of the registers & properties of the display are determined
|
||||
from the compatible string, making this binding somewhat trivial.
|
132
Bindings/bus/nvidia,tegra20-gmi.txt
Normal file
132
Bindings/bus/nvidia,tegra20-gmi.txt
Normal file
@ -0,0 +1,132 @@
|
||||
Device tree bindings for NVIDIA Tegra Generic Memory Interface bus
|
||||
|
||||
The Generic Memory Interface bus enables memory transfers between internal and
|
||||
external memory. Can be used to attach various high speed devices such as
|
||||
synchronous/asynchronous NOR, FPGA, UARTS and more.
|
||||
|
||||
The actual devices are instantiated from the child nodes of a GMI node.
|
||||
|
||||
Required properties:
|
||||
- compatible : Should contain one of the following:
|
||||
For Tegra20 must contain "nvidia,tegra20-gmi".
|
||||
For Tegra30 must contain "nvidia,tegra30-gmi".
|
||||
- reg: Should contain GMI controller registers location and length.
|
||||
- clocks: Must contain an entry for each entry in clock-names.
|
||||
- clock-names: Must include the following entries: "gmi"
|
||||
- resets : Must contain an entry for each entry in reset-names.
|
||||
- reset-names : Must include the following entries: "gmi"
|
||||
- #address-cells: The number of cells used to represent physical base
|
||||
addresses in the GMI address space. Should be 2.
|
||||
- #size-cells: The number of cells used to represent the size of an address
|
||||
range in the GMI address space. Should be 1.
|
||||
- ranges: Must be set up to reflect the memory layout with three integer values
|
||||
for each chip-select line in use (only one entry is supported, see below
|
||||
comments):
|
||||
<cs-number> <offset> <physical address of mapping> <size>
|
||||
|
||||
Note that the GMI controller does not have any internal chip-select address
|
||||
decoding, because of that chip-selects either need to be managed via software
|
||||
or by employing external chip-select decoding logic.
|
||||
|
||||
If external chip-select logic is used to support multiple devices it is assumed
|
||||
that the devices use the same timing and so are probably the same type. It also
|
||||
assumes that they can fit in the 256MB address range. In this case only one
|
||||
child device is supported which represents the active chip-select line, see
|
||||
examples for more insight.
|
||||
|
||||
The chip-select number is decoded from the child nodes second address cell of
|
||||
'ranges' property, if 'ranges' property is not present or empty chip-select will
|
||||
then be decoded from the first cell of the 'reg' property.
|
||||
|
||||
Optional child cs node properties:
|
||||
|
||||
- nvidia,snor-data-width-32bit: Use 32bit data-bus, default is 16bit.
|
||||
- nvidia,snor-mux-mode: Enable address/data MUX mode.
|
||||
- nvidia,snor-rdy-active-before-data: Assert RDY signal one cycle before data.
|
||||
If omitted it will be asserted with data.
|
||||
- nvidia,snor-rdy-active-high: RDY signal is active high
|
||||
- nvidia,snor-adv-active-high: ADV signal is active high
|
||||
- nvidia,snor-oe-active-high: WE/OE signal is active high
|
||||
- nvidia,snor-cs-active-high: CS signal is active high
|
||||
|
||||
Note that there is some special handling for the timing values.
|
||||
From Tegra TRM:
|
||||
Programming 0 means 1 clock cycle: actual cycle = programmed cycle + 1
|
||||
|
||||
- nvidia,snor-muxed-width: Number of cycles MUX address/data asserted on the
|
||||
bus. Valid values are 0-15, default is 1
|
||||
- nvidia,snor-hold-width: Number of cycles CE stays asserted after the
|
||||
de-assertion of WR_N (in case of SLAVE/MASTER Request) or OE_N
|
||||
(in case of MASTER Request). Valid values are 0-15, default is 1
|
||||
- nvidia,snor-adv-width: Number of cycles during which ADV stays asserted.
|
||||
Valid values are 0-15, default is 1.
|
||||
- nvidia,snor-ce-width: Number of cycles before CE is asserted.
|
||||
Valid values are 0-15, default is 4
|
||||
- nvidia,snor-we-width: Number of cycles during which WE stays asserted.
|
||||
Valid values are 0-15, default is 1
|
||||
- nvidia,snor-oe-width: Number of cycles during which OE stays asserted.
|
||||
Valid values are 0-255, default is 1
|
||||
- nvidia,snor-wait-width: Number of cycles before READY is asserted.
|
||||
Valid values are 0-255, default is 3
|
||||
|
||||
Example with two SJA1000 CAN controllers connected to the GMI bus. We wrap the
|
||||
controllers with a simple-bus node since they are all connected to the same
|
||||
chip-select (CS4), in this example external address decoding is provided:
|
||||
|
||||
gmi@70090000 {
|
||||
compatible = "nvidia,tegra20-gmi";
|
||||
reg = <0x70009000 0x1000>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
clocks = <&tegra_car TEGRA20_CLK_NOR>;
|
||||
clock-names = "gmi";
|
||||
resets = <&tegra_car 42>;
|
||||
reset-names = "gmi";
|
||||
ranges = <4 0 0xd0000000 0xfffffff>;
|
||||
|
||||
status = "okay";
|
||||
|
||||
bus@4,0 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 4 0 0x40100>;
|
||||
|
||||
nvidia,snor-mux-mode;
|
||||
nvidia,snor-adv-active-high;
|
||||
|
||||
can@0 {
|
||||
reg = <0 0x100>;
|
||||
...
|
||||
};
|
||||
|
||||
can@40000 {
|
||||
reg = <0x40000 0x100>;
|
||||
...
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
Example with one SJA1000 CAN controller connected to the GMI bus
|
||||
on CS4:
|
||||
|
||||
gmi@70090000 {
|
||||
compatible = "nvidia,tegra20-gmi";
|
||||
reg = <0x70009000 0x1000>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
clocks = <&tegra_car TEGRA20_CLK_NOR>;
|
||||
clock-names = "gmi";
|
||||
resets = <&tegra_car 42>;
|
||||
reset-names = "gmi";
|
||||
ranges = <4 0 0xd0000000 0xfffffff>;
|
||||
|
||||
status = "okay";
|
||||
|
||||
can@4,0 {
|
||||
reg = <4 0 0x100>;
|
||||
nvidia,snor-mux-mode;
|
||||
nvidia,snor-adv-active-high;
|
||||
...
|
||||
};
|
||||
};
|
45
Bindings/bus/nvidia,tegra210-aconnect.txt
Normal file
45
Bindings/bus/nvidia,tegra210-aconnect.txt
Normal file
@ -0,0 +1,45 @@
|
||||
NVIDIA Tegra ACONNECT Bus
|
||||
|
||||
The Tegra ACONNECT bus is an AXI switch which is used to connnect various
|
||||
components inside the Audio Processing Engine (APE). All CPU accesses to
|
||||
the APE subsystem go through the ACONNECT via an APB to AXI wrapper.
|
||||
|
||||
Required properties:
|
||||
- compatible: Must be "nvidia,tegra210-aconnect".
|
||||
- clocks: Must contain the entries for the APE clock (TEGRA210_CLK_APE),
|
||||
and APE interface clock (TEGRA210_CLK_APB2APE).
|
||||
- clock-names: Must contain the names "ape" and "apb2ape" for the corresponding
|
||||
'clocks' entries.
|
||||
- power-domains: Must contain a phandle that points to the audio powergate
|
||||
(namely 'aud') for Tegra210.
|
||||
- #address-cells: The number of cells used to represent physical base addresses
|
||||
in the aconnect address space. Should be 1.
|
||||
- #size-cells: The number of cells used to represent the size of an address
|
||||
range in the aconnect address space. Should be 1.
|
||||
- ranges: Mapping of the aconnect address space to the CPU address space.
|
||||
|
||||
All devices accessed via the ACONNNECT are described by child-nodes.
|
||||
|
||||
Example:
|
||||
|
||||
aconnect@702c0000 {
|
||||
compatible = "nvidia,tegra210-aconnect";
|
||||
clocks = <&tegra_car TEGRA210_CLK_APE>,
|
||||
<&tegra_car TEGRA210_CLK_APB2APE>;
|
||||
clock-names = "ape", "apb2ape";
|
||||
power-domains = <&pd_audio>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x702c0000 0x0 0x702c0000 0x00040000>;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
child1 {
|
||||
...
|
||||
};
|
||||
|
||||
child2 {
|
||||
...
|
||||
};
|
||||
};
|
138
Bindings/bus/qcom,ebi2.txt
Normal file
138
Bindings/bus/qcom,ebi2.txt
Normal file
@ -0,0 +1,138 @@
|
||||
Qualcomm External Bus Interface 2 (EBI2)
|
||||
|
||||
The EBI2 contains two peripheral blocks: XMEM and LCDC. The XMEM handles any
|
||||
external memory (such as NAND or other memory-mapped peripherals) whereas
|
||||
LCDC handles LCD displays.
|
||||
|
||||
As it says it connects devices to an external bus interface, meaning address
|
||||
lines (up to 9 address lines so can only address 1KiB external memory space),
|
||||
data lines (16 bits), OE (output enable), ADV (address valid, used on some
|
||||
NOR flash memories), WE (write enable). This on top of 6 different chip selects
|
||||
(CS0 thru CS5) so that in theory 6 different devices can be connected.
|
||||
|
||||
Apparently this bus is clocked at 64MHz. It has dedicated pins on the package
|
||||
and the bus can only come out on these pins, however if some of the pins are
|
||||
unused they can be left unconnected or remuxed to be used as GPIO or in some
|
||||
cases other orthogonal functions as well.
|
||||
|
||||
Also CS1 and CS2 has -A and -B signals. Why they have that is unclear to me.
|
||||
|
||||
The chip selects have the following memory range assignments. This region of
|
||||
memory is referred to as "Chip Peripheral SS FPB0" and is 168MB big.
|
||||
|
||||
Chip Select Physical address base
|
||||
CS0 GPIO134 0x1a800000-0x1b000000 (8MB)
|
||||
CS1 GPIO39 (A) / GPIO123 (B) 0x1b000000-0x1b800000 (8MB)
|
||||
CS2 GPIO40 (A) / GPIO124 (B) 0x1b800000-0x1c000000 (8MB)
|
||||
CS3 GPIO133 0x1d000000-0x25000000 (128 MB)
|
||||
CS4 GPIO132 0x1c800000-0x1d000000 (8MB)
|
||||
CS5 GPIO131 0x1c000000-0x1c800000 (8MB)
|
||||
|
||||
The APQ8060 Qualcomm Application Processor User Guide, 80-N7150-14 Rev. A,
|
||||
August 6, 2012 contains some incomplete documentation of the EBI2.
|
||||
|
||||
FIXME: the manual mentions "write precharge cycles" and "precharge cycles".
|
||||
We have not been able to figure out which bit fields these correspond to
|
||||
in the hardware, or what valid values exist. The current hypothesis is that
|
||||
this is something just used on the FAST chip selects and that the SLOW
|
||||
chip selects are understood fully. There is also a "byte device enable"
|
||||
flag somewhere for 8bit memories.
|
||||
|
||||
FIXME: The chipselects have SLOW and FAST configuration registers. It's a bit
|
||||
unclear what this means, if they are mutually exclusive or can be used
|
||||
together, or if some chip selects are hardwired to be FAST and others are SLOW
|
||||
by design.
|
||||
|
||||
The XMEM registers are totally undocumented but could be partially decoded
|
||||
because the Cypress AN49576 Antioch Westbridge apparently has suspiciously
|
||||
similar register layout, see: http://www.cypress.com/file/105771/download
|
||||
|
||||
Required properties:
|
||||
- compatible: should be one of:
|
||||
"qcom,msm8660-ebi2"
|
||||
"qcom,apq8060-ebi2"
|
||||
- #address-cells: shoule be <2>: the first cell is the chipselect,
|
||||
the second cell is the offset inside the memory range
|
||||
- #size-cells: should be <1>
|
||||
- ranges: should be set to:
|
||||
ranges = <0 0x0 0x1a800000 0x00800000>,
|
||||
<1 0x0 0x1b000000 0x00800000>,
|
||||
<2 0x0 0x1b800000 0x00800000>,
|
||||
<3 0x0 0x1d000000 0x08000000>,
|
||||
<4 0x0 0x1c800000 0x00800000>,
|
||||
<5 0x0 0x1c000000 0x00800000>;
|
||||
- reg: two ranges of registers: EBI2 config and XMEM config areas
|
||||
- reg-names: should be "ebi2", "xmem"
|
||||
- clocks: two clocks, EBI_2X and EBI
|
||||
- clock-names: shoule be "ebi2x", "ebi2"
|
||||
|
||||
Optional subnodes:
|
||||
- Nodes inside the EBI2 will be considered device nodes.
|
||||
|
||||
The following optional properties are properties that can be tagged onto
|
||||
any device subnode. We are assuming that there can be only ONE device per
|
||||
chipselect subnode, else the properties will become ambigous.
|
||||
|
||||
Optional properties arrays for SLOW chip selects:
|
||||
- qcom,xmem-recovery-cycles: recovery cycles is the time the memory continues to
|
||||
drive the data bus after OE is de-asserted, in order to avoid contention on
|
||||
the data bus. They are inserted when reading one CS and switching to another
|
||||
CS or read followed by write on the same CS. Valid values 0 thru 15. Minimum
|
||||
value is actually 1, so a value of 0 will still yield 1 recovery cycle.
|
||||
- qcom,xmem-write-hold-cycles: write hold cycles, these are extra cycles
|
||||
inserted after every write minimum 1. The data out is driven from the time
|
||||
WE is asserted until CS is asserted. With a hold of 1 (value = 0), the CS
|
||||
stays active for 1 extra cycle etc. Valid values 0 thru 15.
|
||||
- qcom,xmem-write-delta-cycles: initial latency for write cycles inserted for
|
||||
the first write to a page or burst memory. Valid values 0 thru 255.
|
||||
- qcom,xmem-read-delta-cycles: initial latency for read cycles inserted for the
|
||||
first read to a page or burst memory. Valid values 0 thru 255.
|
||||
- qcom,xmem-write-wait-cycles: number of wait cycles for every write access, 0=1
|
||||
cycle. Valid values 0 thru 15.
|
||||
- qcom,xmem-read-wait-cycles: number of wait cycles for every read access, 0=1
|
||||
cycle. Valid values 0 thru 15.
|
||||
|
||||
Optional properties arrays for FAST chip selects:
|
||||
- qcom,xmem-address-hold-enable: this is a boolean property stating that we
|
||||
shall hold the address for an extra cycle to meet hold time requirements
|
||||
with ADV assertion.
|
||||
- qcom,xmem-adv-to-oe-recovery-cycles: the number of cycles elapsed before an OE
|
||||
assertion, with respect to the cycle where ADV (address valid) is asserted.
|
||||
2 means 2 cycles between ADV and OE. Valid values 0, 1, 2 or 3.
|
||||
- qcom,xmem-read-hold-cycles: the length in cycles of the first segment of a
|
||||
read transfer. For a single read trandfer this will be the time from CS
|
||||
assertion to OE assertion. Valid values 0 thru 15.
|
||||
|
||||
|
||||
Example:
|
||||
|
||||
ebi2@1a100000 {
|
||||
compatible = "qcom,apq8060-ebi2";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x0 0x1a800000 0x00800000>,
|
||||
<1 0x0 0x1b000000 0x00800000>,
|
||||
<2 0x0 0x1b800000 0x00800000>,
|
||||
<3 0x0 0x1d000000 0x08000000>,
|
||||
<4 0x0 0x1c800000 0x00800000>,
|
||||
<5 0x0 0x1c000000 0x00800000>;
|
||||
reg = <0x1a100000 0x1000>, <0x1a110000 0x1000>;
|
||||
reg-names = "ebi2", "xmem";
|
||||
clocks = <&gcc EBI2_2X_CLK>, <&gcc EBI2_CLK>;
|
||||
clock-names = "ebi2x", "ebi2";
|
||||
/* Make sure to set up the pin control for the EBI2 */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&foo_ebi2_pins>;
|
||||
|
||||
foo-ebi2@2,0 {
|
||||
compatible = "foo";
|
||||
reg = <2 0x0 0x100>;
|
||||
(...)
|
||||
qcom,xmem-recovery-cycles = <0>;
|
||||
qcom,xmem-write-hold-cycles = <3>;
|
||||
qcom,xmem-write-delta-cycles = <31>;
|
||||
qcom,xmem-read-delta-cycles = <28>;
|
||||
qcom,xmem-write-wait-cycles = <9>;
|
||||
qcom,xmem-read-wait-cycles = <9>;
|
||||
};
|
||||
};
|
20
Bindings/bus/ti,da850-mstpri.txt
Normal file
20
Bindings/bus/ti,da850-mstpri.txt
Normal file
@ -0,0 +1,20 @@
|
||||
* Device tree bindings for Texas Instruments da8xx master peripheral
|
||||
priority driver
|
||||
|
||||
DA8XX SoCs feature a set of registers allowing to change the priority of all
|
||||
peripherals classified as masters.
|
||||
|
||||
Documentation:
|
||||
OMAP-L138 (DA850) - http://www.ti.com/lit/ug/spruh82c/spruh82c.pdf
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: "ti,da850-mstpri" - for da850 based boards
|
||||
- reg: offset and length of the mstpri registers
|
||||
|
||||
Example for da850-lcdk is shown below.
|
||||
|
||||
mstpri {
|
||||
compatible = "ti,da850-mstpri";
|
||||
reg = <0x14110 0x0c>;
|
||||
};
|
45
Bindings/clock/amlogic,gxbb-aoclkc.txt
Normal file
45
Bindings/clock/amlogic,gxbb-aoclkc.txt
Normal file
@ -0,0 +1,45 @@
|
||||
* Amlogic GXBB AO Clock and Reset Unit
|
||||
|
||||
The Amlogic GXBB AO clock controller generates and supplies clock to various
|
||||
controllers within the Always-On part of the SoC.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: should be "amlogic,gxbb-aoclkc"
|
||||
- reg: physical base address of the clock controller and length of memory
|
||||
mapped region.
|
||||
|
||||
- #clock-cells: should be 1.
|
||||
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume. All available clocks are defined as
|
||||
preprocessor macros in the dt-bindings/clock/gxbb-aoclkc.h header and can be
|
||||
used in device tree sources.
|
||||
|
||||
- #reset-cells: should be 1.
|
||||
|
||||
Each reset is assigned an identifier and client nodes can use this identifier
|
||||
to specify the reset which they consume. All available resets are defined as
|
||||
preprocessor macros in the dt-bindings/reset/gxbb-aoclkc.h header and can be
|
||||
used in device tree sources.
|
||||
|
||||
Example: AO Clock controller node:
|
||||
|
||||
clkc_AO: clock-controller@040 {
|
||||
compatible = "amlogic,gxbb-aoclkc";
|
||||
reg = <0x0 0x040 0x0 0x4>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
Example: UART controller node that consumes the clock and reset generated
|
||||
by the clock controller:
|
||||
|
||||
uart_AO: serial@4c0 {
|
||||
compatible = "amlogic,meson-uart";
|
||||
reg = <0x4c0 0x14>;
|
||||
interrupts = <0 90 1>;
|
||||
clocks = <&clkc_AO CLKID_AO_UART1>;
|
||||
resets = <&clkc_AO RESET_AO_UART1>;
|
||||
status = "disabled";
|
||||
};
|
36
Bindings/clock/amlogic,gxbb-clkc.txt
Normal file
36
Bindings/clock/amlogic,gxbb-clkc.txt
Normal file
@ -0,0 +1,36 @@
|
||||
* Amlogic GXBB Clock and Reset Unit
|
||||
|
||||
The Amlogic GXBB clock controller generates and supplies clock to various
|
||||
controllers within the SoC.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: should be "amlogic,gxbb-clkc"
|
||||
- reg: physical base address of the clock controller and length of memory
|
||||
mapped region.
|
||||
|
||||
- #clock-cells: should be 1.
|
||||
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume. All available clocks are defined as
|
||||
preprocessor macros in the dt-bindings/clock/gxbb-clkc.h header and can be
|
||||
used in device tree sources.
|
||||
|
||||
Example: Clock controller node:
|
||||
|
||||
clkc: clock-controller@c883c000 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "amlogic,gxbb-clkc";
|
||||
reg = <0x0 0xc883c000 0x0 0x3db>;
|
||||
};
|
||||
|
||||
Example: UART controller node that consumes the clock generated by the clock
|
||||
controller:
|
||||
|
||||
uart_AO: serial@c81004c0 {
|
||||
compatible = "amlogic,meson-uart";
|
||||
reg = <0xc81004c0 0x14>;
|
||||
interrupts = <0 90 1>;
|
||||
clocks = <&clkc CLKID_CLK81>;
|
||||
status = "disabled";
|
||||
};
|
@ -5,20 +5,50 @@ Technology (IDT). ARM integrated these oscillators deeply into their
|
||||
reference designs by adding special control registers that manage such
|
||||
oscillators to their system controllers.
|
||||
|
||||
The ARM system controller contains logic to serialize and initialize
|
||||
The various ARM system controllers contain logic to serialize and initialize
|
||||
an ICST clock request after a write to the 32 bit register at an offset
|
||||
into the system controller. Furthermore, to even be able to alter one of
|
||||
these frequencies, the system controller must first be unlocked by
|
||||
writing a special token to another offset in the system controller.
|
||||
|
||||
Some ARM hardware contain special versions of the serial interface that only
|
||||
connects the low 8 bits of the VDW (missing one bit), hardwires RDW to
|
||||
different values and sometimes also hardwire the output divider. They
|
||||
therefore have special compatible strings as per this table (the OD value is
|
||||
the value on the pins, not the resulting output divider):
|
||||
|
||||
Hardware variant: RDW OD VDW
|
||||
|
||||
Integrator/AP 22 1 Bit 8 0, rest variable
|
||||
integratorap-cm
|
||||
|
||||
Integrator/AP 46 3 Bit 8 0, rest variable
|
||||
integratorap-sys
|
||||
|
||||
Integrator/AP 22 or 1 17 or (33 or 25 MHz)
|
||||
integratorap-pci 14 1 14
|
||||
|
||||
Integrator/CP 22 variable Bit 8 0, rest variable
|
||||
integratorcp-cm-core
|
||||
|
||||
Integrator/CP 22 variable Bit 8 0, rest variable
|
||||
integratorcp-cm-mem
|
||||
|
||||
The ICST oscillator must be provided inside a system controller node.
|
||||
|
||||
Required properties:
|
||||
- compatible: must be one of
|
||||
"arm,syscon-icst525"
|
||||
"arm,syscon-icst307"
|
||||
"arm,syscon-icst525-integratorap-cm"
|
||||
"arm,syscon-icst525-integratorap-sys"
|
||||
"arm,syscon-icst525-integratorap-pci"
|
||||
"arm,syscon-icst525-integratorcp-cm-core"
|
||||
"arm,syscon-icst525-integratorcp-cm-mem"
|
||||
- lock-offset: the offset address into the system controller where the
|
||||
unlocking register is located
|
||||
- vco-offset: the offset address into the system controller where the
|
||||
ICST control register is located (even 32 bit address)
|
||||
- compatible: must be one of "arm,syscon-icst525" or "arm,syscon-icst307"
|
||||
- #clock-cells: must be <0>
|
||||
- clocks: parent clock, since the ICST needs a parent clock to derive its
|
||||
frequency from, this attribute is compulsory.
|
||||
|
70
Bindings/clock/armada3700-periph-clock.txt
Normal file
70
Bindings/clock/armada3700-periph-clock.txt
Normal file
@ -0,0 +1,70 @@
|
||||
* Peripheral Clock bindings for Marvell Armada 37xx SoCs
|
||||
|
||||
Marvell Armada 37xx SoCs provide peripheral clocks which are
|
||||
used as clock source for the peripheral of the SoC.
|
||||
|
||||
There are two different blocks associated to north bridge and south
|
||||
bridge.
|
||||
|
||||
The peripheral clock consumer should specify the desired clock by
|
||||
having the clock ID in its "clocks" phandle cell.
|
||||
|
||||
The following is a list of provided IDs for Armada 370 North bridge clocks:
|
||||
ID Clock name Description
|
||||
-----------------------------------
|
||||
0 mmc MMC controller
|
||||
1 sata_host Sata Host
|
||||
2 sec_at Security AT
|
||||
3 sac_dap Security DAP
|
||||
4 tsecm Security Engine
|
||||
5 setm_tmx Serial Embedded Trace Module
|
||||
6 avs Adaptive Voltage Scaling
|
||||
7 sqf SPI
|
||||
8 pwm PWM
|
||||
9 i2c_2 I2C 2
|
||||
10 i2c_1 I2C 1
|
||||
11 ddr_phy DDR PHY
|
||||
12 ddr_fclk DDR F clock
|
||||
13 trace Trace
|
||||
14 counter Counter
|
||||
15 eip97 EIP 97
|
||||
16 cpu CPU
|
||||
|
||||
The following is a list of provided IDs for Armada 370 South bridge clocks:
|
||||
ID Clock name Description
|
||||
-----------------------------------
|
||||
0 gbe-50 50 MHz parent clock for Gigabit Ethernet
|
||||
1 gbe-core parent clock for Gigabit Ethernet core
|
||||
2 gbe-125 125 MHz parent clock for Gigabit Ethernet
|
||||
3 gbe1-50 50 MHz clock for Gigabit Ethernet port 1
|
||||
4 gbe0-50 50 MHz clock for Gigabit Ethernet port 0
|
||||
5 gbe1-125 125 MHz clock for Gigabit Ethernet port 1
|
||||
6 gbe0-125 125 MHz clock for Gigabit Ethernet port 0
|
||||
7 gbe1-core Gigabit Ethernet core port 1
|
||||
8 gbe0-core Gigabit Ethernet core port 0
|
||||
9 gbe-bm Gigabit Ethernet Buffer Manager
|
||||
10 sdio SDIO
|
||||
11 usb32-sub2-sys USB 2 clock
|
||||
12 usb32-ss-sys USB 3 clock
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : shall be "marvell,armada-3700-periph-clock-nb" for the
|
||||
north bridge block, or
|
||||
"marvell,armada-3700-periph-clock-sb" for the south bridge block
|
||||
- reg : must be the register address of North/South Bridge Clock register
|
||||
- #clock-cells : from common clock binding; shall be set to 1
|
||||
|
||||
- clocks : list of the parent clock phandle in the following order:
|
||||
TBG-A P, TBG-B P, TBG-A S, TBG-B S and finally the xtal clock.
|
||||
|
||||
|
||||
Example:
|
||||
|
||||
nb_perih_clk: nb-periph-clk@13000{
|
||||
compatible = "marvell,armada-3700-periph-clock-nb";
|
||||
reg = <0x13000 0x1000>;
|
||||
clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>,
|
||||
<&tbg 3>, <&xtalclk>;
|
||||
#clock-cells = <1>;
|
||||
};
|
27
Bindings/clock/armada3700-tbg-clock.txt
Normal file
27
Bindings/clock/armada3700-tbg-clock.txt
Normal file
@ -0,0 +1,27 @@
|
||||
* Time Base Generator Clock bindings for Marvell Armada 37xx SoCs
|
||||
|
||||
Marvell Armada 37xx SoCs provde Time Base Generator clocks which are
|
||||
used as parent clocks for the peripheral clocks.
|
||||
|
||||
The TBG clock consumer should specify the desired clock by having the
|
||||
clock ID in its "clocks" phandle cell.
|
||||
|
||||
The following is a list of provided IDs and clock names on Armada 3700:
|
||||
0 = TBG A P
|
||||
1 = TBG B P
|
||||
2 = TBG A S
|
||||
3 = TBG B S
|
||||
|
||||
Required properties:
|
||||
- compatible : shall be "marvell,armada-3700-tbg-clock"
|
||||
- reg : must be the register address of North Bridge PLL register
|
||||
- #clock-cells : from common clock binding; shall be set to 1
|
||||
|
||||
Example:
|
||||
|
||||
tbg: tbg@13200 {
|
||||
compatible = "marvell,armada-3700-tbg-clock";
|
||||
reg = <0x13200 0x1000>;
|
||||
clocks = <&xtalclk>;
|
||||
#clock-cells = <1>;
|
||||
};
|
28
Bindings/clock/armada3700-xtal-clock.txt
Normal file
28
Bindings/clock/armada3700-xtal-clock.txt
Normal file
@ -0,0 +1,28 @@
|
||||
* Xtal Clock bindings for Marvell Armada 37xx SoCs
|
||||
|
||||
Marvell Armada 37xx SoCs allow to determine the xtal clock frequencies by
|
||||
reading the gpio latch register.
|
||||
|
||||
This node must be a subnode of the node exposing the register address
|
||||
of the GPIO block where the gpio latch is located.
|
||||
|
||||
Required properties:
|
||||
- compatible : shall be one of the following:
|
||||
"marvell,armada-3700-xtal-clock"
|
||||
- #clock-cells : from common clock binding; shall be set to 0
|
||||
|
||||
Optional properties:
|
||||
- clock-output-names : from common clock binding; allows overwrite default clock
|
||||
output names ("xtal")
|
||||
|
||||
Example:
|
||||
gpio1: gpio@13800 {
|
||||
compatible = "marvell,armada-3700-gpio", "syscon", "simple-mfd";
|
||||
reg = <0x13800 0x1000>;
|
||||
|
||||
xtalclk: xtal-clk {
|
||||
compatible = "marvell,armada-3700-xtal-clock";
|
||||
clock-output-names = "xtal";
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
};
|
@ -6,7 +6,8 @@ This binding uses the common clock binding[1].
|
||||
|
||||
Required properties:
|
||||
- compatible : shall be one of the following:
|
||||
"atmel,at91sam9x5-sckc":
|
||||
"atmel,at91sam9x5-sckc" or
|
||||
"atmel,sama5d4-sckc":
|
||||
at91 SCKC (Slow Clock Controller)
|
||||
This node contains the slow clock definitions.
|
||||
|
||||
|
36
Bindings/clock/brcm,bcm53573-ilp.txt
Normal file
36
Bindings/clock/brcm,bcm53573-ilp.txt
Normal file
@ -0,0 +1,36 @@
|
||||
Broadcom BCM53573 ILP clock
|
||||
===========================
|
||||
|
||||
This binding uses the common clock binding:
|
||||
Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
|
||||
This binding is used for ILP clock (sometimes referred as "slow clock")
|
||||
on Broadcom BCM53573 devices using Cortex-A7 CPU.
|
||||
|
||||
ILP's rate has to be calculated on runtime and it depends on ALP clock
|
||||
which has to be referenced.
|
||||
|
||||
This clock is part of PMU (Power Management Unit), a Broadcom's device
|
||||
handing power-related aspects. Its node must be sub-node of the PMU
|
||||
device.
|
||||
|
||||
Required properties:
|
||||
- compatible: "brcm,bcm53573-ilp"
|
||||
- clocks: has to reference an ALP clock
|
||||
- #clock-cells: should be <0>
|
||||
- clock-output-names: from common clock bindings, should contain clock
|
||||
name
|
||||
|
||||
Example:
|
||||
|
||||
pmu@18012000 {
|
||||
compatible = "simple-mfd", "syscon";
|
||||
reg = <0x18012000 0x00001000>;
|
||||
|
||||
ilp {
|
||||
compatible = "brcm,bcm53573-ilp";
|
||||
clocks = <&alp>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "ilp";
|
||||
};
|
||||
};
|
@ -10,6 +10,8 @@ Required Properties:
|
||||
- "samsung,exynos4210-audss-clock" - controller compatible with all Exynos4 SoCs.
|
||||
- "samsung,exynos5250-audss-clock" - controller compatible with Exynos5250
|
||||
SoCs.
|
||||
- "samsung,exynos5410-audss-clock" - controller compatible with Exynos5410
|
||||
SoCs.
|
||||
- "samsung,exynos5420-audss-clock" - controller compatible with Exynos5420
|
||||
SoCs.
|
||||
- reg: physical base address and length of the controller's register set.
|
||||
@ -91,5 +93,5 @@ i2s0: i2s@03830000 {
|
||||
<&clock_audss EXYNOS_MOUT_AUDSS>,
|
||||
<&clock_audss EXYNOS_MOUT_I2S>;
|
||||
clock-names = "iis", "i2s_opclk0", "i2s_opclk1",
|
||||
"mout_audss", "mout_i2s";
|
||||
"mout_audss", "mout_i2s";
|
||||
};
|
||||
|
@ -1,7 +1,7 @@
|
||||
* Clock bindings for the Cirrus Logic CLPS711X CPUs
|
||||
|
||||
Required properties:
|
||||
- compatible : Shall contain "cirrus,clps711x-clk".
|
||||
- compatible : Shall contain "cirrus,ep7209-clk".
|
||||
- reg : Address of the internal register set.
|
||||
- startup-frequency: Factory set CPU startup frequency in HZ.
|
||||
- #clock-cells : Should be <1>.
|
||||
@ -13,7 +13,7 @@ for the full list of CLPS711X clock IDs.
|
||||
Example:
|
||||
clks: clks@80000000 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "cirrus,ep7312-clk", "cirrus,clps711x-clk";
|
||||
compatible = "cirrus,ep7312-clk", "cirrus,ep7209-clk";
|
||||
reg = <0x80000000 0xc000>;
|
||||
startup-frequency = <73728000>;
|
||||
};
|
||||
|
@ -12,24 +12,29 @@ Required Properties:
|
||||
|
||||
- #clock-cells: should be 1.
|
||||
|
||||
- clocks: should contain an entry specifying the root clock from external
|
||||
oscillator supplied through XXTI or XusbXTI pin. This clock should be
|
||||
defined using standard clock bindings with "fin_pll" clock-output-name.
|
||||
That clock is being passed internally to the 9 PLLs.
|
||||
|
||||
All available clocks are defined as preprocessor macros in
|
||||
dt-bindings/clock/exynos5410.h header and can be used in device
|
||||
tree sources.
|
||||
|
||||
External clock:
|
||||
|
||||
There is clock that is generated outside the SoC. It
|
||||
is expected that it is defined using standard clock bindings
|
||||
with following clock-output-name:
|
||||
|
||||
- "fin_pll" - PLL input clock from XXTI
|
||||
|
||||
Example 1: An example of a clock controller node is listed below.
|
||||
|
||||
fin_pll: xxti {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <24000000>;
|
||||
clock-output-names = "fin_pll";
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
clock: clock-controller@0x10010000 {
|
||||
compatible = "samsung,exynos5410-clock";
|
||||
reg = <0x10010000 0x30000>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&fin_pll>;
|
||||
};
|
||||
|
||||
Example 2: UART controller node that consumes the clock generated by the clock
|
||||
|
@ -79,7 +79,7 @@ Required Properties:
|
||||
Input clocks for fsys clock controller:
|
||||
- oscclk
|
||||
- sclk_ufs_mphy
|
||||
- div_aclk_fsys_200
|
||||
- aclk_fsys_200
|
||||
- sclk_pcie_100_fsys
|
||||
- sclk_ufsunipro_fsys
|
||||
- sclk_mmc2_fsys
|
||||
@ -104,6 +104,10 @@ Required Properties:
|
||||
- sclk_decon_tv_vclk_disp
|
||||
- aclk_disp_333
|
||||
|
||||
Input clocks for audio clock controller:
|
||||
- oscclk
|
||||
- fout_aud_pll
|
||||
|
||||
Input clocks for bus0 clock controller:
|
||||
- aclk_bus0_400
|
||||
|
||||
@ -235,7 +239,7 @@ Example 2: Examples of clock controller nodes are listed below.
|
||||
|
||||
clock-names = "oscclk",
|
||||
"sclk_ufs_mphy",
|
||||
"div_aclk_fsys_200",
|
||||
"aclk_fsys_200",
|
||||
"sclk_pcie_100_fsys",
|
||||
"sclk_ufsunipro_fsys",
|
||||
"sclk_mmc2_fsys",
|
||||
@ -245,7 +249,7 @@ Example 2: Examples of clock controller nodes are listed below.
|
||||
"sclk_usbdrd30_fsys";
|
||||
clocks = <&xxti>,
|
||||
<&cmu_cpif CLK_SCLK_UFS_MPHY>,
|
||||
<&cmu_top CLK_DIV_ACLK_FSYS_200>,
|
||||
<&cmu_top CLK_ACLK_FSYS_200>,
|
||||
<&cmu_top CLK_SCLK_PCIE_100_FSYS>,
|
||||
<&cmu_top CLK_SCLK_UFSUNIPRO_FSYS>,
|
||||
<&cmu_top CLK_SCLK_MMC2_FSYS>,
|
||||
@ -297,6 +301,9 @@ Example 2: Examples of clock controller nodes are listed below.
|
||||
compatible = "samsung,exynos5433-cmu-aud";
|
||||
reg = <0x114c0000 0x0b04>;
|
||||
#clock-cells = <1>;
|
||||
|
||||
clock-names = "oscclk", "fout_aud_pll";
|
||||
clocks = <&xxti>, <&cmu_top CLK_FOUT_AUD_PLL>;
|
||||
};
|
||||
|
||||
cmu_bus0: clock-controller@13600000 {
|
||||
|
@ -14,6 +14,10 @@ Required properties:
|
||||
Optional properties:
|
||||
- clock-output-names : From common clock binding.
|
||||
|
||||
Some clocks that require special treatments are also handled by that
|
||||
driver, with the compatibles:
|
||||
- allwinner,sun4i-a10-pll3-2x-clk
|
||||
|
||||
Example:
|
||||
clock {
|
||||
compatible = "fixed-factor-clock";
|
||||
|
50
Bindings/clock/hisi-crg.txt
Normal file
50
Bindings/clock/hisi-crg.txt
Normal file
@ -0,0 +1,50 @@
|
||||
* HiSilicon Clock and Reset Generator(CRG)
|
||||
|
||||
The CRG module provides clock and reset signals to various
|
||||
modules within the SoC.
|
||||
|
||||
This binding uses the following bindings:
|
||||
Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
Documentation/devicetree/bindings/reset/reset.txt
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: should be one of the following.
|
||||
- "hisilicon,hi3516cv300-crg"
|
||||
- "hisilicon,hi3516cv300-sysctrl"
|
||||
- "hisilicon,hi3519-crg"
|
||||
- "hisilicon,hi3798cv200-crg"
|
||||
- "hisilicon,hi3798cv200-sysctrl"
|
||||
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
|
||||
- #clock-cells: should be 1.
|
||||
|
||||
Each clock is assigned an identifier and client nodes use this identifier
|
||||
to specify the clock which they consume.
|
||||
|
||||
All these identifier could be found in <dt-bindings/clock/hi3519-clock.h>.
|
||||
|
||||
- #reset-cells: should be 2.
|
||||
|
||||
A reset signal can be controlled by writing a bit register in the CRG module.
|
||||
The reset specifier consists of two cells. The first cell represents the
|
||||
register offset relative to the base address. The second cell represents the
|
||||
bit index in the register.
|
||||
|
||||
Example: CRG nodes
|
||||
CRG: clock-reset-controller@12010000 {
|
||||
compatible = "hisilicon,hi3519-crg";
|
||||
reg = <0x12010000 0x10000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <2>;
|
||||
};
|
||||
|
||||
Example: consumer nodes
|
||||
i2c0: i2c@12110000 {
|
||||
compatible = "hisilicon,hi3519-i2c";
|
||||
reg = <0x12110000 0x1000>;
|
||||
clocks = <&CRG HI3519_I2C0_RST>;
|
||||
resets = <&CRG 0xe4 0>;
|
||||
};
|
@ -77,7 +77,7 @@ Examples:
|
||||
clks: ccm@53f80000{
|
||||
compatible = "fsl,imx31-ccm";
|
||||
reg = <0x53f80000 0x4000>;
|
||||
interrupts = <0 31 0x04 0 53 0x04>;
|
||||
interrupts = <31>, <53>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
|
@ -1,10 +1,24 @@
|
||||
Binding for Maxim MAX77686 32k clock generator block
|
||||
Binding for Maxim MAX77686/MAX77802/MAX77620 32k clock generator block
|
||||
|
||||
This is a part of device tree bindings of MAX77686 multi-function device.
|
||||
More information can be found in bindings/mfd/max77686.txt file.
|
||||
This is a part of device tree bindings of MAX77686/MAX77802/MAX77620
|
||||
multi-function device. More information can be found in MFD DT binding
|
||||
doc as follows:
|
||||
bindings/mfd/max77686.txt for MAX77686 and
|
||||
bindings/mfd/max77802.txt for MAX77802 and
|
||||
bindings/mfd/max77620.txt for MAX77620.
|
||||
|
||||
The MAX77686 contains three 32.768khz clock outputs that can be controlled
|
||||
(gated/ungated) over I2C.
|
||||
(gated/ungated) over I2C. Clocks are defined as preprocessor macros in
|
||||
dt-bindings/clock/maxim,max77686.h.
|
||||
|
||||
|
||||
The MAX77802 contains two 32.768khz clock outputs that can be controlled
|
||||
(gated/ungated) over I2C. Clocks are defined as preprocessor macros in
|
||||
dt-bindings/clock/maxim,max77802.h.
|
||||
|
||||
The MAX77686 contains one 32.768khz clock outputs that can be controlled
|
||||
(gated/ungated) over I2C. Clocks are defined as preprocessor macros in
|
||||
dt-bindings/clock/maxim,max77620.h.
|
||||
|
||||
Following properties should be presend in main device node of the MFD chip.
|
||||
|
||||
@ -17,30 +31,84 @@ Optional properties:
|
||||
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume. Following indices are allowed:
|
||||
- 0: 32khz_ap clock,
|
||||
- 1: 32khz_cp clock,
|
||||
- 2: 32khz_pmic clock.
|
||||
- 0: 32khz_ap clock (max77686, max77802), 32khz_out0 (max77620)
|
||||
- 1: 32khz_cp clock (max77686, max77802),
|
||||
- 2: 32khz_pmic clock (max77686).
|
||||
|
||||
Clocks are defined as preprocessor macros in dt-bindings/clock/maxim,max77686.h
|
||||
header and can be used in device tree sources.
|
||||
Clocks are defined as preprocessor macros in above dt-binding header for
|
||||
respective chips.
|
||||
|
||||
Example: Node of the MFD chip
|
||||
Example:
|
||||
|
||||
max77686: max77686@09 {
|
||||
compatible = "maxim,max77686";
|
||||
interrupt-parent = <&wakeup_eint>;
|
||||
interrupts = <26 0>;
|
||||
reg = <0x09>;
|
||||
#clock-cells = <1>;
|
||||
1. With MAX77686:
|
||||
|
||||
/* ... */
|
||||
};
|
||||
#include <dt-bindings/clock/maxim,max77686.h>
|
||||
/* ... */
|
||||
|
||||
Example: Clock consumer node
|
||||
Node of the MFD chip
|
||||
max77686: max77686@09 {
|
||||
compatible = "maxim,max77686";
|
||||
interrupt-parent = <&wakeup_eint>;
|
||||
interrupts = <26 0>;
|
||||
reg = <0x09>;
|
||||
#clock-cells = <1>;
|
||||
|
||||
foo@0 {
|
||||
compatible = "bar,foo";
|
||||
/* ... */
|
||||
clock-names = "my-clock";
|
||||
clocks = <&max77686 MAX77686_CLK_PMIC>;
|
||||
};
|
||||
/* ... */
|
||||
};
|
||||
|
||||
Clock consumer node
|
||||
|
||||
foo@0 {
|
||||
compatible = "bar,foo";
|
||||
/* ... */
|
||||
clock-names = "my-clock";
|
||||
clocks = <&max77686 MAX77686_CLK_PMIC>;
|
||||
};
|
||||
|
||||
2. With MAX77802:
|
||||
|
||||
#include <dt-bindings/clock/maxim,max77802.h>
|
||||
/* ... */
|
||||
|
||||
Node of the MFD chip
|
||||
max77802: max77802@09 {
|
||||
compatible = "maxim,max77802";
|
||||
interrupt-parent = <&wakeup_eint>;
|
||||
interrupts = <26 0>;
|
||||
reg = <0x09>;
|
||||
#clock-cells = <1>;
|
||||
|
||||
/* ... */
|
||||
};
|
||||
|
||||
Clock consumer node
|
||||
|
||||
foo@0 {
|
||||
compatible = "bar,foo";
|
||||
/* ... */
|
||||
clock-names = "my-clock";
|
||||
clocks = <&max77802 MAX77802_CLK_32K_AP>;
|
||||
};
|
||||
|
||||
|
||||
3. With MAX77620:
|
||||
|
||||
#include <dt-bindings/clock/maxim,max77620.h>
|
||||
/* ... */
|
||||
|
||||
Node of the MFD chip
|
||||
max77620: max77620@3c {
|
||||
compatible = "maxim,max77620";
|
||||
reg = <0x3c>;
|
||||
#clock-cells = <1>;
|
||||
/* ... */
|
||||
};
|
||||
|
||||
Clock consumer node
|
||||
|
||||
foo@0 {
|
||||
compatible = "bar,foo";
|
||||
/* ... */
|
||||
clock-names = "my-clock";
|
||||
clocks = <&max77620 MAX77620_CLK_32K_OUT0>;
|
||||
};
|
||||
|
@ -52,6 +52,7 @@ Required properties:
|
||||
"marvell,dove-core-clock" - for Dove SoC core clocks
|
||||
"marvell,kirkwood-core-clock" - for Kirkwood SoC (except mv88f6180)
|
||||
"marvell,mv88f6180-core-clock" - for Kirkwood MV88f6180 SoC
|
||||
"marvell,mv88f5181-core-clock" - for Orion MV88F5181 SoC
|
||||
"marvell,mv88f5182-core-clock" - for Orion MV88F5182 SoC
|
||||
"marvell,mv88f5281-core-clock" - for Orion MV88F5281 SoC
|
||||
"marvell,mv88f6183-core-clock" - for Orion MV88F6183 SoC
|
||||
|
@ -86,6 +86,8 @@ ID Clock Peripheral
|
||||
7 pex3 PCIe 3
|
||||
8 pex0 PCIe 0
|
||||
9 usb3h0 USB3 Host 0
|
||||
10 usb3h1 USB3 Host 1
|
||||
15 sata0 SATA 0
|
||||
17 sdio SDIO
|
||||
22 xor0 XOR 0
|
||||
28 xor1 XOR 1
|
||||
|
@ -5,22 +5,15 @@ Please also refer to clock-bindings.txt in this directory for common clock
|
||||
bindings usage.
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "oxsemi,ox810se-stdclk"
|
||||
- compatible: For OX810SE, should be "oxsemi,ox810se-stdclk"
|
||||
For OX820, should be "oxsemi,ox820-stdclk"
|
||||
- #clock-cells: 1, see below
|
||||
|
||||
Parent node should have the following properties :
|
||||
- compatible: Should be "oxsemi,ox810se-sys-ctrl", "syscon", "simple-mfd"
|
||||
|
||||
For OX810SE, the clock indices are :
|
||||
- 0: LEON
|
||||
- 1: DMA_SGDMA
|
||||
- 2: CIPHER
|
||||
- 3: SATA
|
||||
- 4: AUDIO
|
||||
- 5: USBMPH
|
||||
- 6: ETHA
|
||||
- 7: PCIA
|
||||
- 8: NAND
|
||||
- compatible: For OX810SE, should be
|
||||
"oxsemi,ox810se-sys-ctrl", "syscon", "simple-mfd"
|
||||
For OX820, should be
|
||||
"oxsemi,ox820-sys-ctrl", "syscon", "simple-mfd"
|
||||
|
||||
example:
|
||||
|
||||
|
@ -14,7 +14,9 @@ Required properties :
|
||||
"qcom,gcc-msm8974"
|
||||
"qcom,gcc-msm8974pro"
|
||||
"qcom,gcc-msm8974pro-ac"
|
||||
"qcom,gcc-msm8994"
|
||||
"qcom,gcc-msm8996"
|
||||
"qcom,gcc-mdm9615"
|
||||
|
||||
- reg : shall contain base register location and length
|
||||
- #clock-cells : shall contain 1
|
||||
@ -22,6 +24,11 @@ Required properties :
|
||||
|
||||
Optional properties :
|
||||
- #power-domain-cells : shall contain 1
|
||||
- Qualcomm TSENS (thermal sensor device) on some devices can
|
||||
be part of GCC and hence the TSENS properties can also be
|
||||
part of the GCC/clock-controller node.
|
||||
For more details on the TSENS properties please refer
|
||||
Documentation/devicetree/bindings/thermal/qcom-tsens.txt
|
||||
|
||||
Example:
|
||||
clock-controller@900000 {
|
||||
@ -31,3 +38,14 @@ Example:
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
Example of GCC with TSENS properties:
|
||||
clock-controller@900000 {
|
||||
compatible = "qcom,gcc-apq8064";
|
||||
reg = <0x00900000 0x4000>;
|
||||
nvmem-cells = <&tsens_calib>, <&tsens_backup>;
|
||||
nvmem-cell-names = "calib", "calib_backup";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#thermal-sensor-cells = <1>;
|
||||
};
|
||||
|
@ -7,6 +7,7 @@ Required properties :
|
||||
"qcom,lcc-msm8960"
|
||||
"qcom,lcc-apq8064"
|
||||
"qcom,lcc-ipq8064"
|
||||
"qcom,lcc-mdm9615"
|
||||
|
||||
- reg : shall contain base register location and length
|
||||
- #clock-cells : shall contain 1
|
||||
|
37
Bindings/clock/qcom,rpmcc.txt
Normal file
37
Bindings/clock/qcom,rpmcc.txt
Normal file
@ -0,0 +1,37 @@
|
||||
Qualcomm RPM Clock Controller Binding
|
||||
------------------------------------------------
|
||||
The RPM is a dedicated hardware engine for managing the shared
|
||||
SoC resources in order to keep the lowest power profile. It
|
||||
communicates with other hardware subsystems via shared memory
|
||||
and accepts clock requests, aggregates the requests and turns
|
||||
the clocks on/off or scales them on demand.
|
||||
|
||||
Required properties :
|
||||
- compatible : shall contain only one of the following. The generic
|
||||
compatible "qcom,rpmcc" should be also included.
|
||||
|
||||
"qcom,rpmcc-msm8916", "qcom,rpmcc"
|
||||
"qcom,rpmcc-apq8064", "qcom,rpmcc"
|
||||
|
||||
- #clock-cells : shall contain 1
|
||||
|
||||
Example:
|
||||
smd {
|
||||
compatible = "qcom,smd";
|
||||
|
||||
rpm {
|
||||
interrupts = <0 168 1>;
|
||||
qcom,ipc = <&apcs 8 0>;
|
||||
qcom,smd-edge = <15>;
|
||||
|
||||
rpm_requests {
|
||||
compatible = "qcom,rpm-msm8916";
|
||||
qcom,smd-channels = "rpm_requests";
|
||||
|
||||
rpmcc: clock-controller {
|
||||
compatible = "qcom,rpmcc-msm8916", "qcom,rpmcc";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
@ -32,6 +32,9 @@ Required properties:
|
||||
* "fsl,b4420-clockgen"
|
||||
* "fsl,b4860-clockgen"
|
||||
* "fsl,ls1021a-clockgen"
|
||||
* "fsl,ls1043a-clockgen"
|
||||
* "fsl,ls1046a-clockgen"
|
||||
* "fsl,ls2080a-clockgen"
|
||||
Chassis-version clock strings include:
|
||||
* "fsl,qoriq-clockgen-1.0": for chassis 1.0 clocks
|
||||
* "fsl,qoriq-clockgen-2.0": for chassis 2.0 clocks
|
||||
|
@ -13,7 +13,10 @@ They provide the following functionalities:
|
||||
|
||||
Required Properties:
|
||||
- compatible: Must be one of:
|
||||
- "renesas,r8a7795-cpg-mssr" for the r8a7795 SoC
|
||||
- "renesas,r8a7743-cpg-mssr" for the r8a7743 SoC (RZ/G1M)
|
||||
- "renesas,r8a7745-cpg-mssr" for the r8a7745 SoC (RZ/G1E)
|
||||
- "renesas,r8a7795-cpg-mssr" for the r8a7795 SoC (R-Car H3)
|
||||
- "renesas,r8a7796-cpg-mssr" for the r8a7796 SoC (R-Car M3-W)
|
||||
|
||||
- reg: Base address and length of the memory resource used by the CPG/MSSR
|
||||
block
|
||||
@ -21,8 +24,9 @@ Required Properties:
|
||||
- clocks: References to external parent clocks, one entry for each entry in
|
||||
clock-names
|
||||
- clock-names: List of external parent clock names. Valid names are:
|
||||
- "extal" (r8a7795)
|
||||
- "extalr" (r8a7795)
|
||||
- "extal" (r8a7743, r8a7745, r8a7795, r8a7796)
|
||||
- "extalr" (r8a7795, r8a7796)
|
||||
- "usb_extal" (r8a7743, r8a7745)
|
||||
|
||||
- #clock-cells: Must be 2
|
||||
- For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
|
||||
|
@ -17,6 +17,7 @@ Required Properties:
|
||||
- "renesas,r8a7779-mstp-clocks" for R8A7779 (R-Car H1) MSTP gate clocks
|
||||
- "renesas,r8a7790-mstp-clocks" for R8A7790 (R-Car H2) MSTP gate clocks
|
||||
- "renesas,r8a7791-mstp-clocks" for R8A7791 (R-Car M2-W) MSTP gate clocks
|
||||
- "renesas,r8a7792-mstp-clocks" for R8A7792 (R-Car V2H) MSTP gate clocks
|
||||
- "renesas,r8a7793-mstp-clocks" for R8A7793 (R-Car M2-N) MSTP gate clocks
|
||||
- "renesas,r8a7794-mstp-clocks" for R8A7794 (R-Car E2) MSTP gate clocks
|
||||
- "renesas,sh73a0-mstp-clocks" for SH73A0 (SH-MobileAG5) MSTP gate clocks
|
||||
|
@ -10,6 +10,7 @@ Required Properties:
|
||||
- compatible: Must be one of
|
||||
- "renesas,r8a7790-cpg-clocks" for the r8a7790 CPG
|
||||
- "renesas,r8a7791-cpg-clocks" for the r8a7791 CPG
|
||||
- "renesas,r8a7792-cpg-clocks" for the r8a7792 CPG
|
||||
- "renesas,r8a7793-cpg-clocks" for the r8a7793 CPG
|
||||
- "renesas,r8a7794-cpg-clocks" for the r8a7794 CPG
|
||||
and "renesas,rcar-gen2-cpg-clocks" as a fallback.
|
||||
|
59
Bindings/clock/rockchip,rk1108-cru.txt
Normal file
59
Bindings/clock/rockchip,rk1108-cru.txt
Normal file
@ -0,0 +1,59 @@
|
||||
* Rockchip RK1108 Clock and Reset Unit
|
||||
|
||||
The RK1108 clock controller generates and supplies clock to various
|
||||
controllers within the SoC and also implements a reset controller for SoC
|
||||
peripherals.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: should be "rockchip,rk1108-cru"
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
- #clock-cells: should be 1.
|
||||
- #reset-cells: should be 1.
|
||||
|
||||
Optional Properties:
|
||||
|
||||
- rockchip,grf: phandle to the syscon managing the "general register files"
|
||||
If missing pll rates are not changeable, due to the missing pll lock status.
|
||||
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume. All available clocks are defined as
|
||||
preprocessor macros in the dt-bindings/clock/rk1108-cru.h headers and can be
|
||||
used in device tree sources. Similar macros exist for the reset sources in
|
||||
these files.
|
||||
|
||||
External clocks:
|
||||
|
||||
There are several clocks that are generated outside the SoC. It is expected
|
||||
that they are defined using standard clock bindings with following
|
||||
clock-output-names:
|
||||
- "xin24m" - crystal input - required,
|
||||
- "ext_vip" - external VIP clock - optional
|
||||
- "ext_i2s" - external I2S clock - optional
|
||||
- "ext_gmac" - external GMAC clock - optional
|
||||
- "hdmiphy" - external clock input derived from HDMI PHY - optional
|
||||
- "usbphy" - external clock input derived from USB PHY - optional
|
||||
|
||||
Example: Clock controller node:
|
||||
|
||||
cru: cru@20200000 {
|
||||
compatible = "rockchip,rk1108-cru";
|
||||
reg = <0x20200000 0x1000>;
|
||||
rockchip,grf = <&grf>;
|
||||
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
Example: UART controller node that consumes the clock generated by the clock
|
||||
controller:
|
||||
|
||||
uart0: serial@10230000 {
|
||||
compatible = "rockchip,rk1108-uart", "snps,dw-apb-uart";
|
||||
reg = <0x10230000 0x100>;
|
||||
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clocks = <&cru SCLK_UART0>;
|
||||
};
|
@ -1,16 +1,18 @@
|
||||
STMicroelectronics STM32 Reset and Clock Controller
|
||||
===================================================
|
||||
|
||||
The RCC IP is both a reset and a clock controller. This documentation only
|
||||
describes the clock part.
|
||||
The RCC IP is both a reset and a clock controller.
|
||||
|
||||
Please also refer to clock-bindings.txt in this directory for common clock
|
||||
controller binding usage.
|
||||
Please refer to clock-bindings.txt for common clock controller binding usage.
|
||||
Please also refer to reset.txt for common reset controller binding usage.
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "st,stm32f42xx-rcc"
|
||||
- compatible: Should be:
|
||||
"st,stm32f42xx-rcc"
|
||||
"st,stm32f469-rcc"
|
||||
- reg: should be register base and length as documented in the
|
||||
datasheet
|
||||
- #reset-cells: 1, see below
|
||||
- #clock-cells: 2, device nodes should specify the clock in their "clocks"
|
||||
property, containing a phandle to the clock device node, an index selecting
|
||||
between gated clocks and other clocks and an index specifying the clock to
|
||||
@ -19,6 +21,7 @@ Required properties:
|
||||
Example:
|
||||
|
||||
rcc: rcc@40023800 {
|
||||
#reset-cells = <1>;
|
||||
#clock-cells = <2>
|
||||
compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
|
||||
reg = <0x40023800 0x400>;
|
||||
@ -35,16 +38,23 @@ from the first RCC clock enable register (RCC_AHB1ENR, address offset 0x30).
|
||||
It is calculated as: index = register_offset / 4 * 32 + bit_offset.
|
||||
Where bit_offset is the bit offset within the register (LSB is 0, MSB is 31).
|
||||
|
||||
To simplify the usage and to share bit definition with the reset and clock
|
||||
drivers of the RCC IP, macros are available to generate the index in
|
||||
human-readble format.
|
||||
|
||||
For STM32F4 series, the macro are available here:
|
||||
- include/dt-bindings/mfd/stm32f4-rcc.h
|
||||
|
||||
Example:
|
||||
|
||||
/* Gated clock, AHB1 bit 0 (GPIOA) */
|
||||
... {
|
||||
clocks = <&rcc 0 0>
|
||||
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>
|
||||
};
|
||||
|
||||
/* Gated clock, AHB2 bit 4 (CRYP) */
|
||||
... {
|
||||
clocks = <&rcc 0 36>
|
||||
clocks = <&rcc 0 STM32F4_AHB2_CLOCK(CRYP)>
|
||||
};
|
||||
|
||||
Specifying other clocks
|
||||
@ -61,5 +71,25 @@ Example:
|
||||
|
||||
/* Misc clock, FCLK */
|
||||
... {
|
||||
clocks = <&rcc 1 1>
|
||||
clocks = <&rcc 1 STM32F4_APB1_CLOCK(TIM2)>
|
||||
};
|
||||
|
||||
|
||||
Specifying softreset control of devices
|
||||
=======================================
|
||||
|
||||
Device nodes should specify the reset channel required in their "resets"
|
||||
property, containing a phandle to the reset device node and an index specifying
|
||||
which channel to use.
|
||||
The index is the bit number within the RCC registers bank, starting from RCC
|
||||
base address.
|
||||
It is calculated as: index = register_offset / 4 * 32 + bit_offset.
|
||||
Where bit_offset is the bit offset within the register.
|
||||
For example, for CRC reset:
|
||||
crc = AHB1RSTR_offset / 4 * 32 + CRCRST_bit_offset = 0x10 / 4 * 32 + 12 = 140
|
||||
|
||||
example:
|
||||
|
||||
timer2 {
|
||||
resets = <&rcc STM32F4_APB1_RESET(TIM2)>;
|
||||
};
|
||||
|
@ -10,14 +10,7 @@ This binding uses the common clock binding[1].
|
||||
Required properties:
|
||||
|
||||
- compatible : shall be:
|
||||
"st,stih416-clkgenc-vcc-hd", "st,clkgen-mux"
|
||||
"st,stih416-clkgenf-vcc-fvdp", "st,clkgen-mux"
|
||||
"st,stih416-clkgenf-vcc-hva", "st,clkgen-mux"
|
||||
"st,stih416-clkgenf-vcc-hd", "st,clkgen-mux"
|
||||
"st,stih416-clkgenf-vcc-sd", "st,clkgen-mux"
|
||||
"st,stih415-clkgen-a9-mux", "st,clkgen-mux"
|
||||
"st,stih416-clkgen-a9-mux", "st,clkgen-mux"
|
||||
"st,stih407-clkgen-a9-mux", "st,clkgen-mux"
|
||||
"st,stih407-clkgen-a9-mux"
|
||||
|
||||
- #clock-cells : from common clock binding; shall be set to 0.
|
||||
|
||||
@ -27,10 +20,13 @@ Required properties:
|
||||
|
||||
Example:
|
||||
|
||||
clk_m_hva: clk-m-hva@fd690868 {
|
||||
clk_m_a9: clk-m-a9@92b0000 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "st,stih416-clkgenf-vcc-hva", "st,clkgen-mux";
|
||||
reg = <0xfd690868 4>;
|
||||
compatible = "st,stih407-clkgen-a9-mux";
|
||||
reg = <0x92b0000 0x10000>;
|
||||
|
||||
clocks = <&clockgen_f 1>, <&clk_m_a1_div0 3>;
|
||||
clocks = <&clockgen_a9_pll 0>,
|
||||
<&clockgen_a9_pll 0>,
|
||||
<&clk_s_c0_flexgen 13>,
|
||||
<&clk_m_a9_ext2f_div2>;
|
||||
};
|
||||
|
@ -9,24 +9,10 @@ Base address is located to the parent node. See clock binding[2]
|
||||
Required properties:
|
||||
|
||||
- compatible : shall be:
|
||||
"st,clkgena-prediv-c65", "st,clkgena-prediv"
|
||||
"st,clkgena-prediv-c32", "st,clkgena-prediv"
|
||||
|
||||
"st,clkgena-plls-c65"
|
||||
"st,plls-c32-a1x-0", "st,clkgen-plls-c32"
|
||||
"st,plls-c32-a1x-1", "st,clkgen-plls-c32"
|
||||
"st,stih415-plls-c32-a9", "st,clkgen-plls-c32"
|
||||
"st,stih415-plls-c32-ddr", "st,clkgen-plls-c32"
|
||||
"st,stih416-plls-c32-a9", "st,clkgen-plls-c32"
|
||||
"st,stih416-plls-c32-ddr", "st,clkgen-plls-c32"
|
||||
"st,stih407-plls-c32-a0", "st,clkgen-plls-c32"
|
||||
"st,stih407-plls-c32-a9", "st,clkgen-plls-c32"
|
||||
"sst,plls-c32-cx_0", "st,clkgen-plls-c32"
|
||||
"sst,plls-c32-cx_1", "st,clkgen-plls-c32"
|
||||
"st,stih418-plls-c28-a9", "st,clkgen-plls-c32"
|
||||
|
||||
"st,stih415-gpu-pll-c32", "st,clkgengpu-pll-c32"
|
||||
"st,stih416-gpu-pll-c32", "st,clkgengpu-pll-c32"
|
||||
"st,clkgen-pll0"
|
||||
"st,clkgen-pll1"
|
||||
"st,stih407-clkgen-plla9"
|
||||
"st,stih418-clkgen-plla9"
|
||||
|
||||
- #clock-cells : From common clock binding; shall be set to 1.
|
||||
|
||||
@ -36,17 +22,16 @@ Required properties:
|
||||
|
||||
Example:
|
||||
|
||||
clockgen-a@fee62000 {
|
||||
reg = <0xfee62000 0xb48>;
|
||||
clockgen-a9@92b0000 {
|
||||
compatible = "st,clkgen-c32";
|
||||
reg = <0x92b0000 0xffff>;
|
||||
|
||||
clk_s_a0_pll: clk-s-a0-pll {
|
||||
clockgen_a9_pll: clockgen-a9-pll {
|
||||
#clock-cells = <1>;
|
||||
compatible = "st,clkgena-plls-c65";
|
||||
compatible = "st,stih407-clkgen-plla9";
|
||||
|
||||
clocks = <&clk_sysin>;
|
||||
|
||||
clock-output-names = "clk-s-a0-pll0-hs",
|
||||
"clk-s-a0-pll0-ls",
|
||||
"clk-s-a0-pll1";
|
||||
clock-output-names = "clockgen-a9-pll-odf";
|
||||
};
|
||||
};
|
||||
|
@ -13,14 +13,6 @@ address is common of all subnode.
|
||||
...
|
||||
};
|
||||
|
||||
prediv_node {
|
||||
...
|
||||
};
|
||||
|
||||
divmux_node {
|
||||
...
|
||||
};
|
||||
|
||||
quadfs_node {
|
||||
...
|
||||
};
|
||||
@ -29,10 +21,6 @@ address is common of all subnode.
|
||||
...
|
||||
};
|
||||
|
||||
vcc_node {
|
||||
...
|
||||
};
|
||||
|
||||
flexgen_node {
|
||||
...
|
||||
};
|
||||
@ -43,11 +31,8 @@ This binding uses the common clock binding[1].
|
||||
Each subnode should use the binding described in [2]..[7]
|
||||
|
||||
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
[2] Documentation/devicetree/bindings/clock/st,clkgen-divmux.txt
|
||||
[3] Documentation/devicetree/bindings/clock/st,clkgen-mux.txt
|
||||
[4] Documentation/devicetree/bindings/clock/st,clkgen-pll.txt
|
||||
[5] Documentation/devicetree/bindings/clock/st,clkgen-prediv.txt
|
||||
[6] Documentation/devicetree/bindings/clock/st,vcc.txt
|
||||
[7] Documentation/devicetree/bindings/clock/st,quadfs.txt
|
||||
[8] Documentation/devicetree/bindings/clock/st,flexgen.txt
|
||||
|
||||
@ -57,44 +42,27 @@ Required properties:
|
||||
|
||||
Example:
|
||||
|
||||
clockgen-a@fee62000 {
|
||||
|
||||
reg = <0xfee62000 0xb48>;
|
||||
clockgen-a@090ff000 {
|
||||
compatible = "st,clkgen-c32";
|
||||
reg = <0x90ff000 0x1000>;
|
||||
|
||||
clk_s_a0_pll: clk-s-a0-pll {
|
||||
#clock-cells = <1>;
|
||||
compatible = "st,clkgena-plls-c65";
|
||||
|
||||
clocks = <&clk-sysin>;
|
||||
|
||||
clock-output-names = "clk-s-a0-pll0-hs",
|
||||
"clk-s-a0-pll0-ls",
|
||||
"clk-s-a0-pll1";
|
||||
};
|
||||
|
||||
clk_s_a0_osc_prediv: clk-s-a0-osc-prediv {
|
||||
#clock-cells = <0>;
|
||||
compatible = "st,clkgena-prediv-c65",
|
||||
"st,clkgena-prediv";
|
||||
compatible = "st,clkgen-pll0";
|
||||
|
||||
clocks = <&clk_sysin>;
|
||||
|
||||
clock-output-names = "clk-s-a0-osc-prediv";
|
||||
clock-output-names = "clk-s-a0-pll-ofd-0";
|
||||
};
|
||||
|
||||
clk_s_a0_hs: clk-s-a0-hs {
|
||||
clk_s_a0_flexgen: clk-s-a0-flexgen {
|
||||
compatible = "st,flexgen";
|
||||
|
||||
#clock-cells = <1>;
|
||||
compatible = "st,clkgena-divmux-c65-hs",
|
||||
"st,clkgena-divmux";
|
||||
|
||||
clocks = <&clk-s_a0_osc_prediv>,
|
||||
<&clk-s_a0_pll 0>, /* pll0 hs */
|
||||
<&clk-s_a0_pll 2>; /* pll1 */
|
||||
clocks = <&clk_s_a0_pll 0>,
|
||||
<&clk_sysin>;
|
||||
|
||||
clock-output-names = "clk-s-fdma-0",
|
||||
"clk-s-fdma-1",
|
||||
""; /* clk-s-jit-sense */
|
||||
/* fourth output unused */
|
||||
clock-output-names = "clk-ic-lmi0";
|
||||
};
|
||||
};
|
||||
|
||||
|
@ -60,6 +60,10 @@ This binding uses the common clock binding[2].
|
||||
Required properties:
|
||||
- compatible : shall be:
|
||||
"st,flexgen"
|
||||
"st,flexgen-audio", "st,flexgen" (enable clock propagation on parent for
|
||||
audio use case)
|
||||
"st,flexgen-video", "st,flexgen" (enable clock propagation on parent
|
||||
and activate synchronous mode)
|
||||
|
||||
- #clock-cells : from common clock binding; shall be set to 1 (multiple clock
|
||||
outputs).
|
||||
|
@ -11,12 +11,8 @@ This binding uses the common clock binding[1].
|
||||
|
||||
Required properties:
|
||||
- compatible : shall be:
|
||||
"st,stih416-quadfs216", "st,quadfs"
|
||||
"st,stih416-quadfs432", "st,quadfs"
|
||||
"st,stih416-quadfs660-E", "st,quadfs"
|
||||
"st,stih416-quadfs660-F", "st,quadfs"
|
||||
"st,stih407-quadfs660-C", "st,quadfs"
|
||||
"st,stih407-quadfs660-D", "st,quadfs"
|
||||
"st,quadfs"
|
||||
"st,quadfs-pll"
|
||||
|
||||
|
||||
- #clock-cells : from common clock binding; shall be set to 1.
|
||||
@ -35,14 +31,15 @@ Required properties:
|
||||
|
||||
Example:
|
||||
|
||||
clockgen_e: clockgen-e@fd3208bc {
|
||||
#clock-cells = <1>;
|
||||
compatible = "st,stih416-quadfs660-E", "st,quadfs";
|
||||
reg = <0xfd3208bc 0xB0>;
|
||||
clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "st,quadfs-pll";
|
||||
reg = <0x9103000 0x1000>;
|
||||
|
||||
clocks = <&clk_sysin>;
|
||||
clock-output-names = "clk-m-pix-mdtp-0",
|
||||
"clk-m-pix-mdtp-1",
|
||||
"clk-m-pix-mdtp-2",
|
||||
"clk-m-mpelpc";
|
||||
};
|
||||
clocks = <&clk_sysin>;
|
||||
|
||||
clock-output-names = "clk-s-c0-fs0-ch0",
|
||||
"clk-s-c0-fs0-ch1",
|
||||
"clk-s-c0-fs0-ch2",
|
||||
"clk-s-c0-fs0-ch3";
|
||||
};
|
||||
|
28
Bindings/clock/sunxi-ccu.txt
Normal file
28
Bindings/clock/sunxi-ccu.txt
Normal file
@ -0,0 +1,28 @@
|
||||
Allwinner Clock Control Unit Binding
|
||||
------------------------------------
|
||||
|
||||
Required properties :
|
||||
- compatible: must contain one of the following compatibles:
|
||||
- "allwinner,sun6i-a31-ccu"
|
||||
- "allwinner,sun8i-a23-ccu"
|
||||
- "allwinner,sun8i-a33-ccu"
|
||||
- "allwinner,sun8i-h3-ccu"
|
||||
- "allwinner,sun50i-a64-ccu"
|
||||
|
||||
- reg: Must contain the registers base address and length
|
||||
- clocks: phandle to the oscillators feeding the CCU. Two are needed:
|
||||
- "hosc": the high frequency oscillator (usually at 24MHz)
|
||||
- "losc": the low frequency oscillator (usually at 32kHz)
|
||||
- clock-names: Must contain the clock names described just above
|
||||
- #clock-cells : must contain 1
|
||||
- #reset-cells : must contain 1
|
||||
|
||||
Example:
|
||||
ccu: clock@01c20000 {
|
||||
compatible = "allwinner,sun8i-h3-ccu";
|
||||
reg = <0x01c20000 0x400>;
|
||||
clocks = <&osc24M>, <&osc32k>;
|
||||
clock-names = "hosc", "losc";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
134
Bindings/clock/uniphier-clock.txt
Normal file
134
Bindings/clock/uniphier-clock.txt
Normal file
@ -0,0 +1,134 @@
|
||||
UniPhier clock controller
|
||||
|
||||
|
||||
System clock
|
||||
------------
|
||||
|
||||
Required properties:
|
||||
- compatible: should be one of the following:
|
||||
"socionext,uniphier-sld3-clock" - for sLD3 SoC.
|
||||
"socionext,uniphier-ld4-clock" - for LD4 SoC.
|
||||
"socionext,uniphier-pro4-clock" - for Pro4 SoC.
|
||||
"socionext,uniphier-sld8-clock" - for sLD8 SoC.
|
||||
"socionext,uniphier-pro5-clock" - for Pro5 SoC.
|
||||
"socionext,uniphier-pxs2-clock" - for PXs2/LD6b SoC.
|
||||
"socionext,uniphier-ld11-clock" - for LD11 SoC.
|
||||
"socionext,uniphier-ld20-clock" - for LD20 SoC.
|
||||
- #clock-cells: should be 1.
|
||||
|
||||
Example:
|
||||
|
||||
sysctrl@61840000 {
|
||||
compatible = "socionext,uniphier-sysctrl",
|
||||
"simple-mfd", "syscon";
|
||||
reg = <0x61840000 0x4000>;
|
||||
|
||||
clock {
|
||||
compatible = "socionext,uniphier-ld11-clock";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
other nodes ...
|
||||
};
|
||||
|
||||
Provided clocks:
|
||||
|
||||
8: ST DMAC
|
||||
12: GIO (Giga bit stream I/O)
|
||||
14: USB3 ch0 host
|
||||
15: USB3 ch1 host
|
||||
16: USB3 ch0 PHY0
|
||||
17: USB3 ch0 PHY1
|
||||
20: USB3 ch1 PHY0
|
||||
21: USB3 ch1 PHY1
|
||||
|
||||
|
||||
Media I/O (MIO) clock, SD clock
|
||||
-------------------------------
|
||||
|
||||
Required properties:
|
||||
- compatible: should be one of the following:
|
||||
"socionext,uniphier-sld3-mio-clock" - for sLD3 SoC.
|
||||
"socionext,uniphier-ld4-mio-clock" - for LD4 SoC.
|
||||
"socionext,uniphier-pro4-mio-clock" - for Pro4 SoC.
|
||||
"socionext,uniphier-sld8-mio-clock" - for sLD8 SoC.
|
||||
"socionext,uniphier-pro5-sd-clock" - for Pro5 SoC.
|
||||
"socionext,uniphier-pxs2-sd-clock" - for PXs2/LD6b SoC.
|
||||
"socionext,uniphier-ld11-mio-clock" - for LD11 SoC.
|
||||
"socionext,uniphier-ld20-sd-clock" - for LD20 SoC.
|
||||
- #clock-cells: should be 1.
|
||||
|
||||
Example:
|
||||
|
||||
mioctrl@59810000 {
|
||||
compatible = "socionext,uniphier-mioctrl",
|
||||
"simple-mfd", "syscon";
|
||||
reg = <0x59810000 0x800>;
|
||||
|
||||
clock {
|
||||
compatible = "socionext,uniphier-ld11-mio-clock";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
other nodes ...
|
||||
};
|
||||
|
||||
Provided clocks:
|
||||
|
||||
0: SD ch0 host
|
||||
1: eMMC host
|
||||
2: SD ch1 host
|
||||
7: MIO DMAC
|
||||
8: USB2 ch0 host
|
||||
9: USB2 ch1 host
|
||||
10: USB2 ch2 host
|
||||
11: USB2 ch3 host
|
||||
12: USB2 ch0 PHY
|
||||
13: USB2 ch1 PHY
|
||||
14: USB2 ch2 PHY
|
||||
15: USB2 ch3 PHY
|
||||
|
||||
|
||||
Peripheral clock
|
||||
----------------
|
||||
|
||||
Required properties:
|
||||
- compatible: should be one of the following:
|
||||
"socionext,uniphier-sld3-peri-clock" - for sLD3 SoC.
|
||||
"socionext,uniphier-ld4-peri-clock" - for LD4 SoC.
|
||||
"socionext,uniphier-pro4-peri-clock" - for Pro4 SoC.
|
||||
"socionext,uniphier-sld8-peri-clock" - for sLD8 SoC.
|
||||
"socionext,uniphier-pro5-peri-clock" - for Pro5 SoC.
|
||||
"socionext,uniphier-pxs2-peri-clock" - for PXs2/LD6b SoC.
|
||||
"socionext,uniphier-ld11-peri-clock" - for LD11 SoC.
|
||||
"socionext,uniphier-ld20-peri-clock" - for LD20 SoC.
|
||||
- #clock-cells: should be 1.
|
||||
|
||||
Example:
|
||||
|
||||
perictrl@59820000 {
|
||||
compatible = "socionext,uniphier-perictrl",
|
||||
"simple-mfd", "syscon";
|
||||
reg = <0x59820000 0x200>;
|
||||
|
||||
clock {
|
||||
compatible = "socionext,uniphier-ld11-peri-clock";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
other nodes ...
|
||||
};
|
||||
|
||||
Provided clocks:
|
||||
|
||||
0: UART ch0
|
||||
1: UART ch1
|
||||
2: UART ch2
|
||||
3: UART ch3
|
||||
4: I2C ch0
|
||||
5: I2C ch1
|
||||
6: I2C ch2
|
||||
7: I2C ch3
|
||||
8: I2C ch4
|
||||
9: I2C ch5
|
||||
10: I2C ch6
|
@ -8,6 +8,7 @@ Required properties:
|
||||
- compatible : shall be one of the following:
|
||||
"apm,xgene-socpll-clock" - for a X-Gene SoC PLL clock
|
||||
"apm,xgene-pcppll-clock" - for a X-Gene PCP PLL clock
|
||||
"apm,xgene-pmd-clock" - for a X-Gene PMD clock
|
||||
"apm,xgene-device-clock" - for a X-Gene device clock
|
||||
"apm,xgene-socpll-v2-clock" - for a X-Gene SoC PLL v2 clock
|
||||
"apm,xgene-pcppll-v2-clock" - for a X-Gene PCP PLL v2 clock
|
||||
@ -22,6 +23,15 @@ Required properties for SoC or PCP PLL clocks:
|
||||
Optional properties for PLL clocks:
|
||||
- clock-names : shall be the name of the PLL. If missing, use the device name.
|
||||
|
||||
Required properties for PMD clocks:
|
||||
- reg : shall be the physical register address for the pmd clock.
|
||||
- clocks : shall be the input parent clock phandle for the clock.
|
||||
- #clock-cells : shall be set to 1.
|
||||
- clock-output-names : shall be the name of the clock referenced by derive
|
||||
clock.
|
||||
Optional properties for PLL clocks:
|
||||
- clock-names : shall be the name of the clock. If missing, use the device name.
|
||||
|
||||
Required properties for device clocks:
|
||||
- reg : shall be a list of address and length pairs describing the CSR
|
||||
reset and/or the divider. Either may be omitted, but at least
|
||||
@ -59,6 +69,14 @@ For example:
|
||||
type = <0>;
|
||||
};
|
||||
|
||||
pmd0clk: pmd0clk@7e200200 {
|
||||
compatible = "apm,xgene-pmd-clock";
|
||||
#clock-cells = <1>;
|
||||
clocks = <&pmdpll 0>;
|
||||
reg = <0x0 0x7e200200 0x0 0x10>;
|
||||
clock-output-names = "pmd0clk";
|
||||
};
|
||||
|
||||
socpll: socpll@17000120 {
|
||||
compatible = "apm,xgene-socpll-clock";
|
||||
#clock-cells = <1>;
|
||||
|
35
Bindings/clock/zx296718-clk.txt
Normal file
35
Bindings/clock/zx296718-clk.txt
Normal file
@ -0,0 +1,35 @@
|
||||
Device Tree Clock bindings for ZTE zx296718
|
||||
|
||||
This binding uses the common clock binding[1].
|
||||
|
||||
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
|
||||
Required properties:
|
||||
- compatible : shall be one of the following:
|
||||
"zte,zx296718-topcrm":
|
||||
zx296718 top clock selection, divider and gating
|
||||
|
||||
"zte,zx296718-lsp0crm" and
|
||||
"zte,zx296718-lsp1crm":
|
||||
zx296718 device level clock selection and gating
|
||||
|
||||
- reg: Address and length of the register set
|
||||
|
||||
The clock consumer should specify the desired clock by having the clock
|
||||
ID in its "clocks" phandle cell. See include/dt-bindings/clock/zx296718-clock.h
|
||||
for the full list of zx296718 clock IDs.
|
||||
|
||||
|
||||
topclk: topcrm@1461000 {
|
||||
compatible = "zte,zx296718-topcrm-clk";
|
||||
reg = <0x01461000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
usbphy0:usb-phy0 {
|
||||
compatible = "zte,zx296718-usb-phy";
|
||||
#phy-cells = <0>;
|
||||
clocks = <&topclk USB20_PHY_CLK>;
|
||||
clock-names = "phyclk";
|
||||
status = "okay";
|
||||
};
|
78
Bindings/cpufreq/brcm,stb-avs-cpu-freq.txt
Normal file
78
Bindings/cpufreq/brcm,stb-avs-cpu-freq.txt
Normal file
@ -0,0 +1,78 @@
|
||||
Broadcom AVS mail box and interrupt register bindings
|
||||
=====================================================
|
||||
|
||||
A total of three DT nodes are required. One node (brcm,avs-cpu-data-mem)
|
||||
references the mailbox register used to communicate with the AVS CPU[1]. The
|
||||
second node (brcm,avs-cpu-l2-intr) is required to trigger an interrupt on
|
||||
the AVS CPU. The interrupt tells the AVS CPU that it needs to process a
|
||||
command sent to it by a driver. Interrupting the AVS CPU is mandatory for
|
||||
commands to be processed.
|
||||
|
||||
The interface also requires a reference to the AVS host interrupt controller,
|
||||
so a driver can react to interrupts generated by the AVS CPU whenever a command
|
||||
has been processed. See [2] for more information on the brcm,l2-intc node.
|
||||
|
||||
[1] The AVS CPU is an independent co-processor that runs proprietary
|
||||
firmware. On some SoCs, this firmware supports DFS and DVFS in addition to
|
||||
Adaptive Voltage Scaling.
|
||||
|
||||
[2] Documentation/devicetree/bindings/interrupt-controller/brcm,l2-intc.txt
|
||||
|
||||
|
||||
Node brcm,avs-cpu-data-mem
|
||||
--------------------------
|
||||
|
||||
Required properties:
|
||||
- compatible: must include: brcm,avs-cpu-data-mem and
|
||||
should include: one of brcm,bcm7271-avs-cpu-data-mem or
|
||||
brcm,bcm7268-avs-cpu-data-mem
|
||||
- reg: Specifies base physical address and size of the registers.
|
||||
- interrupts: The interrupt that the AVS CPU will use to interrupt the host
|
||||
when a command completed.
|
||||
- interrupt-parent: The interrupt controller the above interrupt is routed
|
||||
through.
|
||||
- interrupt-names: The name of the interrupt used to interrupt the host.
|
||||
|
||||
Optional properties:
|
||||
- None
|
||||
|
||||
Node brcm,avs-cpu-l2-intr
|
||||
-------------------------
|
||||
|
||||
Required properties:
|
||||
- compatible: must include: brcm,avs-cpu-l2-intr and
|
||||
should include: one of brcm,bcm7271-avs-cpu-l2-intr or
|
||||
brcm,bcm7268-avs-cpu-l2-intr
|
||||
- reg: Specifies base physical address and size of the registers.
|
||||
|
||||
Optional properties:
|
||||
- None
|
||||
|
||||
|
||||
Example
|
||||
=======
|
||||
|
||||
avs_host_l2_intc: interrupt-controller@f04d1200 {
|
||||
#interrupt-cells = <1>;
|
||||
compatible = "brcm,l2-intc";
|
||||
interrupt-parent = <&intc>;
|
||||
reg = <0xf04d1200 0x48>;
|
||||
interrupt-controller;
|
||||
interrupts = <0x0 0x19 0x0>;
|
||||
interrupt-names = "avs";
|
||||
};
|
||||
|
||||
avs-cpu-data-mem@f04c4000 {
|
||||
compatible = "brcm,bcm7271-avs-cpu-data-mem",
|
||||
"brcm,avs-cpu-data-mem";
|
||||
reg = <0xf04c4000 0x60>;
|
||||
interrupts = <0x1a>;
|
||||
interrupt-parent = <&avs_host_l2_intc>;
|
||||
interrupt-names = "sw_intr";
|
||||
};
|
||||
|
||||
avs-cpu-l2-intr@f04d1100 {
|
||||
compatible = "brcm,bcm7271-avs-cpu-l2-intr",
|
||||
"brcm,avs-cpu-l2-intr";
|
||||
reg = <0xf04d1100 0x10>;
|
||||
};
|
@ -123,6 +123,9 @@ PROPERTIES
|
||||
|
||||
|
||||
EXAMPLE
|
||||
|
||||
iMX6QDL/SX requires four clocks
|
||||
|
||||
crypto@300000 {
|
||||
compatible = "fsl,sec-v4.0";
|
||||
fsl,sec-era = <2>;
|
||||
@ -139,6 +142,23 @@ EXAMPLE
|
||||
clock-names = "mem", "aclk", "ipg", "emi_slow";
|
||||
};
|
||||
|
||||
|
||||
iMX6UL does only require three clocks
|
||||
|
||||
crypto: caam@2140000 {
|
||||
compatible = "fsl,sec-v4.0";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x2140000 0x3c000>;
|
||||
ranges = <0 0x2140000 0x3c000>;
|
||||
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
clocks = <&clks IMX6UL_CLK_CAAM_MEM>,
|
||||
<&clks IMX6UL_CLK_CAAM_ACLK>,
|
||||
<&clks IMX6UL_CLK_CAAM_IPG>;
|
||||
clock-names = "mem", "aclk", "ipg";
|
||||
};
|
||||
|
||||
=====================================================================
|
||||
Job Ring (JR) Node
|
||||
|
||||
|
19
Bindings/devfreq/event/rockchip-dfi.txt
Normal file
19
Bindings/devfreq/event/rockchip-dfi.txt
Normal file
@ -0,0 +1,19 @@
|
||||
|
||||
* Rockchip rk3399 DFI device
|
||||
|
||||
Required properties:
|
||||
- compatible: Must be "rockchip,rk3399-dfi".
|
||||
- reg: physical base address of each DFI and length of memory mapped region
|
||||
- rockchip,pmu: phandle to the syscon managing the "pmu general register files"
|
||||
- clocks: phandles for clock specified in "clock-names" property
|
||||
- clock-names : the name of clock used by the DFI, must be "pclk_ddr_mon";
|
||||
|
||||
Example:
|
||||
dfi: dfi@0xff630000 {
|
||||
compatible = "rockchip,rk3399-dfi";
|
||||
reg = <0x00 0xff630000 0x00 0x4000>;
|
||||
rockchip,pmu = <&pmugrf>;
|
||||
clocks = <&cru PCLK_DDR_MON>;
|
||||
clock-names = "pclk_ddr_mon";
|
||||
status = "disabled";
|
||||
};
|
209
Bindings/devfreq/rk3399_dmc.txt
Normal file
209
Bindings/devfreq/rk3399_dmc.txt
Normal file
@ -0,0 +1,209 @@
|
||||
* Rockchip rk3399 DMC(Dynamic Memory Controller) device
|
||||
|
||||
Required properties:
|
||||
- compatible: Must be "rockchip,rk3399-dmc".
|
||||
- devfreq-events: Node to get DDR loading, Refer to
|
||||
Documentation/devicetree/bindings/devfreq/
|
||||
rockchip-dfi.txt
|
||||
- interrupts: The interrupt number to the CPU. The interrupt
|
||||
specifier format depends on the interrupt controller.
|
||||
It should be DCF interrupts, when DDR dvfs finish,
|
||||
it will happen.
|
||||
- clocks: Phandles for clock specified in "clock-names" property
|
||||
- clock-names : The name of clock used by the DFI, must be
|
||||
"pclk_ddr_mon";
|
||||
- operating-points-v2: Refer to Documentation/devicetree/bindings/power/opp.txt
|
||||
for details.
|
||||
- center-supply: DMC supply node.
|
||||
- status: Marks the node enabled/disabled.
|
||||
|
||||
Following properties are ddr timing:
|
||||
|
||||
- rockchip,dram_speed_bin : Value reference include/dt-bindings/clock/ddr.h,
|
||||
it select ddr3 cl-trp-trcd type, default value
|
||||
"DDR3_DEFAULT".it must selected according to
|
||||
"Speed Bin" in ddr3 datasheet, DO NOT use
|
||||
smaller "Speed Bin" than ddr3 exactly is.
|
||||
|
||||
- rockchip,pd_idle : Config the PD_IDLE value, defined the power-down
|
||||
idle period, memories are places into power-down
|
||||
mode if bus is idle for PD_IDLE DFI clocks.
|
||||
|
||||
- rockchip,sr_idle : Configure the SR_IDLE value, defined the
|
||||
selfrefresh idle period, memories are places
|
||||
into self-refresh mode if bus is idle for
|
||||
SR_IDLE*1024 DFI clocks (DFI clocks freq is
|
||||
half of dram's clocks), defaule value is "0".
|
||||
|
||||
- rockchip,sr_mc_gate_idle : Defined the self-refresh with memory and
|
||||
controller clock gating idle period, memories
|
||||
are places into self-refresh mode and memory
|
||||
controller clock arg gating if bus is idle for
|
||||
sr_mc_gate_idle*1024 DFI clocks.
|
||||
|
||||
- rockchip,srpd_lite_idle : Defined the self-refresh power down idle
|
||||
period, memories are places into self-refresh
|
||||
power down mode if bus is idle for
|
||||
srpd_lite_idle*1024 DFI clocks. This parameter
|
||||
is for LPDDR4 only.
|
||||
|
||||
- rockchip,standby_idle : Defined the standby idle period, memories are
|
||||
places into self-refresh than controller, pi,
|
||||
phy and dram clock will gating if bus is idle
|
||||
for standby_idle * DFI clocks.
|
||||
|
||||
- rockchip,dram_dll_disb_freq : It's defined the DDR3 dll bypass frequency in
|
||||
MHz, when ddr freq less than DRAM_DLL_DISB_FREQ,
|
||||
ddr3 dll will bypssed note: if dll was bypassed,
|
||||
the odt also stop working.
|
||||
|
||||
- rockchip,phy_dll_disb_freq : Defined the PHY dll bypass frequency in
|
||||
MHz (Mega Hz), when ddr freq less than
|
||||
DRAM_DLL_DISB_FREQ, phy dll will bypssed.
|
||||
note: phy dll and phy odt are independent.
|
||||
|
||||
- rockchip,ddr3_odt_disb_freq : When dram type is DDR3, this parameter defined
|
||||
the odt disable frequency in MHz (Mega Hz),
|
||||
when ddr frequency less then ddr3_odt_disb_freq,
|
||||
the odt on dram side and controller side are
|
||||
both disabled.
|
||||
|
||||
- rockchip,ddr3_drv : When dram type is DDR3, this parameter define
|
||||
the dram side driver stength in ohm, default
|
||||
value is DDR3_DS_40ohm.
|
||||
|
||||
- rockchip,ddr3_odt : When dram type is DDR3, this parameter define
|
||||
the dram side ODT stength in ohm, default value
|
||||
is DDR3_ODT_120ohm.
|
||||
|
||||
- rockchip,phy_ddr3_ca_drv : When dram type is DDR3, this parameter define
|
||||
the phy side CA line(incluing command line,
|
||||
address line and clock line) driver strength.
|
||||
Default value is PHY_DRV_ODT_40.
|
||||
|
||||
- rockchip,phy_ddr3_dq_drv : When dram type is DDR3, this parameter define
|
||||
the phy side DQ line(incluing DQS/DQ/DM line)
|
||||
driver strength. default value is PHY_DRV_ODT_40.
|
||||
|
||||
- rockchip,phy_ddr3_odt : When dram type is DDR3, this parameter define the
|
||||
phy side odt strength, default value is
|
||||
PHY_DRV_ODT_240.
|
||||
|
||||
- rockchip,lpddr3_odt_disb_freq : When dram type is LPDDR3, this parameter defined
|
||||
then odt disable frequency in MHz (Mega Hz),
|
||||
when ddr frequency less then ddr3_odt_disb_freq,
|
||||
the odt on dram side and controller side are
|
||||
both disabled.
|
||||
|
||||
- rockchip,lpddr3_drv : When dram type is LPDDR3, this parameter define
|
||||
the dram side driver stength in ohm, default
|
||||
value is LP3_DS_34ohm.
|
||||
|
||||
- rockchip,lpddr3_odt : When dram type is LPDDR3, this parameter define
|
||||
the dram side ODT stength in ohm, default value
|
||||
is LP3_ODT_240ohm.
|
||||
|
||||
- rockchip,phy_lpddr3_ca_drv : When dram type is LPDDR3, this parameter define
|
||||
the phy side CA line(incluing command line,
|
||||
address line and clock line) driver strength.
|
||||
default value is PHY_DRV_ODT_40.
|
||||
|
||||
- rockchip,phy_lpddr3_dq_drv : When dram type is LPDDR3, this parameter define
|
||||
the phy side DQ line(incluing DQS/DQ/DM line)
|
||||
driver strength. default value is
|
||||
PHY_DRV_ODT_40.
|
||||
|
||||
- rockchip,phy_lpddr3_odt : When dram type is LPDDR3, this parameter define
|
||||
the phy side odt strength, default value is
|
||||
PHY_DRV_ODT_240.
|
||||
|
||||
- rockchip,lpddr4_odt_disb_freq : When dram type is LPDDR4, this parameter
|
||||
defined the odt disable frequency in
|
||||
MHz (Mega Hz), when ddr frequency less then
|
||||
ddr3_odt_disb_freq, the odt on dram side and
|
||||
controller side are both disabled.
|
||||
|
||||
- rockchip,lpddr4_drv : When dram type is LPDDR4, this parameter define
|
||||
the dram side driver stength in ohm, default
|
||||
value is LP4_PDDS_60ohm.
|
||||
|
||||
- rockchip,lpddr4_dq_odt : When dram type is LPDDR4, this parameter define
|
||||
the dram side ODT on dqs/dq line stength in ohm,
|
||||
default value is LP4_DQ_ODT_40ohm.
|
||||
|
||||
- rockchip,lpddr4_ca_odt : When dram type is LPDDR4, this parameter define
|
||||
the dram side ODT on ca line stength in ohm,
|
||||
default value is LP4_CA_ODT_40ohm.
|
||||
|
||||
- rockchip,phy_lpddr4_ca_drv : When dram type is LPDDR4, this parameter define
|
||||
the phy side CA line(incluing command address
|
||||
line) driver strength. default value is
|
||||
PHY_DRV_ODT_40.
|
||||
|
||||
- rockchip,phy_lpddr4_ck_cs_drv : When dram type is LPDDR4, this parameter define
|
||||
the phy side clock line and cs line driver
|
||||
strength. default value is PHY_DRV_ODT_80.
|
||||
|
||||
- rockchip,phy_lpddr4_dq_drv : When dram type is LPDDR4, this parameter define
|
||||
the phy side DQ line(incluing DQS/DQ/DM line)
|
||||
driver strength. default value is PHY_DRV_ODT_80.
|
||||
|
||||
- rockchip,phy_lpddr4_odt : When dram type is LPDDR4, this parameter define
|
||||
the phy side odt strength, default value is
|
||||
PHY_DRV_ODT_60.
|
||||
|
||||
Example:
|
||||
dmc_opp_table: dmc_opp_table {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
opp00 {
|
||||
opp-hz = /bits/ 64 <300000000>;
|
||||
opp-microvolt = <900000>;
|
||||
};
|
||||
opp01 {
|
||||
opp-hz = /bits/ 64 <666000000>;
|
||||
opp-microvolt = <900000>;
|
||||
};
|
||||
};
|
||||
|
||||
dmc: dmc {
|
||||
compatible = "rockchip,rk3399-dmc";
|
||||
devfreq-events = <&dfi>;
|
||||
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru SCLK_DDRCLK>;
|
||||
clock-names = "dmc_clk";
|
||||
operating-points-v2 = <&dmc_opp_table>;
|
||||
center-supply = <&ppvar_centerlogic>;
|
||||
upthreshold = <15>;
|
||||
downdifferential = <10>;
|
||||
rockchip,ddr3_speed_bin = <21>;
|
||||
rockchip,pd_idle = <0x40>;
|
||||
rockchip,sr_idle = <0x2>;
|
||||
rockchip,sr_mc_gate_idle = <0x3>;
|
||||
rockchip,srpd_lite_idle = <0x4>;
|
||||
rockchip,standby_idle = <0x2000>;
|
||||
rockchip,dram_dll_dis_freq = <300>;
|
||||
rockchip,phy_dll_dis_freq = <125>;
|
||||
rockchip,auto_pd_dis_freq = <666>;
|
||||
rockchip,ddr3_odt_dis_freq = <333>;
|
||||
rockchip,ddr3_drv = <DDR3_DS_40ohm>;
|
||||
rockchip,ddr3_odt = <DDR3_ODT_120ohm>;
|
||||
rockchip,phy_ddr3_ca_drv = <PHY_DRV_ODT_40>;
|
||||
rockchip,phy_ddr3_dq_drv = <PHY_DRV_ODT_40>;
|
||||
rockchip,phy_ddr3_odt = <PHY_DRV_ODT_240>;
|
||||
rockchip,lpddr3_odt_dis_freq = <333>;
|
||||
rockchip,lpddr3_drv = <LP3_DS_34ohm>;
|
||||
rockchip,lpddr3_odt = <LP3_ODT_240ohm>;
|
||||
rockchip,phy_lpddr3_ca_drv = <PHY_DRV_ODT_40>;
|
||||
rockchip,phy_lpddr3_dq_drv = <PHY_DRV_ODT_40>;
|
||||
rockchip,phy_lpddr3_odt = <PHY_DRV_ODT_240>;
|
||||
rockchip,lpddr4_odt_dis_freq = <333>;
|
||||
rockchip,lpddr4_drv = <LP4_PDDS_60ohm>;
|
||||
rockchip,lpddr4_dq_odt = <LP4_DQ_ODT_40ohm>;
|
||||
rockchip,lpddr4_ca_odt = <LP4_CA_ODT_40ohm>;
|
||||
rockchip,phy_lpddr4_ca_drv = <PHY_DRV_ODT_40>;
|
||||
rockchip,phy_lpddr4_ck_cs_drv = <PHY_DRV_ODT_80>;
|
||||
rockchip,phy_lpddr4_dq_drv = <PHY_DRV_ODT_80>;
|
||||
rockchip,phy_lpddr4_odt = <PHY_DRV_ODT_60>;
|
||||
status = "disabled";
|
||||
};
|
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Reference in New Issue
Block a user