3 Commits

Author	SHA1	Message	Date
John Baldwin	e83ea6241a	Each processor socket in a QPI system has a special PCI bus for the ... "uncore" devices (such as the memory controller) in that socket. Stop hardcoding support for two busses, but instead start probing buses at domain 0, bus 255 and walk down until a bus probe fails. Also, do not probe a bus if it has already been enumerated elsewhere (e.g. if ACPI ever enumerates these buses in the future).	2010-09-07 13:50:02 +00:00
John Baldwin	8bddaf9007	Correctly ensure that the CPU family is 0x6, not non-zero. ... Submitted by: Dimitry Andric	2010-08-25 20:37:58 +00:00
John Baldwin	c2175767b7	Intel QPI chipsets actually provide two extra "non-core" PCI buses that ... provide PCI devices for various hardware such as memory controllers, etc. These PCI buses are not enumerated via ACPI however. Add qpi(4) psuedo bus and Host-PCI bridge drivers to enumerate these buses. Currently the driver uses the CPU ID to determine the bridges' presence. In collaboration with: Joseph Golio @ Isilon Systems MFC after: 2 weeks	2010-08-25 19:12:05 +00:00