- add bus_space_rmi_pci.c for PCI bus space
- files.xlr update for changes in files
- pcibus.c merged into xlr_pci.c (they were small files with inter-dependencies)
- xlr_pci.c - lot of changes here with few fixes, formatting cleanup
Obtained from: C. Jayachandran (JC) - c.jayachandran@gmail.com
- remove pci related code from bus_space_rmi.c, we will have another
file for PCI bus space functions which will do byte-swapping.
- remove local SWAP implementation
- added TODO stub for unimplemented functions
Obtained from: C. Jayachandran - c.jayachandran@gmail.com
- (cleanup) remove rmi specific 'struct mips_intrhand' - this is no
longer needed since 'struct intr_event' have all the required hooks
- add xlr_cpu_establish_hardintr, which has args for pre/post ithread
and filter hooks, so that the PCI code can add the PCI controller
interrupt ack code here
- make 'cpu_establish_hardintr' use the above function.
- (fix) change type of eirr/eimr from register_t to uint64_t. These
have to be 64bit otherwise we cannot handle interrupts from 32.
- (fix) use eimr to mask eirr before checking interrupts, so that we
will not handle masked interrupts.
Obtained from: C. Jayachandran - c.jayachandran@gmail.com
The backtrace code tries to look for an instruction of the form "sw ra, x(sp)"
to figure out the program counter of the calling function. When we generate
the kernel exception frame we store the 'ra' at the time of the exception
using an instruction of the same form. The problem is that the 'ra' at the
time of the exception is not the same as the 'program counter' at the time
of the exception.
The fix is to save the 'exception program counter' register by staging
it through the 'ra' register.
The RX overflow is reported in bit 2 on real hardware and Linux driver
for the same device already has this defined correctly.
This fixes frequent interrupt storms seen on RouterStation Pro boards.
Discussed with: gonzo
Getting the little-endian PCI bus working on the big-endian CPU proved to be
quite challenging. We let the PCI devices be mapped in the "match byte lanes"
address window. This is where they are mapped by the CFE and DMA transfers
generated to or from addresses within this window are not subject to automatic
byte-swapping.
However any access by the driver to memory-mapped pci space is redirected
via the "match bit lanes" address window. We get the benefit of automatic
byte swapping through this address window and drivers don't need to change
to deal with CPU big-endianness.
this in the Sibyte PCI hostbridge driver instead.
The nexus driver sees resource allocation requests for memory and irq
resources only. These are legitimate resources on all MIPS platforms.
Suggested by: imp
the 'debugging' section of any HEAD kernel and enable for the mainstream
ones, excluding the embedded architectures.
It may, of course, enabled on a case-by-case basis.
Sponsored by: Sandvine Incorporated
Requested by: emaste
Discussed with: kib
have code that detects this and makes two
transmit descriptors. However its possible
that the algorithm detects when the second
page is not used (when the data aligns perfectly
to the bottom of the page). This caused a 0
len descriptor to be added which locks up the
rge device. Skip such things with a continue.
JC provided this patch... Thanks JC :-)
Obtained from: JC (c.jayachandran@gmail.com)
Specifically on an SMP kernel it was observed that if both the
processors are doing an exit1() via ast()->postsig()->sigexit()
then we will deadlock.
This happens because exit1() calls vmspace_exit() that in turn
calls pmap_invalidate_all(). This function tries to do a
smp_rendezvous() which blocks because the other processor is not
responding to IPIs - because it too is doing AST processing with
interrupts disabled.
The platform that supports SMP currently is a SWARM with a dual-core Sibyte
processor. The kernel config file to use is SWARM_SMP.
Reviewed by: imp, rrs
disabling interrupts.
Simplify register usage - we can directly load 'curpcb' into 'k1' after
interrupts are disabled. There is no need to do so indirectly through 'a1'.
The only reason we need to have the sb_load64() and sb_store64()
functions in assembly is to cheat the compiler and generate the
'ld' and 'sd' instructions which it otherwise will not do when
compiling for a 32-bit architecture. There are some 64-bit
registers in the SCD unit that must be accessed using 64-bit
load and store instructions.
The basic idea is to use a the same virtual address as a window onto
distinct physical memory locations - one per processor. The physical
address that you access through this mapping depends on which cpu you
are currently executing on. We can now use the same virtual address
on any processor to access its per-cpu area.
The details are:
- The virtual address for 'struct pcpu *pcpup' is obtained by
stealing 2 pages worth of KVA in pmap_bootstrap().
- The mapping from the constant virtual address to a distinct
physical page is done in cpu_pcpu_init() through a wired TLB entry.
- A side-effect of this is that we reserve 2 pages worth of memory
for the pcpu but in reality it needs much less than that. The unused
memory is now used as the boot stack for the BSP and APs.
Remove SMP-specific bits from locore.S. The plan is to use a separate
mpboot.S for AP bootstrap.
Discussed on: freebsd-mips
Approved by: imp (mentor)
interrupts must be disabled through the
page_zero's or copys etc. Note that the
temporary mapping used by panic's may
cause us pain since int's may not be disabled.
When we get dumps working we may have to revist
this. Note that with this fix the build got
much much further.. until it hung on disk IO (I
would imagine thats the rge/msgring driver acting
up).
above 4Gig. If so when we add the base address with
the size we will wrap. So for now we just ignore
such memory and only use what we can. When we
get 64 bit working then we will be much better ;->
lacking a copyright/license statement. All these files were in the
Cavium FreeBSD source drop and appear to be written by Cavium (some
are nearly verbatim copies of files from the cnusers' 1.9.0 SDK, which
also uses this copyright).
routine in one place was setting the valid2 bit to
2 not 1. This meant the PTE was NOT valid and so
you would crash.
In Zero Page there was a incorrect setting of
the valid bit AFTER the actual zero (opps)..
Hopefully this will fix the 0xc0000000 crashes
that I have been seeing (unless of course there are
other problems with these old hacks of mine to get
to memory above 512Meg)
the RMI/XLR has the COP0 and COP2 bits enabled
Plus it needs SX too. Thanks again for JC in
catching this ;-)
Submitted by: JC (jayachandranc@netlogicmicro.com
to invalidate memory chunk that starts or ends in the middle of
cache line.
This was responsible for one half of the problem preventing umass
to work reliably on some MIPS32 platforms. USBng needs to stop
sharing cache lines between DMA-able memory and other structures
to cure the other half.
Discussed with: imp, gonzo
