Commit Graph

437 Commits

Author SHA1 Message Date
Ed Maste
d4cd50b494 libunwind: add noexec stack annotation
Reported by:	vangyzen
Reviewed by:	kib
MFC after:	1 week
Sponsored by:	The FreeBSD Foundation
Differential Revision:	https://reviews.freebsd.org/D9075
2017-01-07 14:40:58 +00:00
Ed Maste
77ac8927fd libunwind: make __{de,}register_frame compatible with libgcc API
The libgcc __register_frame and __deregister_frame functions take a
pointer to a set of FDE/CIEs, terminated by an entry where length is 0.

In Apple's libunwind implementation the pointer is taken to be to a
single FDE. I suspect this was just an Apple bug, compensated by Apple-
specific code in LLVM.

See lib/ExecutionEngine/RuntimeDyld/RTDyldMemoryManager.cpp and
http://lists.llvm.org/pipermail/llvm-dev/2013-April/061737.html
for more detail.

This change is based on the LLVM RTDyldMemoryManager.cpp. It should
later be changed to be alignment-safe.

Reported by:	dim
Reviewed by:	dim
MFC after:	1 month
Sponsored by:	The FreeBSD Foundation
Differential Revision:	https://reviews.freebsd.org/D8869
2016-12-21 14:06:44 +00:00
Dimitry Andric
3ffd353070 Merge ^/head r309817 through r310168. 2016-12-16 18:38:31 +00:00
Dimitry Andric
d246bac328 Merge llvm, clang, lld, lldb, compiler-rt and libc++ 3.9.1 release
r289601.
2016-12-16 18:30:53 +00:00
Dimitry Andric
e480fc73f5 Tentatively apply https://reviews.llvm.org/D18730 to work around gcc PR
70528 (bogus error: constructor required before non-static data member).
This should fix buildworld with the external gcc package.

Reported by:	https://jenkins.freebsd.org/job/FreeBSD_HEAD_amd64_gcc/
2016-12-10 22:03:44 +00:00
Dimitry Andric
7a83c005f5 Update llvm, clang, lld, lldb, compiler-rt and libc++ to release_39
branch r288847.
2016-12-10 15:30:39 +00:00
Dimitry Andric
1bde3b7066 Merge ^/head r309519 through r309757. 2016-12-09 20:57:43 +00:00
Dimitry Andric
3157e69de7 Pull in r281586 from upstream llvm trunk (by Wei Mi):
Add some shortcuts in LazyValueInfo to reduce compile time of
  Correlated Value Propagation.

  The patch is to partially fix PR10584. Correlated Value Propagation
  queries LVI to check non-null for pointer params of each callsite. If
  we know the def of param is an alloca instruction, we know it is
  non-null and can return early from LVI. Similarly, CVP queries LVI to
  check whether pointer for each mem access is constant. If the def of
  the pointer is an alloca instruction, we know it is not a constant
  pointer. These shortcuts can reduce the cost of CVP significantly.

  Differential Revision: https://reviews.llvm.org/D18066

This significantly reduces memory usage and compilation time when
compiling a particular C++ source file of the graphics/colmap port.

PR:		215136
MFC after:	3 days
2016-12-08 21:02:34 +00:00
Dimitry Andric
4dcfa14438 Update llvm, clang, lld and lldb to release_39 branch r288513. 2016-12-02 19:36:28 +00:00
Dimitry Andric
f41fbc90dc Update llvm, clang, lld and lldb to release_39 branch r287912. 2016-11-26 01:02:53 +00:00
Dimitry Andric
11c1fce83a Pull in r283060 from upstream llvm trunk (by Hal Finkel):
[PowerPC] Refactor soft-float support, and enable PPC64 soft float

  This change enables soft-float for PowerPC64, and also makes
  soft-float disable all vector instruction sets for both 32-bit and
  64-bit modes. This latter part is necessary because the PPC backend
  canonicalizes many Altivec vector types to floating-point types, and
  so soft-float breaks scalarization support for many operations. Both
  for embedded targets and for operating-system kernels desiring
  soft-float support, it seems reasonable that disabling hardware
  floating-point also disables vector instructions (embedded targets
  without hardware floating point support are unlikely to have Altivec,
  etc. and operating system kernels desiring not to use floating-point
  registers to lower syscall cost are unlikely to want to use vector
  registers either). If someone needs this to work, we'll need to
  change the fact that we promote many Altivec operations to act on
  v4f32. To make it possible to disable Altivec when soft-float is
  enabled, hardware floating-point support needs to be expressed as a
  positive feature, like the others, and not a negative feature,
  because target features cannot have dependencies on the disabling of
  some other feature. So +soft-float has now become -hard-float.

  Fixes PR26970.

Pull in r283061 from upstream clang trunk (by Hal Finkel):

  [PowerPC] Enable soft-float for PPC64, and +soft-float -> -hard-float

  Enable soft-float support on PPC64, as the backend now supports it.
  Also, the backend now uses -hard-float instead of +soft-float, so set
  the target features accordingly.

  Fixes PR26970.

Reported by:	Mark Millard
PR:		214433
2016-11-25 18:12:13 +00:00
Dimitry Andric
26aa2dc584 Pull in r282174 from upstream llvm trunk (by Krzysztof Parzyszek):
[PPC] Set SP after loading data from stack frame, if no red zone is
  present

  Follow-up to r280705: Make sure that the SP is only restored after
  all data is loaded from the stack frame, if there is no red zone.

  This completes the fix for
  https://llvm.org/bugs/show_bug.cgi?id=26519.

  Differential Revision: https://reviews.llvm.org/D24466

Reported by:    Mark Millard
PR:             214433
2016-11-25 18:01:32 +00:00
Dimitry Andric
f1d9b58cd4 Work around LLVM PR30879, which is about a bad interaction between X86
Call Frame Optimization on i386 and libunwind, by disallowing the
optimization for i386-freebsd12.

This should fix some instances of broken exception handling when frame
pointers are omitted, in particular some unittests run during the build
of editors/libreoffice.

This hack will be removed as soon as upstream has implemented a more
permanent fix for this problem.

Upstream PR:	https://llvm.org/bugs/show_bug.cgi?id=30879
Reviewed by:	emaste
PR:		212343
2016-11-19 21:05:17 +00:00
Dimitry Andric
2828dafcf3 Merge ^/head r308227 through r308490. 2016-11-10 22:12:19 +00:00
Dimitry Andric
0ef0edf2bb Pull in r263301 from upstream llvm trunk (by Ahmed Bougacha):
[AArch64] Don't blindly lower f16/f128 FCCMPs.

  Instead, extend f16 (like we do when lowering a standalone SETCC),
  and let f128 be legalized to the RT calls.

  Fixes PR26803.

This fixes a fatal "Cannot select" backend error when building the
net/freerdp port for AArch64.

PR:		214380
MFC after:	3 days
2016-11-10 19:40:14 +00:00
Ruslan Bukin
ef37962496 Implement riscv jumpto() so world can be compiled.
Sponsored by:	DARPA, AFRL
Sponsored by:	HEIF5
2016-11-10 12:54:33 +00:00
Dimitry Andric
10652ae062 Pull in r278002 from upstream llvm trunk (by Silviu Baranga):
[AArch64] PR28877: Don't assume we're running after legalization when
  creating vcvtfp2fxs

  Summary:
  The DAG combine transformation that was generating the
  aarch64_neon_vcvtfp2fxs node was assuming that all inputs where legal
  and wasn't accounting that the input could be a v4f64 if we're trying
  to do the transformation before legalization. We now bail out in this
  case.

  All illegal types besides v4f64 were already rejected.

  Fixes https://llvm.org/bugs/show_bug.cgi?id=28877

  Reviewers: jmolloy

  Subscribers: aemerson, rengolin, llvm-commits

  Differential Revision: https://reviews.llvm.org/D23261

This fixes several ports on AArch64.

Requested by:   andrew
MFC after:      3 days
2016-11-06 16:27:09 +00:00
Dimitry Andric
02ebdc7823 Merge ^/head r307736 through r308146. 2016-10-31 19:02:42 +00:00
Ed Maste
0656bb22c0 libunwind: consistently add \n to log and trace messages
Previously most messages included a newline in the string, but a few of
them were missing. Fix these and simplify by just adding the newline in
the _LIBUNWIND_LOG macro itself.

While here correct 'libuwind' typo (missing 'n').

Upstream LLVM libunwind commits r280086 and r280103.
2016-10-28 00:04:04 +00:00
Dimitry Andric
ffd193b577 Pull in r282336 from upstream llvm trunk (by Sanjay Patel):
[x86] don't try to create a vector integer inst for an SSE1 target
  (PR30512)

  This bug was introduced with:
  http://reviews.llvm.org/rL272511

  We need to restrict the lowering to v4f32 comparisons because that's
  all SSE1 can handle.

  This should fix:
  https://llvm.org/bugs/show_bug.cgi?id=28044

This avoids a "Do not know how to custom type legalize this operation"
error when building the multimedia/ffmpeg port on i386 with SSE enabled.
2016-09-24 20:53:05 +00:00
Dimitry Andric
9dbab393d9 Pull in r280705 from upstream llvm trunk (by Krzysztof Parzyszek):
[PPC] Claim stack frame before storing into it, if no red zone is
  present

  Unlike PPC64, PPC32/SVRV4 does not have red zone. In the absence of
  it there is no guarantee that this part of the stack will not be
  modified by any interrupt. To avoid this, make sure to claim the
  stack frame first before storing into it.

  This fixes https://llvm.org/bugs/show_bug.cgi?id=26519.

  Differential Revision: https://reviews.llvm.org/D24093
2016-09-10 16:51:39 +00:00
Dimitry Andric
82d50f9201 Pull in r280350 from upstream llvm trunk (by Hal Finkel):
Add ISD::EH_DWARF_CFA, simplify @llvm.eh.dwarf.cfa on Mips, fix on
  PowerPC

  LLVM has an @llvm.eh.dwarf.cfa intrinsic, used to lower the
  GCC-compatible __builtin_dwarf_cfa() builtin. As pointed out in
  PR26761, this is currently broken on PowerPC (and likely on ARM as
  well). Currently, @llvm.eh.dwarf.cfa is lowered using:

    ADD(FRAMEADDR, FRAME_TO_ARGS_OFFSET)

  where FRAME_TO_ARGS_OFFSET defaults to the constant zero. On x86,
  FRAME_TO_ARGS_OFFSET is lowered to 2*SlotSize. This setup, however,
  does not work for PowerPC. Because of the way that the stack layout
  works, the canonical frame address is not exactly (FRAMEADDR +
  FRAME_TO_ARGS_OFFSET) on PowerPC (there is a lower save-area offset
  as well), so it is not just a matter of implementing
  FRAME_TO_ARGS_OFFSET for PowerPC (unless we redefine its semantics --
  We can do that, since it is currently used only for
  @llvm.eh.dwarf.cfa lowering, but the better to directly lower the CFA
  construct itself (since it can be easily represented as a
  fixed-offset FrameIndex)). Mips currently does this, but by using a
  custom lowering for ADD that specifically recognizes the (FRAMEADDR,
  FRAME_TO_ARGS_OFFSET) pattern.

  This change introduces a ISD::EH_DWARF_CFA node, which by default
  expands using the existing logic, but can be directly lowered by the
  target. Mips is updated to use this method (which simplifies its
  implementation, and I suspect makes it more robust), and updates
  PowerPC to do the same.

  Fixes PR26761.

  Differential Revision: https://reviews.llvm.org/D24038
2016-09-10 16:11:42 +00:00
Dimitry Andric
1efa33ef28 Pull in r280188 from upstream llvm trunk (by Hal Finkel):
[PowerPC] Don't spill the frame pointer twice

  When a function contains something, such as inline asm, which
  explicitly clobbers the register used as the frame pointer, don't
  spill it twice. If we need a frame pointer, it will be saved/restored
  in the prologue/epilogue code.  Explicitly spilling it again will
  reuse the same spill slot used by the prologue/epilogue code, thus
  clobbering the saved value. The same applies to the base-pointer or
  PIC-base register.

  Partially fixes PR26856. Thanks to Ulrich for his analysis and the
  small inline-asm reproducer.
2016-09-10 15:44:00 +00:00
Dimitry Andric
b6054a7b70 Pull in r280040 from upstream llvm trunk (by Hal Finkel):
[PowerPC] Add support for -mlongcall

  The "long call" option forces the use of the indirect calling
  sequence for all calls (even those that don't really need it). GCC
  provides this option; This is helpful, under certain circumstances,
  for building very-large binaries, and some other specialized use
  cases.

  Fixes PR19098.

Pull in r280041 from upstream clang trunk (by Hal Finkel):

  [PowerPC] Add support for -mlongcall

  Add support for GCC's PowerPC -mlongcall option; the backend supports
  the corresponding target feature as of r280040.

  Fixes PR19098.
2016-09-10 15:38:46 +00:00
Dimitry Andric
1f645baf55 Pull in r280837 from upstream llvm trunk (by Wei Mi):
Don't reduce the width of vector mul if the target doesn't support
  SSE2.

  The patch is to fix PR30298, which is caused by rL272694. The
  solution is to bail out if the target has no SSE2.

  Differential Revision: https://reviews.llvm.org/D24288

This fixes building the multimedia/libx264 port on i386.
2016-09-07 20:36:13 +00:00
Dimitry Andric
d1c8d4428b Update clang to the final 3.9.0 release. There were no more code changes
since the last release candidate.
2016-09-02 19:20:27 +00:00
Dimitry Andric
8f1f370da9 Merge ^/head r305087 through r305219. 2016-09-01 18:16:45 +00:00
Dimitry Andric
1dc088ab69 Pull in r277331 from upstream llvm trunk (by Diana Picus):
[AArch64] Return the correct size for TLSDESC_CALLSEQ

  The branch relaxation pass is computing the wrong offsets because it assumes
  TLSDESC_CALLSEQ eats up 4 bytes, when in fact it is lowered to an instruction
  sequence taking up 16 bytes. This can become a problem in huge files with lots
  of TLS accesses, as it may slowly move branch targets out of the range computed
  by the branch relaxation pass.

  Fixes PR24234 https://llvm.org/bugs/show_bug.cgi?id=24234

  Differential Revision: https://reviews.llvm.org/D22870

This fixes "error in backend: fixup value out of range" when compiling
the misc/talkfilters port for AArch64.

Reported by:	sbruno
PR:		201762
MFC after:	3 days
2016-09-01 18:11:44 +00:00
Ed Maste
cc5e1c7d54 Include Options.inc using path from lld src top
Otherwise we will encoutner conflicts with libllvm's Options.inc in the
bmake lld build.
2016-08-30 16:49:09 +00:00
Ed Maste
4cb4d1d8cf lld: only include GNU ld emulation
We don't need Windows link.exe and Darwin Mach-O linker emulation now.
2016-08-30 16:43:24 +00:00
Ed Maste
b641216763 Add lld FREEBSD-Xlist corresponding to directories removed in r305067 2016-08-30 16:17:09 +00:00
Ed Maste
97c3811c96 Bring lld (release_39 branch, r279477) to contrib 2016-08-30 16:15:19 +00:00
Dimitry Andric
07e2539346 Tentatively apply https://reviews.llvm.org/D23921, to get rid of false
positive diagnostics from -Wvarargs about enum parameters, e.g.:

cddl/contrib/opensolaris/lib/libnvpair/libnvpair.c:388:15: error: passing an object that undergoes default argument promotion to 'va_start' has undefined behavior
      [-Werror,-Wvarargs]
        va_start(ap, which);
                     ^
cddl/contrib/opensolaris/lib/libnvpair/libnvpair.c:382:66: note: parameter of type 'enum nvlist_prtctl_fmt' is declared here
nvlist_prtctl_dofmt(nvlist_prtctl_t pctl, enum nvlist_prtctl_fmt which, ...)
                                                                 ^
2016-08-28 19:28:00 +00:00
Dimitry Andric
68629f0dce Update llvm to release_39 branch r279689. 2016-08-27 11:51:08 +00:00
Dimitry Andric
df96a70f74 Slightly reduce diffs against upstream lldb, and comment out PDB support. 2016-08-25 21:13:16 +00:00
Dimitry Andric
be69257a66 Update clang to release_39 branch r279477. 2016-08-24 17:43:49 +00:00
Dimitry Andric
fccc5558f5 Update llvm to release_39 branch r279477. 2016-08-24 17:43:08 +00:00
Dimitry Andric
9228435a16 Update build glue for lldb. Also comment out parts of the
initialization and termination code which reference plugins and
components that we don't use.
2016-08-20 18:45:25 +00:00
Dimitry Andric
0c6be76289 Cleanup some left-over CMakeLists.txt files. 2016-08-20 15:20:01 +00:00
Dimitry Andric
6ca8079c85 Pull in r265122 from upstream llvm trunk (by James Molloy):
Fix for pr24346: arm asm label calculation error in sub

  Some ARM instructions encode 32-bit immediates as a 8-bit integer
  (0-255) and a 4-bit rotation (0-30, even) in its least significant 12
  bits. The original fixup, FK_Data_4, patches the instruction by the
  value bit-to-bit, regardless of the encoding. For example, assuming
  the label L1 and L2 are 0x0 and 0x104 respectively, the following
  instruction:

    add r0, r0, #(L2 - L1) ; expects 0x104, i.e., 260

  would be assembled to the following, which adds 1 to r0, instead of
  260:

    e2800104 add r0, r0, #4, 2 ; equivalently 1

  The new fixup kind fixup_arm_mod_imm takes care of the encoding:

    e2800f41 add r0, r0, #260

  Patch by Ting-Yuan Huang!

This fixes label calculation for ARM assembly, and is needed to enable
ARM assembly sources for OpenSSL.

Requested by:	jkim
MFC after:	3 days
2016-08-20 14:04:51 +00:00
Dimitry Andric
910b36f73f Pull in r262772 from upstream clang trunk (by Simon Pilgrim):
[X86] AMD Bobcat CPU (btver1) doesn't support XSAVE

  btver1 is a SSSE3/SSE4a only CPU - it doesn't have AVX and doesn't
  support XSAVE.

  Differential Revision: http://reviews.llvm.org/D17682

Pull in r262782 from upstream llvm trunk (by Simon Pilgrim):

  [X86] AMD Bobcat CPU (btver1) doesn't support XSAVE

  btver1 is a SSSE3/SSE4a only CPU - it doesn't have AVX and doesn't
  support XSAVE.

  Differential Revision: http://reviews.llvm.org/D17683

This ensures clang does not emit AVX instructions for CPUTYPE=btver1.

Reported by:	Michel Depeige <demik+freebsd@lostwave.net>
PR:		211864
MFC after:	3 days
2016-08-17 21:57:11 +00:00
Dimitry Andric
500ffce73e Update lldb to release_39 branch r278877. 2016-08-17 19:43:45 +00:00
Dimitry Andric
52449dae19 Update clang to release_39 branch r278877. 2016-08-17 19:42:52 +00:00
Dimitry Andric
6c4bc1bd27 Update llvm to release_39 branch r278877. 2016-08-17 19:41:29 +00:00
Ed Maste
4bb0738ee7 Update lldb to release_39 branch r276489 and resolve immediate conflicts. 2016-08-17 08:51:41 +00:00
Dimitry Andric
6f79a7d5fc Remove one obsolete piece of code, that I originally imported from
upstream clang r266775, but got moved around later in upstream r266797.
2016-08-17 06:58:43 +00:00
Dimitry Andric
e7145dcb9f Update clang to release_39 branch r276489, and resolve conflicts. 2016-08-16 21:17:51 +00:00
Dimitry Andric
3ca95b0202 Update llvm to release_39 branch r276489, and resolve conflicts. 2016-08-16 21:02:59 +00:00
Ed Maste
03f124f737 libunwind: correct return code in unwinding trace log message
Obtained from:	LLVM r277215
MFC after:	3 days
Sponsored by:	The FreeBSD Foundation
2016-07-29 21:37:00 +00:00
Ruslan Bukin
0efcacc58b Set real values for context/cursor sizes for RISC-V to prevent static
assertions.

Reviewed by:	emaste
Sponsored by:	DARPA, AFRL
2016-07-22 14:57:26 +00:00