and outputing them in generated files.
Fixed a few other scanner bugs that for some reason didn't show up until
these modifications were made.
MFC after: 10 days
immediate value or the accumulator. 0 is the chip's internal
representation for the accumulator, and so 0 is an invalid immediate value
when the accumulator can also be specified as an argument.
Submitted by: gibbs
aicasm is run on the build machine and therefore needs to be
compiled and linked against the headers and libraries (resp)
of the build machine. Since normally the default include
directories are search after any specified on the command
line, make sure we don't accidentally pick up machine
dependent headers from the kernel compile directory by
specifying /usr/include first.
This solves the (cross) build problem for ia64.
Approved by: gibbs
Add support for constructing a table of critical section regions in
the firmware image. The kernel driver will soon have support for
single stepping the sequencer outside of a critical region prior
to starting exception handling.
other systems.
o Normalize copyright text.
o Clean up probe code function interfaces by passing around a single
structure of common arguments instead of passing "too many" args
in each function call.
o Add support for the AAA-131 as a SCSI adapter.
o Add support for the AHA-4944 courtesy of "Matthew N. Dodd" <winter@jurai.net
o Correct manual termination support for PCI cards. The bit definitions
for manual termination control in the SEEPROM were incorrect.
o Add support for extracting NVRAM information from SCB 2 for BIOSen
that use this mechanism to pass this data to OS drivers.
o Properly set the STPWLEVEL bit in PCI config space based on the
setting in an SEEPROM.
o Go back to useing 32byte SCBs for all controllers. The current
firmware allows us to embed 12byte cdbs on all controllers in
a 32byte SCB, and larger cdbs are rarely used, so it is a
better use of this space to offer more SCBs (32).
o Add support for U160 transfers.
o Add an idle loop executed during data transfers that prefetches
S/G segments on controllers that have a secondary DMA engine
(aic789X).
o Improve the performance of reselections by avoiding an extra
one byte DMA in the case of an SCB lookup miss for the reselecting
target. We now keep a 16byte "untagged target" array on the card
for dealing with untagged reselections. If the controller has
external SCB ram and can support 64byte SCBs, then we use an
"untagged target/lun" array to maximize concurrency. Without
external SCB ram, the controller is limited to one untagged
transaction per target, auto-request sense operations excluded.
o Correct the setup of the STPWEN bit in SXFRCTL1. This control
line is tri-stated until set to one, so set it to one and then
set it to the desired value.
o Add tagged queuing support to our target role implementation.
o Handle the common cases of the ignore wide residue message
in firmware.
o Add preliminary support for 39bit addressing.
o Add support for assembling on big-endian machines. Big-endian
support is not complete in the driver.
o Correctly remove SCBs in the waiting for selection queue when
freezing a device queue.
o Now that we understand more about the autoflush bug on the
aic7890, only use the workaround on devices that need it.
o Add a workaround for the "aic7890 hangs the system when you
attempt to pause it" problem. We can now pause the aic7890
safely regardless of what instruction it is executing.
aic7xxx.c:
Add a function for sucking firmware out of the controller
prior to reset.
Remove some inline bloat from functions that should not have
been inlined.
During initialization, wait 1ms after the chip reset before
touching any registers. You can get machine checks on certain
architectures (Atari I think?) without the delay.
Return CAM_REQ_CMP for external BDR requests instead
of CAM_BDR_SENT.
Bump some messages to bootverbose levels above 1.
Don't clear any negotiated sync rate if the target rejects
a WDTR message. The sync rate is only cleared if the target
accepts a WDTR message.
Fix a small bug in the mesgin handling code that could cause
us to believe that we had recieved a message that was actually
received by another target. This could only confuse us in
some very rare transmission negotiation scenarios.
Remove some unecessary cleanup of residual information after
a residual is reported. The sequencer does this when the
command is queued now.
Don't mess with the IRQMS bit in the host control register unless
we are an aic7770 chip.
Use calling context to determine if the card is already paused when
we update the target message request bit field in controller scratch
ram. Looking at the paused bit in the HCNTRL register opened up a
race condition.
Insert delays in the target message request update routine as a temporary
work around for what looks like a chip bug. I'm still investigating this
one.
Fix the Abort/Abort Tag/BDR handler to pull its message from the message
buffer in our softc instead of attempting to get it from a register on
the controller. The message is never recorded by the controller in the
new message scheme.
Don't rely on having an SCB when a BDR occurs. We can issue these during
invalid reconnects to.
Fix a few cases where we were restarting the sequencer but then still
falling out of a switch statement to unpause the sequencer again.
This could cause us to mess up sequencer state if it generated another
pausing interrupt between the time of the restart and unpause.
Kill the 'transceiver settle' loop during card initialization. I
failed to realize that a controller that is not connected to any
cables will never settle or enable the SCSI transceivers at all.
The correct solution is to monitor the IOERR interrupt which indicates
that the transceiver state has changed (UW<->LVD).
Modify the aic7xxx assembler to properly echo input when stdin is not
a tty.
reorganization in rev 1.16 of i386/include/types.h which changed
stdlib.h's use of <machine/types.h>. The problem was the -I. was causing
machine/types.h to come from the current kernel source, while stdlib.h was
coming from /usr/include. /usr/include/stdlib.h is as old as the last
'make world', the machine/types.h was as new as the current source.
is more robust and common code can be used for both the target and iniator
roles. The mechanism for tracking negotiation state has also been simplified.
Add support for sync/wide negotiation in target mode and fix many of
the target mode bugs running at higher speeds uncovered. Make a first
stab at getting all of the bus skew delays correct. Sync+Wide dataout
transfers still cause problems, but this may be an initiator problem.
Ensure that we exit BITBUCKET mode if the controller is restarted.
Add support for target mode only firmware downloads. This has been
tested on the aic7880, but should mean that we can perform target mode
on any aic7xxx controller. Mixed mode (initiator and target roles in
the same firmware load) is currently only supported on the aic7890, but
with optimization, may fit on chips with less instruction space.
- Convert to CAM
- Use a new DMA based queuing and paging scheme
- Add preliminary target mode support
- Add support for the aic789X chips
- Take advantage of external SRAM on more controllers.
- Numerous bug fixes and performance improvements.
operands that are set during seqeuncer program download instead of at
assembly time.
Convert the sequencer code to use" downloaded constants" for four run time
constants that vary depending on the board type. This frees up 4 bytes
of sequencer scratch ram space where these constants used to be stored and
also removes the additional instructions required to load their values
into the accumulator prior to using them.
Remove the REJBYTE sram variable. The host driver can just as easly
read the accumulator to get this value.
The scratch ram savings is important as the old code used to clober the
SCSICONF register on 274X cards which sits near the top of scratch ram
space. The SCSICONF register controls bus termination, and clobbering
it is not a good thing. Now we have 4 bytes to spare.
This should fix the reported problems with cards that don't have devices
attached to them failing with a stream of "Somone reset bus X" messages.
Doug Ledford determined the cause of the problem, fixes by me.
Be consistant about testing for parity errors after waiting for a
REQ on the bus.
Don't ack the last byte in a transaction until after we've cleared
all target state.
aic7xxx_asm.c:
Test the return value of getopt against -1 not EOF. (Yet another
shameless victum of the style guide being wrong).
Stick 4 more, twin channel only, instructions behind
.if ( TWIN_CHANNEL)
aic7xxx_asm.c:
Add the -O options which allows the specification of which options
to include in a program listing. This makes it possible to easily
determine the address of any instruction in the program across
different hardware/option configurations. Updated usage() as well.
New sequencer assembler for the aic7xxx adapters. This assembler
performs some amount of register type checking, allows bit
manipulation of symbolic constants, and generates "patch tables"
for conditionalized downloading of portions of the program.
This makes it easier to take full advantage of the different
features of the aic7xxx cards without imposing run time penalies
or being bound to the small memory footprints of the low end
cards for features like target mode.
aic7xxx.reg:
New, assembler parsed, register definitions fo the aic7xxx cards.
This was done primarily in anticipation of 7810 support which
will have a different register layout, but should be able to use
the same assembler. The kernel aic7xxx driver consumes a generated
file in the compile directory to get the definitions of the register
locations.
aic7xxx.seq:
Convert to the slighly different syntax of the new assembler.
Conditionalize SCB_PAGING, ultra, and twin features which shaves
quite a bit of space once the program is downloaded.
Add code to leave the selection hardware enabled during reconnects
that win bus arbitration. This ensures that we will rearbitrate
as soon as the bus goes free instead of delaying for a bit.
When we expect the bus to go free, perform all of the cleanup
associated with that event "up front" and enter a loop awaiting
bus free. If we see a REQ first, complain, but attempt to
continue. This will hopefully address, or at least help diagnose,
the "target didn't send identify" messages that have been reported.
Spelling corrections obtained from NetBSD.
This will make a number of things easier in the future, as well as (finally!)
avoiding the Id-smashing problem which has plagued developers for so long.
Boy, I'm glad we're not using sup anymore. This update would have been
insane otherwise.
Fix support for the aic7850 by looking only at the relavent bits of the
QINCNT. The 7850 puts random garbage in the high bits and all my attempts
to determine the cause of this failed. This approach does seem to work
around the problem.
Don't trust SCSIPERR to tell us when there is a parity error. On
some revs of the 7870 and the 7880, this bit follows the parity of
the current byte. Instead of using a SEQINT to tell the kernel,
re-enable the standard parity error interrupt since it seems to pause
the sequencer right at the time of the error which is the effect we were
looking for anyway.
aic7xxx_reg.h:
Remove PARITY_ERROR seqeuncer interrupt type, its no longer used.
Define QCOUNTMASK as the SRAM location for the mask to use on the
QINCNT register. QCOUNTMASK is determined by the number of SCBs
supported by the device we're working on.
aic7xxx_asm.c
Properly check the return value of fopen, and define the arg list
in getopt correctly.
Submitted by: Pete Bentley <pete@demon.net>
1) Use cpp to preprocess the sequencer code.
2) Convert all "magic numbers" to #defines shared by the sequencer and
kernel driver via the aic7xxx_reg.h file. (The assembler still needs
to be re-written in lex/yacc to allow ~|& type constructions).
3) Raise ATN on parity errors for "in" phases and send an initiator detected
error or message-in parity error message as appropriate.
4) Turn off the reselection hardware from the time or a (re)connection to
busfree. It seems that some fast targets were able to reconnect before
the sequencer was able to see busfree.
5) The message buffer is considered "in-use" when there is a positive length
count. The ACTIVE_MSG flag was unnecesary.
6) Properly set SCB_NEXT_WAITING to SCB_LIST_HEAD in scbs being added to
the waiting scb list. This is a change in how the list code works to
facilitate some planned work in the reset code.
7) The fields in the SCB have be re-arranged to be quad-word aligned.
8) The inb code has been rewritten to catch phasemisses and be more efficient.
9) Go back to "snooping the bus" to determine if the incomming identify
message will be followed by a simple queue message. Its much faster than
doing a search through the SCBs.
10) Implement better tag range checking for incomming tags.
11) Make sdtr_to_rate more accurate (use 25 instead of 24 in calculations -
must have been asleep that night).
12) Rearrange some routines to reduce code complexity and size.
13) Update comments and formatting.
14) Fixed bugs I've forgotten about??
Reviewed by: David Greenman <davidg@FreeBSD.org>
is identical to the older version, just the copyright has changed. Many
thanks go to Dean Gehnert of the Linux camp who went the extra mile to make
this happen.
Other changes:
Update assembler man page to include the -v and -D options
Merge in Dean's latest changes to the assembler
Have the sequencer do a MSG_REJECT when the negotiated syncronous rate
is lower than the adapter supports. This forces asyncronous mode which
is faster at these rates anyway.
This code will be moved shortly to the non-gpld portion of the tree.
- Report valid residual byte counts. We actually pause the sequencer
when the residual is non-zero. I thought about using DMA to do this,
bus sequencer program space is tight.
- Fix embarassing off by one error in the computation of a 2's
compliment variable. This was most likely the cause of the
many problems reported with the tagged queuing code.
- Handle "MAX_SYNC" as a special case (ie we are the ones starting
the sync negotiation sequence). This was done so that the target
scratch area can be initialed to 0 offset (asyncronous transfers)
safely. The initialization to 0 (was 15) is necessary since in
some cases a Wide negotiation could run into problems if SCSIRATE
was set wrong and we went into data(in/out).
- Trim the DMA routines a little by using some procedures. Net
effect is more functionality with 3 less instructions after this
update.
- Toggle the WIDEODD bit of the DFCNTRL whenever this is not the
last SG block. It has no effect in the 8bit bus configuration,
but in the Wide configuration ensures that the overlap byte is
held in the SCSI block if the transfer is odd so it will end
up in the next SG (the correct behavior).
