to the virtual one. I may had a reason at some point to use the later, but
can't remember which, and it can leads to issues.
Reported by: Guillaume Ballet <gballet gmail com>
as 'real memory' instead of Maxmem if the value is available.
Note amd64 displayed physmem as 'usable memory' since machdep.c r1.640
to unconfuse users. Now it is consistent across amd64 and i386 again.
While I am here, clean up smbios.c a bit and update copyright date.
Reviewed by: jhb
o Don't run through the register initialization in the read mac routine
for the AX88x90. It duplicates other stuff that we do.
o Eliminate the 10ms delay after we reset the AX88x90. We already wait for
the appropriate bits to indicate reset is done.
a device specific DMA tag. On amd64 it could exhaust all of bounce
pages when bus_dma_tag_create(9) is called at malo_pci_attach() then as
result in next turn it returns ENOMEM. This fix a attach fail on amd64.
Pointed by: yongari
Tested by: dchagin
MFC after: 3 days
It seems that RTL8168D and RTL8102EL requires additional settle
time to complete RL_PHYAR register write. Accessing RL_PHYAR
register right after the write causes errors for subsequent PHY
register accesses.
Tested by: george at luckytele dot com,
Steve Wills < STEVE at stevenwills dot com >
don't have one of the clock cycles (the turn cycle) that the AX88x90
chips have. Make this conditional. But this seems totally crazy and
can't possibly be right. Commit the fix for the moment until I can
explore this mystery more deeply.
On the plus side, the DL10022-based cards I have (D-Link DEF-670TXD
and SMC8040TX) work after this fix.
Add ch_suspend/ch_resume methods for PCI controllers and implement them
for AHCI. Refactor AHCI channel initialization according to it.
Fix Port Multipliers operation. It is far from perfect yet, but works now.
Tested with JMicron JMB363 AHCI + SiI 3726 PMP pair.
Previous version was also tested with SiI 4726 PMP.
Hardware sponsored by: Vitsch Electronics / VEHosting.nl
o call ieee80211_encap in ieee80211_start so frames passed down to drivers
are already encapsulated
o remove ieee80211_encap calls in drivers
o fixup wi so it recreates the 802.3 head it requires from the 802.11
header contents
o move fast-frame aggregation from ath to net80211 (conditional on
IEEE80211_SUPPORT_SUPERG):
- aggregation is now done in ieee80211_start; it is enabled when the
packets/sec exceeds ieee80211_ffppsmin (net.wlan.ffppsmin) and frames
are held on a staging queue according to ieee80211_ffagemax
(net.wlan.ffagemax) to wait for a frame to combine with
- drivers must call back to age/flush the staging queue (ath does this
on tx done, at swba, and on rx according to the state of the tx queues
and/or the contents of the staging queue)
- remove fast-frame-related data structures from ath
- add ieee80211_ff_node_init and ieee80211_ff_node_cleanup to handle
per-node fast-frames state (we reuse 11n tx ampdu state)
o change ieee80211_encap calling convention to include an explicit vap
so frames coming through a WDS vap are recognized w/o setting M_WDS
With these changes any device able to tx/rx 3Kbyte+ frames can use fast-frames.
Reviewed by: thompsa, rpaulo, avatar, imp, sephe
is set and "natd_enable" is NOT set;
- Accept and pass firewall type to the external firewall script.
Submitted by: Yuri Kurenkov < y -dot- kurenkov -at- init -dot- ru >
MFC after: 3 days
No response from: freebsd-rc
o Introduce new chip_type AX88790. There's a few places we need to know the
exact chip for workaronds.
o Explain the AX88190 workaround for the ISR bits being stuck, and don't
apply them to the AX88790. The datasheet says the bits are fixed, and
experience confirms.
o Fix mii bit-bang read code to read and discard the 'floating' bit.
o Remove empty ed_pccard_ax88x90_mii_reset routine
o Report error from mii_phy_probe
o Don't use ed_probe_Novel_generic for ax88x90 chips. It puts them into
an odd state sometimes. Instead, use a more stream-lined version that
avoids the trouble spots. This was copied and tweaked from the original.
o Move chip reset into its own routine.
o Minor code optimiation on getting MAC address
o Add code for coping with AX88790 cards that are in power down state and
need to be kicked before the PHY registers for the internal phy read right.
o Remove ugly cap of PHYs at 17.
o For AX88790, we need to set a special bit for accessig phy 16 (the internal
phy) and clear it for all others according to a chip erratum.
o streamline the bit-bang code for AX88x90: the delays aren't needed according
to the datasheet timing diagrams and also the Linux driver
o Fix minor bit definition for direction bit.
o Generally: Some comments reformatted
o Only try the toshiba probe on cards labelled as toshiba
# From another Akihabara card (this one from a few years ago from a
# friend in Japan). Fix the Corega FEther II PCC-TXD. This one is
# still on sale new, as of a few weeks ago. should fix all other AX88x90
# based cards, but I have some testing left to finish on my collection...
o PC98 uses 32-bit block numbers. Limit the scheme to 2^32-1
blocks when the media is larger. The 32-bit block numbers
are implicit (16-bit cylinder * 8-bit head * 8-bit sector).
o EBR uses 32-bit block numbers. Limit the scheme to 2^32-1
blocks when the media is larger.
o Calculate the number of entries based on the rounded media
size, rather than the raw media size.
