Commit Graph

657 Commits

Author SHA1 Message Date
Adrian Chadd
6ad02dbafe Add global TX timeout handling.
The global TX timeout counter increments whenever a frame is ready
to be transmitted and the medium is busy.
2011-04-18 12:15:43 +00:00
Adrian Chadd
d10f1cdc8c Mark the PHY as inactive before the chip is reset.
It's also marked inactive by the initvals, and enabled after
the baseband/PLL has been configured, but before the RF
registers have been programmed.

The origin and reason for this particular change is currently unknown.

Obtained from:	Linux ath9k
2011-04-17 13:46:13 +00:00
Adrian Chadd
b39c47d922 Don't do Kite antenna switch selection this way (for now); antenna
diversity is done elsewhere now.
2011-04-16 13:47:17 +00:00
Adrian Chadd
52d84465a2 Disable classic-style fast diversity on the AR5416 and later.
Antenna diversity on the >= AR5416 is implemented differently than the
AR5212 and previous chips. So for now, and not to confuse things, just
disable it for now.
2011-04-16 12:46:46 +00:00
Adrian Chadd
18a3a3309f Remove some duplicate code from the AR9285 TX power configuration path. 2011-04-16 11:59:37 +00:00
Adrian Chadd
235ab70e0a Add in the AR9285 (Kite) diversity to if_ath, enabling TX/RX antenna
diversity.

This is bit dirty and likely should be revised at a later date,
with an eye to unifying/tidying up the whole diversity setup
and allowing developers to do "tricky stuff" as they desire.
For now, this works.
2011-04-13 15:17:23 +00:00
Adrian Chadd
81484cdb07 Add in the last bit of the HAL support for Kite diversity.
* add a new method, specifically for doing per-RX packet
  antenna diversity
* set that HAL method only if it's Kite and a Kite chip that
  does diversity.
2011-04-13 15:12:48 +00:00
Adrian Chadd
1171c869d7 More kite diversity related changes.
* add a diversity flag to the HAL debugging section
* add a check to make sure the kite diversity code doesn't run
  on boards that don't require it, as not all Kite chips will
  implement it.
* add some debug statements when the diversity code makes
  changes to the antenna diversity/combining setup.
2011-04-13 15:08:51 +00:00
Adrian Chadd
ac27b8ff27 Change this to be less noisy. 2011-04-13 14:51:07 +00:00
Adrian Chadd
77823fbc2c Bring over the antenna diversity logic support for Kite.
Again, this is just the code ported from ath9k and included in the build,
it isn't yet enabled.
2011-04-13 11:32:15 +00:00
Adrian Chadd
c772d0204f Port over a TX gain fix from ath9k specific to the AR9285 (Kite) and AR9271.
Note: this HAL currently only supports the AR9285.

From Linux ath9k:

The problem is that when the attenuation is increased,
the rate will start to drop from MCS7 -> MCS6, and finally
will see MCS1 -> CCK_11Mbps. When the rate is changed b/w
CCK and OFDM, it will use register desired_scale to calculate
how much tx gain need to change.

The output power with the same tx gain for CCK and OFDM modulated
signals are different. This difference is constant for AR9280
but not AR9285/AR9271. It has different PA architecture
a constant. So it should be calibrated against this PA
characteristic.

The driver has to read the calibrated values from EEPROM and set
the tx power registers accordingly.
2011-04-13 04:40:59 +00:00
Adrian Chadd
6984989598 Add new fields to the v4k EEPROM modal header. 2011-04-13 03:05:42 +00:00
Adrian Chadd
132163b12f Add OS_REG_RMW, which mirrors ath9k's REG_RMW.
This macro does a read-modify-write pass with register bits to set and clear.
2011-04-13 03:05:15 +00:00
Adrian Chadd
1c554472de Add the initial AR9285 PHY glue for supporting antenna diversity.
This code isn't currently used anywhere; it's just linked into the build.
2011-04-13 02:40:45 +00:00
Adrian Chadd
a03467b1ba De-dup the ar5416 rates array definition. 2011-04-11 11:15:34 +00:00
Adrian Chadd
7ab2ab919c Fix the completely wrong types I used in the previous commit. 2011-04-08 08:49:50 +00:00
Adrian Chadd
82c30dc46e Begin fleshing out a public HAL routine to export the per-chain
ctl/ext noise floor values.

This routine doesn't check to see whether the radio is MIMO
capable - instead, it simply returns either the raw values,
the "nominal" values if the raw values aren't yet available
or are invalid, or '0' values if there's no valid channel/
no valid MIMO values.

Callers are expected to verify the radio is a MIMO radio
(which for now means it's an 11n chipset, there are non-11n
MIMO chipsets out there but I don't think we support them,
at least in MIMO mode) before exporting the MIMO values.
2011-04-08 07:44:00 +00:00
Adrian Chadd
f1ff114882 Export the per-chain ctl/ext noise floor values, raw and uncut, to the
upper-level HAL.

Right now the per-chain noise floor values aren't used anywhere in
the upper-level HAL, so the driver currently has no real reference
to compare the per-chain RSSI values to.

This is needed before per-chain RSSI values (for ctl and ext radios)
are can be thrown upstairs to the net80211 code.
2011-04-08 06:58:01 +00:00
Adrian Chadd
8cc7d3572f Extend the RX descriptor block to include two more EVM words.
This will be needed for later AR93xx/AR94xx 3-stream devices.
2011-04-08 06:29:41 +00:00
Adrian Chadd
5e7d0e6482 Add some more OS_MARK probes to the RX DMA setup/teardown code path.
I'm trying to debug the RX DMA path and help the ath9k guys with
"RX dma abort stuck" issue that both our drivers have.
2011-04-07 13:14:51 +00:00
Adrian Chadd
c5d5272355 Make the alq log path tunable 2011-04-05 16:14:54 +00:00
Adrian Chadd
74e3a02137 The xpaBiasLvlFreq[] fields in the modal header also need swapping
when the EEPROM contents are byte-swapped.
2011-04-05 13:14:17 +00:00
Adrian Chadd
9e9ae8e207 Commit missing bits from the last commit:
* add the hal capability flag
* make sure its disabled for the ar9280/ar9285.
2011-04-04 14:53:36 +00:00
Adrian Chadd
8a2a6beedb Add a HAL capability bit for supporting self-linked RX descriptors and disable it for the 11n chipsets.
From the ath9k source:

==

11N: we can no longer afford to self link the last descriptor.
MAC acknowledges BA status as long as it copies frames to host
buffer (or rx fifo). This can incorrectly acknowledge packets
to a sender if last desc is self-linked.

==

Since this is useful for pre-AR5416 chips that communicate PHY errors
via error frames rather than by on-chip counters, leave the support
in there, but disable it for AR5416 and later.
2011-04-04 14:52:31 +00:00
Adrian Chadd
efa7c2b36c At least set the coverage class value here; worry about populating the
register values at a later date.
2011-04-04 11:01:53 +00:00
Adrian Chadd
f90a170c46 I missed committing this last time - it's needed for the 5ghz fast clock calculation. 2011-04-03 20:15:41 +00:00
Adrian Chadd
97efbf40fc Add in the clock timing calculation when Merlin is using the 5ghz fast clock.
This is a 44mhz clock, not a 40mhz clock like normal for 5ghz operation.
2011-04-03 17:36:32 +00:00
Adrian Chadd
c55968698f Import a fix from the ath9k - reduce the TX FIFO size for Kite (AR9285.) 2011-04-03 12:02:49 +00:00
Adrian Chadd
3d45fa543f Add an explanation of the inivals 2011-04-03 11:59:52 +00:00
Adrian Chadd
634a6d0283 From ath9k - clear the RX descriptor status before recycling it. 2011-04-02 00:27:22 +00:00
Adrian Chadd
5d51c507d0 Add some more debugging 2011-04-02 00:24:13 +00:00
Adrian Chadd
b569f9f5df Introduce AH_AR5416_INTERRUPT_MITIGATION which enables interrupt mitigation for
the AR5416 and later. Rename the older HAL option to use this.
2011-03-31 08:48:05 +00:00
Adrian Chadd
dba9c85977 Break out the ath PCI logic into a separate device/module.
Introduce the AHB glue for Atheros embedded systems. Right now it's
hard-coded for the AR9130 chip whose support isn't yet in this HAL;
it'll be added in a subsequent commit.

Kernel configuration files now need both 'ath' and 'ath_pci' devices; both
modules need to be loaded for the ath device to work.
2011-03-31 08:07:13 +00:00
Adrian Chadd
f77057db08 According to ath9k recv.c, one shouldn't be doing self-linked descriptors
in the RX path when doing 11n and block-ack'ed frames. Apparently, the MAC
will loop over that self-linked descriptor and treat it as "good enough"
for (incorrectly!) ACKing the frames in the block-ack.

Until I figure out how to work around this issue in the future, this counter
will tell me if packet RX processing ever gets to the point where it's
touching the self-linked descriptor. If there's ever enough packets to get
to that point, BA's will be invalid and likely very unhappy.
2011-03-29 15:59:07 +00:00
Adrian Chadd
4f545a2c3d Add in HT protection but disable it by default.
I'll clear how it's supposed to work with Bernhard and then look
at enabling this in the correct situations.

But this -does- enable HT RTS protection (using the appropriate legacy
rates) if this bit of code is enabled.
2011-03-28 11:48:49 +00:00
Adrian Chadd
4aa18e9d93 Fix typo. 2011-03-27 10:35:39 +00:00
Adrian Chadd
8fd67f92b0 Rename AH_ENABLE_11N to ATH_ENABLE_11 - the HAL supports 11n by
default but the ath driver doesn't. This is a much more consistent
name.
2011-03-27 08:47:55 +00:00
Adrian Chadd
bb16aa8120 .. And another missed commit - add the PSPOLL capability. 2011-03-26 13:06:43 +00:00
Adrian Chadd
d2211b6a68 This was missing from the previous HAL commit - it fixes a typo and
introduces the PS-POLL hardware support.
2011-03-26 11:59:18 +00:00
Adrian Chadd
a74f5bf40c If 802.11n is enabled, bump the number of buffers used up to a larger
level.

This is important for AMPDU RX as each burst is multiple packets in a row.
2011-03-26 11:58:29 +00:00
Adrian Chadd
f378d4c804 Add in the hardware PS-POLL frame reception setting, but leave it disabled
by default.

Adventourous souls with an AR9220/AR9280 or later and who have a device
that sends PS-POLL frames may wish to try tinkering with this option and
get back to me.
2011-03-26 10:52:37 +00:00
Adrian Chadd
a0e1036046 Introduce hardware PS-POLL support in the HAL.
Linux ath9k only enables this for AR9280 and later NICs; so
create a capability for it so it isn't enabled for earlier
NICs.

Enabling hardware PS-POLL support will come in a later commit
and will be disabled by default.
2011-03-26 10:47:17 +00:00
Adrian Chadd
f95233b6f5 Put these two back to mirror what ath9k does.
Even though they map to setting the error filter register,
ath9k also writes them untouched to AR_RX_FILTER.

The Force-BSSID match bit can stay high, as it maps to a
misc mode register setting rather than an RX filter bit.
2011-03-26 07:29:48 +00:00
Adrian Chadd
8c98d9bae1 Shuffle around the HAL_RX_FILTER bits to be slightly more sensible.
The phyerr, radar and bssid-match bits aren't real bits, they map
to enabling bits in other registers. Move those out of the way of
valid RX filter bits.

Add a few new fields from ath9k - compba, ps-poll, mcast-bcast-all.
2011-03-26 07:15:35 +00:00
Adrian Chadd
532f24429c After discussing with Bernhard, the "right" way in net80211 to check
the channel width is ni->ni_chw, which is set to the negotiated channel
width. ni->ni_htflags is the capability, rather than the negotiated
value.

Teach both the TX path and the sample rate module about this.
2011-03-25 10:55:25 +00:00
Adrian Chadd
75f0fbfbbf I broke periodic adc calibrations - so restore them to working order. 2011-03-25 10:53:13 +00:00
Adrian Chadd
ab2e5836be Re-disable the setting of 2040/shortgi bits for now.
This seems to work fine for STA but not HT/20 AP mode.

Further discussion with net80211 people will need to take place
to ensure that the right flags are set based on the negotiated
capabilities of the remote peer, rather than whatever the local
parameters are.

Sending short-gi frames in 20mhz may work on some chips but
it certainly isn't supported on anything currently supported
by the HAL; and sending HT40 frames in HT20 mode just plain
won't work.
2011-03-25 04:15:30 +00:00
Adrian Chadd
7dd51df82f After discussion with Felix Fietkau (nbd) about the ath9k Merlin LNA bit
settings, it seems that our defines are backwards and don't match what
is in the EEPROM documentation or internal driver.

The ath9k code used to have a bitfield here, rather than a uint8_t, and
there were #defines used to swap the order based on the endian of the
platform - this wasn't because of nybble or bit ordering of the
underlying host but because of what the compiler was doing.

This may be the reason for the backwards field numbers, as ath9k had
similar issues.
2011-03-25 00:45:24 +00:00
Adrian Chadd
423c974c28 Flip ANI on for the AR5416 and later chips. I haven't verified it on
the AR9285 so I'll leave it off for that.

Ath9k sources indiciate that one of the ANI modes interferes with
RIFS detection, so match ath9k and disable that.
2011-03-25 00:40:08 +00:00
Adrian Chadd
24cfde2fc3 The right commit - add a couple more AR_PCU_MISC_MODE2 register bits -
SOWL specific.
2011-03-25 00:06:58 +00:00