Commit Graph

212 Commits

Author SHA1 Message Date
Luigi Rizzo
579a6e3c4e add netmap support for "em", "lem", "igb" and "re".
On my hardware, "em" in netmap mode does about 1.388 Mpps
on one card (on an Asus motherboard), and 1.1 Mpps on another
card (PCIe bus). Both seem to be NIC-limited, because
i have the same rate even with the CPU running at 150 MHz.

On the "re" driver the tx throughput is around 420-450 Kpps
on various (8111C and the like) chipsets. On the Rx side
performance seems much better, and i can receive the full
load generated by the "em" cards.

"igb" is untested as i don't have the hardware.
2011-12-05 15:33:13 +00:00
Pyun YongHyeon
6830588dd1 To save more power, switch to 10/100Mbps link when controller is
put into suspend/shutdown.  Old PCI controllers performed that
operation in firmware but for RTL8111C or newer controllers, it's
responsibility of driver.  It's not clear whether the firmware of
RTL8111B still downgrades its speed to 10/100Mbps so leave it as it
was.
2011-11-23 23:29:18 +00:00
Pyun YongHyeon
eef0e49628 Make sure to stop TX MAC before freeing queued TX frames.
For RTL8111DP, check if the TX MAC is active by reading RL_GTXSTART
register.  For RTL8402/8168E-VL/8168F/8411, wait until TX queue is
empty.
2011-11-23 22:07:13 +00:00
Pyun YongHyeon
fcb220acd1 Disable accepting frames in re_stop() to put RX MAC into idle state.
Because there is no reliable way to know whether RX MAC is in
stopped state, rejecting all frames would be the only way to
minimize possible races.
Otherwise it's possible to receive frames while stop command
execution is in progress and controller can DMA the frame to freed
RX buffer during that period.
This was observed on recent PCIe controllers(i.e. RTL8111F).

While this change may not be required on old controllers it
wouldn't make negative effects on old controllers.  One side effect
of this change is disabling receive so driver reprograms RL_RXCFG
to receive WOL frames when it is put into suspend or shutdown.

This should address occasional 'memory modified free' errors seen
on recent RealTek controllers.
2011-11-23 02:08:05 +00:00
Pyun YongHyeon
1662c49e56 Perform media change after setting IFF_DRV_RUNNING flag. Without it,
driver would ignore the first link state update if controller
already established a link such that it would have to take
additional link state handling in re_tick().
2011-11-22 23:27:59 +00:00
Pyun YongHyeon
44f7cbf586 Writing access to RL_CFG5 register also requires EEPROM write
access.
While I'm here, enable WOL through magic packet but disable waking
up system via unicast, multicast and broadcast frames.  Otherwise,
multicast or unicast frame(e.g. ICMP echo request) can wake up
system which is not probably wanted behavior on most environments.
This was not known as problem because RL_CFG5 register access had
not effect until this change.
The capability to wake up system with unicast/multicast frames
are still set in driver, default off, so users who need that
feature can still activate it with ifconfig(8).
2011-11-22 23:19:49 +00:00
Marius Strobl
4b7ec27007 - There's no need to overwrite the default device method with the default
one. Interestingly, these are actually the default for quite some time
  (bus_generic_driver_added(9) since r52045 and bus_generic_print_child(9)
  since r52045) but even recently added device drivers do this unnecessarily.
  Discussed with: jhb, marcel
- While at it, use DEVMETHOD_END.
  Discussed with: jhb
- Also while at it, use __FBSDID.
2011-11-22 21:28:20 +00:00
Pyun YongHyeon
d467ffaa66 Add preliminary support for RTL8168/8111F PCIe Gigabit ethernet.
H/W donated by:	RealTek Semiconductor Corp.
2011-11-17 22:07:50 +00:00
Pyun YongHyeon
6b0a8e0476 Add preliminary support for second generation RTL8105E PCIe
FastEthernet.

H/W donated by:	RealTek Semiconductor Corp.
2011-11-17 21:24:56 +00:00
Pyun YongHyeon
017f1c8db9 Disable PCIe ASPM (Active State Power Management) for all
controllers.
More and more RealTek controllers started to implement EEE feature.
Vendor driver seems to load a kind of firmware for EEE with
additional PHY fixups.  It is known that the EEE feature may need
ASPM support.  Unfortunately there is no documentation for EEE of
the controller so enabling ASPM may cause more problems.
2011-11-16 23:29:27 +00:00
Pyun YongHyeon
600af6c29b Add missing driver lock in SIOCSIFCAP handler. 2011-11-16 22:09:14 +00:00
Pyun YongHyeon
d56f7f5284 Add preliminary support for RTL8411 PCIe Gigabit ethernet with
integrated card reader.

H/W donated by:	RealTek Semiconductor Corp.
2011-11-16 22:05:38 +00:00
Pyun YongHyeon
a9e3362a07 Add preliminary support for RTL8402 PCIe FastEthernet with
integrated card reader.

H/W donated by:	RealTek Semiconductor Corp.
2011-11-16 21:37:45 +00:00
Marius Strobl
b303030684 Sprinkle some const. 2011-11-02 23:23:19 +00:00
Pyun YongHyeon
57c81d92ae Close a race where SIOCGIFMEDIA ioctl get inconsistent link status.
Because driver is accessing a common MII structure in
mii_pollstat(), updating user supplied structure should be done
before dropping a driver lock.

Reported by:	Karim (fodillemlinkarimi <> gmail dot com)
2011-10-17 19:49:00 +00:00
Pyun YongHyeon
caa19d50d1 Add new device id of D-Link DGE-530T Rev. C controller. DGE-503T
Rev A1 and B1 is supported by sk(4) but the DGE-530T Rev. C
controller is re-branded RealTek 8169 controller.

PR:	kern/159116
Approved by:	re (kib)
2011-07-30 01:06:12 +00:00
John Baldwin
3b0a4aef96 Do a sweep of the tree replacing calls to pci_find_extcap() with calls to
pci_find_cap() instead.
2011-03-23 13:10:15 +00:00
Pyun YongHyeon
39e692013a Add initial support for RTL8401E PCIe Fast Ethernet.
PR:	154789
2011-02-16 21:59:42 +00:00
Pyun YongHyeon
bc2a100257 Disable TX IP checksum offloading for RTL8168C controllers. The
controller in question generates frames with bad IP checksum value
if packets contain IP options.  For instance, packets generated by
ping(8) with record route option have wrong IP checksum value. The
controller correctly computes checksum for normal TCP/UDP packets
though.
There are two known RTL8168/8111C variants in market and the issue
I observed happened on RL_HWREV_8168C_SPIN2. I'm not sure
RL_HWREV_8168C also has the same issue but it would be better to
assume it has the same issue since they shall share same core.
RTL8102E which is supposed to be released at the time of
RTL8168/8111C announcement does not have the issue.

Tested by:	Konstantin V. Krotov ( kkv <> insysnet dot ru )
2011-02-04 17:49:55 +00:00
Pyun YongHyeon
54899a96e1 Add support for RTL8105E PCIe Fast Ethernet controller. It seems
the controller has a kind of embedded controller/memory and vendor
applies a large set of magic code via undocumented PHY registers in
device initialization stage. I guess it's a firmware image for the
embedded controller in RTL8105E since the code is too big compared
to other DSP fixups. However I have no idea what that magic code
does and what's purpose of the embedded controller. Fortunately
driver seems to still work without loading the firmware.

While I'm here change device description of RTL810xE controller.

H/W donated by:	Realtek Semiconductor Corp.
2011-01-26 21:14:20 +00:00
Pyun YongHyeon
502be0f749 Do not use interrupt taskqueue on controllers with MSI/MSI-X
capability. One of reason using interrupt taskqueue in re(4) was
to reduce number of TX/RX interrupts under load because re(4)
controllers have no good TX/RX interrupt moderation mechanism.
Basic TX interrupt moderation is done by hardware for most
controllers but RX interrupt moderation through undocumented
register showed poor RX performance so it was disabled in r215025.
Using taskqueue to handle RX interrupt greatly reduced number of
interrupts but re(4) consumed all available CPU cycles to run the
taskqueue under high TX/RX network load.  This can happen even with
RTL810x fast ethernet controller and I believe this is not
acceptable for most systems.

To mitigate the issue, use one-shot timer register to moderate RX
interrupts. The timer register provides programmable one-shot timer
and can be used to suppress interrupt generation. The timer runs at
125MHZ on PCIe controllers so the minimum time allowed for the
timer is 8ns. Data sheet says the register is 32 bits but
experimentation shows only lower 13 bits are valid so maximum time
that can be programmed is 65.528us. This yields theoretical maximum
number of RX interrupts that could be generated per second is about
15260. Combined with TX completion interrupts re(4) shall generate
less than 20k interrupts. This number is still slightly high
compared to other intelligent ethernet controllers but system is
very responsive even under high network load.

Introduce sysctl variable dev.re.%d.int_rx_mod that controls amount
of time to delay RX interrupt processing in units of us. Value 0
completely disables RX interrupt moderation. To provide old
behavior for controllers that have MSI/MSI-X capability, introduce
a new tunable hw.re.intr_filter. If the tunable is set to non-zero
value, driver will use interrupt taskqueue. The default value of
the tunable is 0. This tunable has no effect on controllers that
has no MSI/MSI-X capability or if MSI/MSI-X is explicitly disabled
by administrator.

While I'm here cleanup interrupt setup/teardown since re(4) uses
single MSI/MSI-X message at this moment.
2011-01-26 20:25:40 +00:00
Pyun YongHyeon
d180a66f19 Remove TX taskqueue and directly invoke re_start in interrupt task. 2011-01-25 23:27:28 +00:00
Pyun YongHyeon
4a58fd452a Prefer MSI-X to MSI on controllers that support MSI-X. All
recent PCIe controllers(RTL8102E or later and RTL8168/8111C or
later) supports either 2 or 4 MSI-X messages. Unfortunately vendor
did not publicly release RSS related information yet. However
switching to MSI-X is one-step forward to support RSS.
2011-01-25 22:18:00 +00:00
Pyun YongHyeon
f9ad4da76d Disable TSO for all Realtek controllers. Experimentation showed
RTL8111C generated corrupted frames where TCP option header was
broken. All other sample controllers I have did not show such
problem so it could be RTL8111C specific issue. Because there are
too many variants it's hard to tell how many controllers have such
issue. Just disable TSO by default but have user override it.
2011-01-25 19:05:46 +00:00
Pyun YongHyeon
7be4de2de7 Apply TX interrupt moderation to all RTL810xE PCIe Fast Ethernet
controllers. Experimentation with RTL8102E, RTL8103E and RTL8105E
showed dramatic decrement of TX completion interrupts under high TX
load(e.g.  from 147k interrupts/second to 10k interrupts/second)
With this change, TX interrupt moderation is applied to all
controllers except RTL8139C+.
2011-01-24 00:01:06 +00:00
Pyun YongHyeon
ef278cb4ae Change model names of controller RTL_HWREV_8168_SPIN[123] to real ones.
s/RL_HWREV_8168_SPIN1/RL_HWREV_8168B_SPIN1/g
s/RL_HWREV_8168_SPIN2/RL_HWREV_8168B_SPIN2/g
s/RL_HWREV_8168_SPIN3/RL_HWREV_8168B_SPIN3/g
No functional changes.
2011-01-18 00:46:10 +00:00
Pyun YongHyeon
81eee0ebf8 Implement initial jumbo frame support for RTL8168/8111 C/D/E PCIe
GbE controllers. It seems these controllers no longer support
multi-fragmented RX buffers such that driver have to allocate
physically contiguous buffers.

 o Retire RL_FLAG_NOJUMBO flag and introduce RL_FLAG_JUMBOV2 to
   mark controllers that use new jumbo frame scheme.
 o Configure PCIe max read request size to 4096 for standard frames
   and reduce it to 512 for jumbo frames.
 o TSO/checksum offloading is not supported for jumbo frames on
   these controllers. Reflect it to ioctl handler and driver
   initialization.
 o Remove unused rl_stats_no_timeout in softc.
 o Embed a pointer to structure rl_hwrev into softc to keep track
   of controller MTU limitation and remove rl_hwrev in softc since
   that information is available through a pointer to structure
   rl_hwrev.

Special thanks to Realtek for donating sample hardwares which made
this possible.

H/W donated by:	Realtek Semiconductor Corp.
2011-01-17 03:24:33 +00:00
Pyun YongHyeon
f0431c5bb0 Add initial support for RTL8168E/8111E-VL PCIe GbE.
H/W donated by:	Realtek Semiconductor Corp.
2011-01-17 02:23:50 +00:00
Pyun YongHyeon
4a814a5edb If driver is not able to allocate RX buffer, do not start driver.
While I'm here move RX buffer allocation and descriptor
initialization up to not touch hardware registers in case of RX
buffer allocation failure.
2011-01-13 23:15:09 +00:00
Pyun YongHyeon
9e18005d99 Make sure to check validity of dma maps before destroying. 2011-01-13 23:00:28 +00:00
Pyun YongHyeon
9325262669 re_reset() should be called only after setting device specific
features.
2011-01-13 22:52:57 +00:00
Pyun YongHyeon
d3b181ae81 Allow TX/RX checksum offloading to be configured independently. 2011-01-13 22:49:10 +00:00
Pyun YongHyeon
89feeee459 For re(4) controllers that uses new jumbo frame scheme(RTL8168C/D/E),
limit maximum RX buffer size to RE_RX_DESC_BUFLEN instead of
blindly configuring it to 16KB. Due to lack of documentation, re(4)
didn't allow jumbo frame on these controllers. However it seems
controller is confused with jumbo frame such that it can DMA the
received frame to wrong address instead of splitting it into
multiple RX buffers. Of course, this caused panic.

Since re(4) does not support jumbo frames on these controllers,
make controller drop frame that is longer than RE_RX_DESC_BUFLEN
sized frame. Fortunately RTL810x controllers, which do not support
jumbo frame, have no such issues but this change also limited
maximum RX buffer size allowed to RTL810x controllers. Allowing
16KB RX buffer for controllers that have no such capability is
meaningless.

MFC after:	3 days
2011-01-12 03:43:47 +00:00
Pyun YongHyeon
16a4824bf9 When driver is not running, do not send DUMP command to controller
and just show old (cached) values. Controller will not respond to
the command unless MAC is enabled so DUMP request for down
interface caused request timeout.
2011-01-10 23:47:11 +00:00
Pyun YongHyeon
d6d7d923ad Implement TSO on RealTek RTL8168/8111 C or later controllers.
RealTek changed TX descriptor format for later controllers so these
controllers require MSS configuration in different location of TX
descriptor. TSO is enabled by default for controllers that use new
descriptor format.
For old controllers, TSO is still disabled by default due to broken
frames under certain conditions but users can enable it.
Special thanks to Hayes Wang at RealTek.

MFC after:	2 weeks
2011-01-10 23:28:46 +00:00
Pyun YongHyeon
64436f6e91 Add flow control for all re(4) controllers. re(4) controllers do
not provide any MAC configuration interface for resolved flow
control parameters. There is even no register that configures water
mark which will control generation of pause frames.
However enabling flow control surely enhanced performance a lot.
2010-11-15 00:06:19 +00:00
Pyun YongHyeon
5e6906ee36 Only moderate TX completion interrupts. Relying on taskqueue to
suppress RX interrupts seems to give better RX performance than
RX interrupt moderation.
2010-11-09 01:52:09 +00:00
Pyun YongHyeon
483cc44070 Follow the lead of vendor's interrupt moderation mechanism.
It seems RTL8169/RTL8168/RTL810xE has a kind of interrupt
moderation mechanism but it is not documented at all. The magic
value dramatically reduced number of interrupts without noticeable
performance drops so apply it to all RTL8169/RTL8169 controllers.
Vendor's FreeBSD driver also applies it to RTL810xE controllers but
their Linux driver explicitly cleared the register, so do not
enable interrupt moderation for RTL810xE controllers.

While I'm here sort 8169 specific registers.

Obtained from:	RealTek FreeBSD driver
2010-11-08 21:50:50 +00:00
Pyun YongHyeon
2bc085c69c Reduce spin wait time consumed in GMII register access routine.
There were a couple of attempts in the past to reduce it since it
took more than 1ms. Because mii_tick() periodically polls link
status, waiting more than 1ms for each GMII register access was
overkill. Unfortunately all previous attempts were failed with
various ways on different controllers.
This time, add additional 20us dealy at the end of GMII register
access which seems to requirement of all RealTek controllers to
issue next GMII register access request. This is the same way what
Linux does.
2010-11-08 19:15:31 +00:00
Pyun YongHyeon
0534aae0ce Add simple MAC statistics counter reading support. Unfortunately
useful counters like rl_missed_pkts is 16 bits quantity which is
too small to hold meaningful information happened in a second. This
means driver should frequently read these counters in order not to
lose accuracy and that approach is too inefficient in driver's
view. Moreover it seems there is no way to trigger an interrupt to
detect counter near-full or wraparound event as well as lacking
clearing the MAC counters. Another limitation of reading the
counters from RealTek controllers is lack of interrupt firing at
the end of DMA cycle of MAC counter read request such that driver
have to poll the end of the DMA which is a time consuming process
as well as inefficient. The more severe issue of the MAC counter
read request is it takes too long to complete the DMA. All these
limitation made maintaining MAC counters in driver impractical. For
now, just provide simple sysctl interface to trigger reading the
MAC counters. These counters could be used to track down driver
issues. Users can read MAC counters maintained in controller with
the following command.
#sysctl dev.re.0.stats=1

While I'm here add check for validity of dma map and allocated
memory before unloading/freeing them.

Tested by:	rmacklem
2010-11-05 19:28:00 +00:00
Pyun YongHyeon
63472df74a style(9). 2010-11-05 18:24:50 +00:00
Pyun YongHyeon
4baa031067 Remove extra white spaces. 2010-11-05 18:23:43 +00:00
Pyun YongHyeon
66366ca4bf Enable 64bit DMA addressing for RTL810xE/RTL8168/RTL8111 PCIe
controllers. Some old PCI controllers may work with DAC but it was
known to be buggy so 64bit DMA addressing is used only on PCIe
controllers.
2010-11-05 18:19:54 +00:00
Marius Strobl
8e5d93dbb4 Convert the PHY drivers to honor the mii_flags passed down and convert
the NIC drivers as well as the PHY drivers to take advantage of the
mii_attach() introduced in r213878 to get rid of certain hacks. For
the most part these were:
- Artificially limiting miibus_{read,write}reg methods to certain PHY
  addresses; we now let mii_attach() only probe the PHY at the desired
  address(es) instead.
- PHY drivers setting MIIF_* flags based on the NIC driver they hang
  off from, partly even based on grabbing and using the softc of the
  parent; we now pass these flags down from the NIC to the PHY drivers
  via mii_attach(). This got us rid of all such hacks except those of
  brgphy() in combination with bce(4) and bge(4), which is way beyond
  what can be expressed with simple flags.

While at it, I took the opportunity to change the NIC drivers to pass
up the error returned by mii_attach() (previously by mii_phy_probe())
and unify the error message used in this case where and as appropriate
as mii_attach() actually can fail for a number of reasons, not just
because of no PHY(s) being present at the expected address(es).

Reviewed by:	jhb, yongari
2010-10-15 14:52:11 +00:00
Pyun YongHyeon
485d41c0a7 Don't change PCIe maximum read request size to 2048 on RTL810x
controllers. It caused device timeouts.

Reported by:	McLone < mclone <> gmail dot com >
Tested by:	McLone < mclone <> gmail dot com >
MFC after:	5 days
2010-05-07 23:05:27 +00:00
Pyun YongHyeon
d0c4515667 Add preliminary support for 8168E/8111E PCIe controller.
While I'm here simplify device description string.

Tested by:	Michael Beckmann < michael <> apfel dot de >
MFC after:	5 days
2010-04-09 22:50:28 +00:00
Pyun YongHyeon
ecafbbb5b9 Add TSO on VLANs. Because re(4) has a TSO limitation for jumbo
frame, make sure to update VLAN capabilities whenever jumbo frame
is configured.
While I'm here rearrange interface capabilities configuration. The
controller requires VLAN hardware tagging to make TSO work on VLANs
so explicitly check this requirement.
2010-02-22 18:51:14 +00:00
Pyun YongHyeon
02d77e455f Increase PCIe maximuim read request size to 2048. Because re(4) uses
Tx DMA burst size 2048, I beleive PCIe maximum read request size
also should match to the value of Tx DMA burst size. With this
change I can get more than 800Mbps for TCP bulk transfers.
Previously I was not able to get more than 700Mbps. If I enable TSO
it now shows 927Mbps.
2010-02-21 00:00:55 +00:00
Pyun YongHyeon
8281a098c6 Add initial support for RTL8103E PCIe fastethernet.
PR:	kern/142974
2010-01-27 17:49:27 +00:00
Pyun YongHyeon
01d1a6c355 Move interface reinitialization down after disabling WOL in resume
path.
2009-11-19 23:14:40 +00:00