Commit Graph

1280 Commits

Author SHA1 Message Date
Bjoern A. Zeeb
920b965865 MFp4 bz_ipv6_fast:
in_cksum.h required ip.h to be included for struct ip.  To be
  able to use some general checksum functions like in_addword()
  in a non-IPv4 context, limit the (also exported to user space)
  IPv4 specific functions to the times, when the ip.h header is
  present and IPVERSION is defined (to 4).

  We should consider more general checksum (updating) functions
  to also allow easier incremental checksum updates in the L3/4
  stack and firewalls, as well as ponder further requirements by
  certain NIC drivers needing slightly different pseudo values
  in offloading cases.  Thinking in terms of a better "library".

  Sponsored by:	The FreeBSD Foundation
  Sponsored by:	iXsystems

Reviewed by:	gnn (as part of the whole)
MFC After:	3 days
2012-05-24 22:00:48 +00:00
Alexander Motin
dc0aa406db MFprojects/zfsd:
Generalize and unify ses device description.
2012-05-24 11:20:51 +00:00
Adrian Chadd
2d269a1628 Enable the AR8316 switch on the routerstation pro board.
The configuration is:

* RGMII, both ports
* arge0 - connected to PHY4 as a dedicated port (CPU port)
* arge1 - connected to the switch ports

I've verified this on my routerstation pro board.
2012-05-19 20:11:18 +00:00
Adrian Chadd
c7551b8b46 Remove duplicate config bits.
Submitted by:	juli
2012-05-12 19:43:22 +00:00
Adrian Chadd
0d96099845 Revert this - I disabled it whilst hwpmc is/was broken. 2012-05-12 17:42:22 +00:00
Adrian Chadd
1111c8313a Flip on WN1043ND switch PHY support.
* Add the i2c bitbang bus;
* Add the etherswitch/rtl8366rb drivers;
* "fix" the USB GPIO configuration so USB actually works.

Submitted by:	Stefan Bethke <stb@lassitu.de>
2012-05-12 17:41:42 +00:00
Adrian Chadd
9d9690e93b Now that there's a hint for it, add a "I'm an AR7240 switch!" hint. 2012-05-12 05:27:14 +00:00
Adrian Chadd
f7c03fa47d Add in the AP93 configuration file.
The AP93 has:

* AR7240 - mips24k processor with integrated 10/100 switch and
  various other peripherals;
* AR9283 - 2x2 2.4GHz 802.11n (with calibration data in flash);
* 64MB RAM;
* 16MB SPI flash.

The switch code detects as an AR8216 at the present moment, which isn't
_entirely_ strictly true.  However, the MII/MDIO routing in AP93.hints
works - the arge0 MAC connects to PHY4 in the switch, but via the
switch internal MDIO bus.  The switch connects to arge0's MDIO bus,
but only to export the switch registers.

Thanks to stb and ray for the switch work, and ray for helping determine
what the correct switch hints should be for this thing.
2012-05-12 04:52:59 +00:00
Adrian Chadd
411477c533 Add switch support to AP96. 2012-05-11 21:13:43 +00:00
Juli Mallett
0c8da0be6e Add basic SMP support for GXemul. Ideally we would have some way to override
some of the IPI mechanisms used by the common MIPS SMP code so we could use
the multicast IPI facilities, on GXemul as well as on several real hardware
platforms, and the ability to have multiple hard IPI types.
2012-05-07 04:36:48 +00:00
Juli Mallett
bd6c6f4249 Add a trivial driver for the GXemul Ethernet device. Probably quite buggy and
certainly non-optimal, but enough for basic networking use.

Requested by:	rwatson
2012-05-07 04:15:46 +00:00
Juli Mallett
ffbec96825 Add a driver for the GXemul test machine's disk controller and disk devices.
Prefer it to using an md device in the GXEMUL kernel configuration.

Requested by:	rwatson, theraven
2012-05-06 08:28:08 +00:00
Juli Mallett
a0f00447fb Get the memory size from the gxemul mp device. Don't dump the environment if
it is not present.
2012-05-06 05:58:56 +00:00
Adrian Chadd
6632cb429f Disable setting the MII port speed.
This seems to break at least my test board here (AR71xx + AR8316 switch
PHY).  Since I do have a whole sleuth of "normal" PHY boards (with
an AR71xx on a normal PHY port), I'll do some further testing with those
to determine whether this is a general issue, or whether it's limited
to the behaviour of the "fake" dedicated PHY port mode on these atheros
switches.
2012-05-04 02:26:15 +00:00
Adrian Chadd
b846389100 In the new world order, multiphy is now when the phymask is 0x0.
This makes the TP-WN1043ND (ar913x based) work again.
2012-05-03 07:48:19 +00:00
Adrian Chadd
ce3c177ff8 Fix a totally bone-headed, last minute bounds check snafu that somehow
I must've missed when booting a test kernel.

This has been validated on the AR7161.
2012-05-03 05:52:39 +00:00
Bjoern A. Zeeb
4c95ae1b74 Catch-up with r232853 and remove platform APIs which are not used by any
code and which had only stub implementations or no implementation on all
platforms.  Makes gxemul compile.

Hinted by:	rwatson
MFC after:	3 weeks
X-MFC by:	rwatson:
2012-05-02 14:38:43 +00:00
Robert Watson
fe62958717 mips/mips64eb became mips/mips64 while I wasn't looking (whoops), so update
GXEMUL kernel config for the new world order.

Spotted by:	bz
MFC after:	3 weeks
2012-05-02 12:15:34 +00:00
Robert Watson
e36985c9aa Clean up various aspects of the MIPS generic busspace implementation:
1) Always implement missing bus space methods using a panic() stub rather
   than a NULL pointer.  This appeared not to trip up any existing device
   drivers, but due to the nature of the devices I'm supporting locally,
   I'm making use of some of the more obscure busspace methods, and
   panic() is a preferred failure mode.  For example, do this for the
   setregion methods.

2) Hook up several existing busspace method implementations that were
   provided in the file, but not actually present in the methods
   structure.  Especially, single-byte bus I/O routines.  This should
   allow bugs to be fixed in the Atheros 802.11 driver.

There are still some remaining unimplemented methods that would be
desirable to implement -- especially, 64-bit I/O calls that would
observably accelerate device performance on FPGA-based soft CPU cores
that are typically clocked an order of magnitude slower than
conventional hard core CPUs, but that remains for another day.

MFC after:	3 weeks
Discussed with:	jmallett, scottl
Sponsored by:	DARPA, AFRL
2012-05-02 08:23:53 +00:00
Robert Watson
79ee9286f2 Merge a rudimentary gxemul "oldtestmips" port. This consists almost
entirely of one machdep file lifted from the MALTA port, as well as
a low-level console and tty driver for the gxemul debugging console
device (the emulators stdio).  As with many low-level embedded and
hypervisor console devices, it is polled only, so we drive TTY I/O
from a callout; we are perhaps a bit too aware of the MIPS physical
maps in order to attach the console before newbus comes to life.

The sample kernel configuration depends on an MD-based root file
system, which is not provided.  However, any 64-bit, big-endian
userspace image (such as one generated for MALTA) should work.

This will hopefully be supplemented by additional device drivers for
gxemul-specific hardware simulations from Juli Mallett.  We have
found oldtestmips quite useful for testing and improving aspects of
the MIPS port, so it's worth supporting better in FreeBSD.

Requested by:	theraven, jmallett
Sponsored by:	DARPA, AFRL
MFC after:	3 weeks
2012-05-02 08:10:15 +00:00
Adrian Chadd
337ef3cad0 Implement PLL configuration override support, similar to what openwrt
implements.
2012-05-02 07:43:11 +00:00
Adrian Chadd
ceec92152b Disable the pll_1000 hint for now, the upcoming work enables it and it
breaks without the switch PHY code.
2012-05-02 07:41:26 +00:00
Adrian Chadd
7a1e9887de * Force the ethernet MII configuration to be RGMII
* Populate the "pll_1000" field, which will soon be used to override the
  PLL configuration from the default value.

Obtained from:	Linux OpenWRT
2012-05-02 06:19:26 +00:00
Adrian Chadd
f014aaebdf Allow the MII mode to be overridden via 'hint.arge.X.miimode'.
It takes a number at the moment, rather than a string.

Some of the Linux board configurations specify the MII mode explicitly.
2012-05-02 06:18:12 +00:00
Adrian Chadd
8b73bee2d3 Add a missing newline. 2012-05-02 06:17:16 +00:00
Adrian Chadd
23ec80a3da Further ar71xx MII support improvements.
* Flesh out the PLL configuration fetch function, which will return the PLL
  configuration based on the unit number and speed.
* Remove the PLL speed config logic from the AR71xx/AR91xx chip PLL config
  function - pass in a 'pll' value instead.
* Modify arge_set_pll() to:
  + fetch the PLL configuration
  + write the PLL configuration
  + update the MII speed configuration.

This will allow if_arge to override the PLL configuration as required.

Obtained from:	Linux/Atheros/OpenWRT
2012-05-02 04:51:43 +00:00
Adrian Chadd
da88453012 MII related infrastructure changes.
* Add a new method to set the MII mode - GMII, RGMII, RMII, MII.
  + arge0 supports all four (two for non-Gige interfaces.)
  + arge1 only supports two (one for non-gige interfaces.)
* Set the MII clock speed when changing the MAC PLL speed.
  + Needed for AR91xx and AR71xx; not needed for AR724x.

Tested:

* AR71xx only, I'll do AR913x testing tonight and fix whichever issues
  creep up.

TODO:

* Implement the missing AR7242 arge0 PLL configuration, but don't
  adjust the MII speed accordingly.
* .. the AR7240/AR7241 don't require this, so make sure it's not set
  accidentally.

Bugs (not fixed here):

* Statically configured arge speeds are still broken - investigate why
  that is on the AP96 board.  Autonegotiate is working fine, but there
  still seems to be an occasionally heavy packet loss issue.

Obtained from: Linux/Atheros/OpenWRT
2012-05-02 01:21:57 +00:00
Adrian Chadd
784bcea8a9 Introduce an enum which encapsulates the PHY interface types that can be
configured.
2012-05-02 01:14:15 +00:00
Adrian Chadd
a2ebf5ddb1 Add in the MII configuration parameters for the AR71xx.
Obtained from:	Linux/OpenWRT
2012-05-01 20:32:38 +00:00
Adrian Chadd
e4b7508aad Convert AP96 to use the mdioproxy and ARGE_MDIO option.
arge1 still works (it's the standalone PHY) but arge0 and the other switch
ports don't work.  They're enumerated though, demonstrating that the
mdiobus abstraction is correctly working.
2012-05-01 06:21:02 +00:00
Adrian Chadd
72b9c70e36 Break out the arge MDIO bus code into an optional argemdio device.
This is only done if the ARGE_MDIO option is included.

* Shuffle the arge MDIO bus into a separate device, that needs to be
  probed early (use hint.argemdio.X.order=0)
* hint.arge.X.mdio now specifies which miiproxy to rendezvous with.
* Call MAC/MDIO bus init during MDIO attach, not arge attach.

This is done regardless:

* Shift the arge MAC and MDIO bus reset code into separate functions
  and call it early during MDIO bus attach.  It's required for
  correct MDIO bus IO to occur on AR71xx/AR91xx devices.

* Remove the AR71xx/AR91xx centric assumption that there's only one
  MDIO bus.  The initial code mapped miibus0(arge0) and miibus1(arge1)
  MII register operations to the MII0 (arge0) register space.  The
  AR724x (and later, upcoming chipsets) have two MDIO busses and
  the second is very much in use.

TODO:

* since the multiphy behaviour has changed (where now a phymask of >1
  PHY will still be enumerated), multiphy setups may be quite wrong.
  I'll go and fix these so they still have a chance of working, at least.
  until the switch PHY support appears in -HEAD.

Submitted by:	Stefan Bethke <stb@lassitu.de>
2012-05-01 06:18:30 +00:00
Adrian Chadd
03cb2eedfd Migrate ARGE_DEBUG to opt_arge.h.
Submitted by:	Stefan Bethke <stb@lassitu.de>
2012-05-01 04:35:53 +00:00
Dimitry Andric
460378bf13 Add a convenience macro for the returns_twice attribute, and apply it to
the prototypes of the appropriate functions (getcontext, savectx,
setjmp, sigsetjmp and vfork).

MFC after:	2 weeks
2012-04-29 11:04:31 +00:00
Adrian Chadd
1d0e8a50a0 Allow for MIPS devices to have a specific probe/attach order.
The default priority is now '1000' rather than '0'.  This may cause some
unforseen regressions.

Submitted by:	Stefan Bethke <stb@lassitu.de>
Reviewed by:	imp
2012-04-21 04:17:30 +00:00
Adrian Chadd
15a353ce97 Allow for a default GPIO pin "high", which is required for some boards
which tie the USB device enable to a GPIO line.

Submitted by:	Stefan Bethke <stb@lassitu.de>
2012-04-20 22:44:00 +00:00
Adrian Chadd
b50d8083ab Introduce the matching PCI ath(4) fixup code from ar71xx_pci into
ar724x_pci.c.

* Move out the code which populates the firmware into ar71xx_fixup.c
* Shuffle around the ar724x fixup code to match what the ar71xx fixup
  code does.

I've validated this on an AR7240 with AR9285 on-board NIC. It doesn't
yet load, as the AR9285 EEPROM code needs to be made "flash aware."

TODO:

* Validate that I haven't broken AR71xx
* Test AR9285/AR9287 onboard NICs, complete with EEPROM code changes
* Port over the needed BAR hacks for AR7240, AR7241 and AR7242 from
  Linux OpenWRT.  The current WAR has only been tested on the AR7240
  and I'm not sure the way the BAR register is treated is "right".
  The "fixup" method here is right when setting the BAR for local access -
  ie, the BAR address is either 0xffff (AR7240) or 0x1000ffff (AR7241/AR7242),
  but the ath9k-fixup.c code (Linux OpenWRT) does this when setting the
  initial "fixup" BAR.  It then restores the original BAR.
  I'll have to read the ar724x PCI bus glue to see what other special cases
  await.
2012-04-20 08:26:05 +00:00
Adrian Chadd
93f5997b8c Style(9) and white space fixes. 2012-04-17 01:34:49 +00:00
Adrian Chadd
3f08db2e79 Protect the PCI space registers behind a mutex.
Obtained from:	Linux/OpenWRT, Atheros
2012-04-17 01:22:59 +00:00
Adrian Chadd
468d6f48b3 Add in the AP96 phy configuration from openwrt.
* arge0 doesn't (yet) work via the switch PHY ports; I'm not sure why.
* arge1 maps to the WAN port. That works.

TODO:

* The PLL register needs a different (non-default) value for Gigabit
  Ethernet.  The board setup code needs to be extended a bit to allow
  for non-default pll_1000 values - right now, those values come out
  of hard-coded values in the per-chip set_pll_ge() routines.

Obtained from:	Linux / OpenWRT
2012-04-15 22:59:56 +00:00
Adrian Chadd
5fdb2379cb The AR913x MII speed configuration matches the AR71xx MII configuration.
So share the code.

Don't do it for the AR724x - that has a completely different set of PLL
and MII configuration parameters.
2012-04-15 22:34:22 +00:00
Adrian Chadd
bf9abaa954 Fix the mask logic when reading PCI configuration space registers. 2012-04-15 02:38:01 +00:00
Adrian Chadd
c4b28bdc27 Flesh out the rest of the AP96 board/config. 2012-04-13 20:23:32 +00:00
Adrian Chadd
d591b27dbc * Enable ATH_EEPROM_FIRMWARE, now that it's a compile time option
* Tidy up things a bit.
2012-04-13 18:01:53 +00:00
Adrian Chadd
2c61ba4db2 These are uboot, so mark them as such or booting from flash will not work. 2012-04-13 08:56:23 +00:00
Adrian Chadd
3a8a3eebfd Introduce configuration files for AP94 and AP96.
This uses the new firmware(9) method for squirreling away the EEPROM
contents from SPI flash so ath(4) can get to them later.

It won't work out of the box just yet - you have to add this to
if_ath_pci.c:

#define ATH_EEPROM_FIRMWARE

.. until I've added it as a configuration option and updated things.
2012-04-13 08:52:25 +00:00
Adrian Chadd
8f7015e205 (ab)Use the firmware API to store away EEPROM calibration data for
future use by the ath(4) driver.

These embedded devices put the calibration/PCI bootstrap data on the
on board SPI flash rather than on an EEPROM connected to the NIC.
For some boards, there's two NICs and two sets of EEPROM data in the
main SPI flash.

The particulars:

* Introduce ath_fixup_size, which is the size of the EEPROM area in
  bytes.
* Create a firmware image with a name based on the PCI device identifier
  (bus/slot/device/function).
* Hide some verbose debugging behind 'bootverbose'.

ath(4) can then use this to load in the EEPROM data.

This requires AR71XX_ATH_EEPROM to be defined.
2012-04-13 08:45:50 +00:00
Adrian Chadd
8a138d80d0 Remove an unused variable. Grr. 2012-04-13 06:13:37 +00:00
Adrian Chadd
be94a28e2a Sync this code against what's in OpenWRT trunk.
* the openwrt code doesn't treat 0/0/0 any differently
  from other bus/slot/func combinations.
* A "local write" function writes to the LCONF area, and
  so I've added it.
* The PCI workaround at attach time uses this LCONF code,
  which it already did ..
* .. but it is a 4 byte write, not a 2 byte write.
  Even though it's PCIR_COMMAND which is a two byte PCI register.

Tested on:	AR7161
TODO:		The other two AR71xx derivatives
TODO:		More thoroughly stare at the datasheets I do have
		and if it indeed is incorrect, push fixes to both
		FreeBSD and Linux/OpenWRT.

Obtained from:	Linux OpenWRT
2012-04-13 06:11:24 +00:00
Jayachandran C.
2323b34a2d Reinstate the XTLB handler for CPU_NLM and CPU_RMI
These platforms set the KX bit even when booted in 32 bit mode. So
the XLTB handler is needed even when __mips_n64 is not defined.
2012-04-02 11:41:33 +00:00
John Baldwin
5e1a7cc71e Use VM_MEMATTR_UNCACHEABLE for the constant for UC memory rather than
VM_MEMATTR_UNCACHED.  VM_MEMATTR_UNCACHEABLE is the constant other
platforms use.

MFC after:	2 weeks
2012-03-29 16:48:36 +00:00