d/freebsd-dev
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
218,860 Commits 72 Branches 135 Tags 3.2 GiB
570afb920c
Commit Graph

32 Commits

Author SHA1 Message Date
Emmanuel Vadot
338af8a097 Allwinner clk: factor M for mod clock is 4 bits, not 5 
MFC after:	1 week
 2016-12-22 15:01:06 +00:00
Emmanuel Vadot
1e64280173 Honor the CLK_SET_DRYRUN for the *set_freq function for allwinner clocks. 
Reviewed by:	jmcneill
MFC after:	1 month
Differential Revision:	https://reviews.freebsd.org/D8821
 2016-12-16 21:58:48 +00:00
Emmanuel Vadot
def44246f2 PLL3 have a fractional mode where an explicit frequency (297Mhz or 270) 
can be selected for it. If the desired frequency is one of those two, use
this mode instead of the integer one.
When calculating the PLL3 freq for the dotclock, check if it is a multiple
of the fracional frequencies.

MFC after:	2 weeks
 2016-11-26 10:36:48 +00:00
Jared McNeill
02b2e3c5fb Allow the MMC frequency to be set up to 52MHz for MMC high speed timings. 2016-11-15 23:46:01 +00:00
Emmanuel Vadot
51503e707b Upstream DTS provides PLL3 and PLL7 nodes (and their x2 form), 
so remove them from our DTS and adapt the code to handle them correctly.
This fix HDMI video on A20.
 2016-11-15 07:08:33 +00:00
Andrew Turner
df7675353e Stop including fdt_common.h from the arm code when it's unneeded. 
Sponsored by:	ABT Systems Ltd
 2016-11-14 11:41:22 +00:00
Emmanuel Vadot
328dd395ba Do not fail to attach the clock if we cannot set the assigned parents as this 
property isn't mandatory.

MFC after:	2 weeks
 2016-11-08 10:06:43 +00:00
Emmanuel Vadot
e3454ae8b3 For AHB clock we need to set the assigned parents for cpufreq(4) to work. 
MFC after:	2 weeks
 2016-11-04 17:13:47 +00:00
Jared McNeill
5f7cfb6035 Add support for H3 PLL2 (PLL_Audio). 2016-11-02 23:49:57 +00:00
Jared McNeill
8c07f7653a The DTS may report fewer than 4 parents for a module clock. Avoid setting 
the module clock parent to an out-of-range index in these cases.
 2016-11-02 23:46:23 +00:00
Andrew Turner
87e1355ba5 Define the Allwinner PLL FDT constants in the file that uses them rather 
than including a file from under sys/gnu.

Sponsored by:	DARPA, AFRL
 2016-10-26 14:09:30 +00:00
Emmanuel Vadot
1535414c25 The only consumer of pll1 is the CPU clock, we don't need to set it glitch free. 
Reported by:	jmcneill
MFC after:	1 week
 2016-10-26 08:47:35 +00:00
Emmanuel Vadot
6a9f23793d allwinner A10 Pll1 allow changing freq 
PLL1 is used by the cpu core, allowing changing freq is needed for cpufreq.
The factors table contains all the frequencies in the operating point table
present in the DTS.

MFC after:	1 week
 2016-10-25 15:21:08 +00:00
Jared McNeill
3c6a684c11 Match "allwinner,sun8i-h3-apb0-gates-clk" compatible string. 2016-10-15 13:27:01 +00:00
Jared McNeill
2ee32f3c7f Provide a complete A23 PLL1 factor table, from 60MHz to 1872MHz. 2016-10-15 12:23:54 +00:00
Jared McNeill
b78c83e321 Add support for Allwinner A83T CPU frequency scaling. 2016-09-07 01:10:16 +00:00
Jared McNeill
a995bf1b7d Add support for Allwinner H3 PLL_CPUX. 
The H3 PLL_CPUX register looks exactly like the one found in A23, but we
need to follow a specific protocol when making adjustments to the clock.
 2016-09-05 12:36:54 +00:00
Jared McNeill
4e7f43bab6 Add support for the Allwinner H3 Thermal Sensor Controller. The H3 embeds 
a single thermal sensor located in the CPU.
 2016-09-05 11:05:14 +00:00
Jared McNeill
d69d5ab04f Add support for Allwinner A64 thermal sensors. 2016-09-03 15:26:00 +00:00
Jared McNeill
1396b52e55 Add support for changing A23 PLL1 frequency. 2016-09-01 21:20:07 +00:00
Jared McNeill
7f4b51c6f0 Add support for Allwinner A64 PLL_PERIPH0/PLL_PERIPH1 and PLL_HSIC clocks. 
Reviewed by:	andrew, manu
 2016-08-25 10:29:41 +00:00
Jared McNeill
30a0ebdb1c Switch parent clock when setting frequency if a new parent is a better 
candidate for the target rate.

Reviewed by:	andrew, manu
 2016-08-25 10:27:22 +00:00
Jared McNeill
1ff131af88 Add support for Allwinner multi-parent bus gates. 
Reviewed by:	andrew, manu
 2016-08-25 10:24:14 +00:00
Emmanuel Vadot
d00d8ed84f Rename allwinner_machdep.{c.h} to aw_machdep.{c.h} as all allwinner source 
files are name aw_*
 2016-08-17 21:44:02 +00:00
Jared McNeill
814f548cd5 H3/A83T: Use PLL_PERIPH/2 for AHB2 parent clock. 
Reviewed by:	manu
 2016-07-13 20:44:02 +00:00
Michal Meloun
dac935533b EXTRES: Add OF node as argument to all <foo>_get_by_ofw_<bar>() functions. 
In some cases, the driver must handle given properties located in
specific OF subnode. Instead of creating duplicate set of function, add
'node' as argument to existing functions, defaulting it to device OF node.

MFC after: 3 weeks
 2016-07-10 18:28:15 +00:00
Emmanuel Vadot
356c50adff Add support for Allwinner A13. 
Reviewed by:	jmcneill
Relnotes:	yes
Differential Revision:	https://reviews.freebsd.org/D6809
 2016-07-08 23:38:25 +00:00
Oleksandr Tymoshenko
39a997283f Use OF_prop_free instead of direct call to free(9) 
Approved by:	jmcneill
 2016-05-13 22:28:02 +00:00
Emmanuel Vadot
0aa4b81381 Add support for Allwinner H3 SoC. 
For now clocks, GPIO, Pinmux, UART, MMC, EHCI is supported.
Tested on OrangePi-One

Reviewed by:	jmcneill
Approved by:	cognet (mentor)
Differential Revision:	https://reviews.freebsd.org/D6311
 2016-05-13 18:20:54 +00:00
Jared McNeill
8a0fd1a7cd Add support for the Allwinner A83T (sun8iw6p1) SoC. 
Clocks, GPIO, UART, SD card / eMMC, USB, watchdog, and ethernet are
supported. Note that the A83T contains two clusters of four Cortex-A7
CPUs, and only CPUs in first cluster are started for now.

Tested on a Sinovoip Banana Pi BPI-M3.
 2016-05-05 09:41:57 +00:00
Jared McNeill
39fe39bca9 Fix calculation of LCD CH1 SCLK1 output frequency when SCLK2 /2 is used 
as source.

PR:		208680
Reported by:	David Binderman <dcb314@hotmail.com>
 2016-04-26 12:36:12 +00:00
Jared McNeill
6a05f063ed Convert Allwinner port to extres clk/hwreset/regulator APIs. 
Reviewed by:		andrew, gonzo, Emmanuel Vadot <manu@bidouilliste.com>
Approved by:		gonzo (mentor)
Differential Revision:	https://reviews.freebsd.org/D5752
 2016-04-06 23:11:03 +00:00