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6 Commits

Author SHA1 Message Date
Sean Bruno
3f929d8cdd Update hwpmc to support the Xeon class of Ivybridge processors. 
case 0x3E:      /* Per Intel document 325462-045US 01/2013. */

Add manpage to document all the goodness that is available in this
processor model.

No support for uncore events at this time.

Submitted by:	hiren panchasara <hiren.panchasara@gmail.com>
Reviewed by:	davide, jimharris, sbruno
Obtained from:	Yahoo! Inc.
MFC after:	2 weeks
 2013-01-31 22:09:53 +00:00
Sean Bruno
cdfd0cc862 Cleanup and rename some variables in libpmc and hwpmc. 
Submitted by:	hiren panchasara <hiren.panchasara@gmail.com>
Reviewed by:	jimharris@ sbruno@
Obtained from:	Yahoo! Inc.
MFC after:	2 weeks
 2012-10-24 01:26:29 +00:00
Sean Bruno
29f79bb342 Update man page crossreferences to sandybridge xeon class 
MFC after:	2 weeks
 2012-10-19 17:21:10 +00:00
Joel Dahl
4c7c24efe0 Remove trailing whitespace. 2012-09-06 19:24:48 +00:00
Joel Dahl
a619d8f7a1 Minor mdoc fix. 2012-09-06 19:14:02 +00:00
Fabien Thomas
1e862e5ad0 Add Intel Ivy Bridge support to hwpmc(9). 
Update offcore RSP token for Sandy Bridge.
Note: No uncore support.

Will works on Family 6 Model 3a.

MFC after: 1 month
Tested by: bapt, grehan
 2012-09-06 13:54:01 +00:00