Commit Graph

13 Commits

Author SHA1 Message Date
Fabien Thomas
2aef9dd6d3 Fix invalid class removal when IAF is not the last class.
Keep IAF class with 0 PMC and change the alias in libpmc to IAP.

MFC after:	1 week
2010-09-05 13:31:14 +00:00
George V. Neville-Neil
ee6a02813b Make sure that we clear the correct bits when we turn off
a PMC.  It was possible that we could have turned a bit on but
never cleared it.

Extend the calls to rdmsr() to all necessary functions, not
just those which previously caused a panic.

Pointed out by: jhb@
MFC after:	1 week
2010-07-29 17:52:23 +00:00
George V. Neville-Neil
f4a9c30419 Fix a panic brought about by writing an MSR without a proper mask.
All of the necessary wrmsr calls are now preceded by a rdmsr
and we leave the reserved bits alone.
Document the bits in the relevant registers for future reference.

Tested by:	mdf
MFC after:	1 week
2010-07-13 19:37:45 +00:00
Fabien Thomas
5d0848e9c6 - Fix a typo OFFCORE_REQUESTS.ANY.RFO is B0H10H and not 80H10H.
- Enable missing PARTIAL_ADDRESS_ALIAS for Core i7.

MFC after: 3 days
2010-04-15 19:45:03 +00:00
Fabien Thomas
1fa7f10bac - Support for uncore counting events: one fixed PMC with the uncore
domain clock, 8 programmable PMC.
- Westmere based CPU (Xeon 5600, Corei7 980X) support.
- New man pages with events list for core and uncore.
- Updated Corei7 events with Intel 253669-033US December 2009 doc.
  There is some removed events in the documentation, they have been
  kept in the code but documented in the man page as obsolete.
- Offcore response events can be setup with rsp token.

Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
Joseph Koshy
8ca7958478 * Support the L1D_CACHE_LD event on Core2 processors.
* Correct a group of typos: for Core2 programmable events, check
  user supplied umask values against the correct event descriptor
  field.

Submitted by:	Ryan Stone <rysto32 at gmail dot com>
2009-12-26 14:39:23 +00:00
Joseph Koshy
27be5d5888 Only claim that the PMC_CLASS_IAF PMCs are supported by a CPU if
there are PMCs on the CPU that belong to the class.

Review and testing by:	fabient
2009-10-24 01:58:10 +00:00
George V. Neville-Neil
2e7de50933 Add counters for the i7 architecture which were accidentally left
out of the original commit of i7 support.  These are all the counters
on pages A-32 and A-33 of the _Intel(R) 64 and IA32 Architectures
Software Developer's Manual Vol 3B_, June 2009.  Almost all
of these counters relate to operations on the L2 cache.

Reviewed by:	jkoshy
MFC after:	1 month
2009-09-01 17:55:37 +00:00
John Baldwin
21157ad3b1 Adjust the handling of the local APIC PMC interrupt vector:
- Provide lapic_disable_pmc(), lapic_enable_pmc(), and lapic_reenable_pmc()
  routines in the local APIC code that the hwpmc(4) driver can use to
  manage the local APIC PMC interrupt vector.
- Do not enable the local APIC PMC interrupt vector by default when
  HWPMC_HOOKS is enabled.  Instead, the hwpmc(4) driver explicitly
  enables the interrupt when it is succesfully initialized and disables
  the interrupt when it is unloaded.  This avoids enabling the interrupt
  on unsupported CPUs which may result in spurious NMIs.

Reported by:	rnoland
Reviewed by:	jkoshy
Approved by:	re (kib)
MFC after:	2 weeks
2009-08-14 21:05:08 +00:00
Jeff Roberson
597979c4b7 - Add support for nehalem/corei7 cpus. This supports all of the core
counters defined in the reference manual.  It does not support the
   'uncore' events.

Reviewed by:	jkoshy
Sponsored by:	Nokia
2009-01-27 07:29:37 +00:00
Joseph Koshy
8d8b174004 Bug fixes:
- Initialize variables before use.
- Remove a KASSERT() that could falsely trigger if there are other sources
  of NMIs in the system.

Efficiency tweak:
- When checking PMCs that overflowed, ignore PMCs that were not configured for
  sampling.
2008-12-16 11:04:02 +00:00
Joseph Koshy
b4d091f3a4 Fixes for Core2 Extreme support.
Submitted by:	 "Artem Belevich" <artemb at gmail dot com>
2008-12-03 17:30:36 +00:00
Joseph Koshy
0cfab8ddc1 - Add support for PMCs in Intel CPUs of Family 6, model 0xE (Core Solo
and Core Duo), models 0xF (Core2), model 0x17 (Core2Extreme) and
  model 0x1C (Atom).

  In these CPUs, the actual numbers, kinds and widths of PMCs present
  need to queried at run time.  Support for specific "architectural"
  events also needs to be queried at run time.

  Model 0xE CPUs support programmable PMCs, subsequent CPUs
  additionally support "fixed-function" counters.

- Use event names that are close to vendor documentation, taking in
  account that:
  - events with identical semantics on two or more CPUs in this family
    can have differing names in vendor documentation,
  - identical vendor event names may map to differing events across
    CPUs,
  - each type of CPU supports a different subset of measurable
    events.

  Fixed-function and programmable counters both use the same vendor
  names for events.  The use of a class name prefix ("iaf-" or
  "iap-" respectively) permits these to be distinguished.

- In libpmc, refactor pmc_name_of_event() into a public interface
  and an internal helper function, for use by log handling code.

- Minor code tweaks: staticize a global, freshen a few comments.

Tested by:	gnn
2008-11-27 09:00:47 +00:00