Commit Graph

18 Commits

Author SHA1 Message Date
Marius Strobl
ab00a509ee o Don't allocate resources for SDMA in sdhci(4) if the controller or the
front-end doesn't support SDMA or the latter implements a platform-
  specific transfer method instead. While at it, factor out allocation
  and freeing of SDMA resources to sdhci_dma_{alloc,free}() in order to
  keep the code more readable when adding support for ADMA variants.

o Base the size of the SDMA bounce buffer on MAXPHYS up to the maximum
  of 512 KiB instead of using a fixed 4-KiB-buffer. With the default
  MAXPHYS of 128 KiB and depending on the controller and medium, this
  reduces the number of SDHCI interrupts by a factor of ~16 to ~32 on
  sequential reads while an increase of throughput of up to ~84 % was
  seen.

  Front-ends for broken controllers that only support an SDMA buffer
  boundary of a specific size may set SDHCI_QUIRK_BROKEN_SDMA_BOUNDARY
  and supply a size via struct sdhci_slot. According to Linux, only
  Qualcomm MSM-type SDHCI controllers are affected by this, though.

  Requested by: Shreyank Amartya (unconditional bump to 512 KiB)

o Introduce a SDHCI_DEPEND macro for specifying the dependency of the
  front-end modules on the sdhci(4) one and bump the module version
  of sdhci(4) to 2 via an also newly introduced SDHCI_VERSION in order
  to ensure that all components are in sync WRT struct sdhci_slot.

o In sdhci(4):
  - Make pointers const were applicable,
  - replace a few device_printf(9) calls with slot_printf() for
    consistency, and
  - sync some local functions with their prototypes WRT static.
2018-12-30 23:08:06 +00:00
Marius Strobl
f5d03775e0 For consistency within the front-end, prefer SDHCI_{READ,WRITE}_{2,4}()
to sdhci_acpi_{read,write}_{2,4}() in the sdhci_acpi_set_uhs_timing()
added in r340543.
2018-11-19 23:56:33 +00:00
Marius Strobl
835998c210 Add a quirk handling for AMDI0040 controllers allowing them to do HS400.
Submitted by:	Shreyank Amartya (original version)
2018-11-18 00:52:27 +00:00
Takanori Watanabe
5efca36fbd Distinguish _CID match and _HID match and make lower priority probe
when _CID match.

Reviewed by: jhb, imp
Differential Revision:https://reviews.freebsd.org/D16468
2018-10-26 00:05:46 +00:00
Oleksandr Tymoshenko
2a99321a57 [sdhci] Add ACPI identifier for AMD eMMC 5.0 controller
Submitted by:	Rajesh Kumar <rajfbsd@gmail.com>
Approved by:	re (rgrimes)
Differential Revision:	https://reviews.freebsd.org/D17189
2018-09-29 00:35:36 +00:00
Marius Strobl
aafdd1d65a The broken DDR52 support of Intel Bay Trail eMMC controllers rumored
in the commit log of r321385 has been confirmed via the public VLI54
erratum. Thus, stop advertising DDR52 for these controllers.
Note that this change should hardly make a difference in practice as
eMMC chips from the same era as these SoCs most likely support HS200
at least, probably even up to HS400ES.
2018-05-14 21:46:06 +00:00
Marius Strobl
7fcf47802a - Check the slot type capability, set SDHCI_SLOT_{EMBEDDED,NON_REMOVABLE}
for embedded slots. Fail in the sdhci(4) initialization for slot type
  shared, which is completely unsupported by this driver at the moment. [1]
  For Intel eMMC controllers, taking the embedded slot type into account
  obsoltes setting SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE so remove these quirk
  entries.
- Hide the 1.8 V VDD capability when the slot is detected as non-embedded,
  as the SDHCI specification explicitly states that 1.8 V VDD is applicable
  to embedded slots only. [2]
- Define some easy bits of the SDHCI specification v4.20. [3]
- Don't leak bus_dma(9) resources in failure paths of sdhci_init_slot().

Obtained from:	DragonFlyBSD 65704a46 [1], 7ba10b88 [2], 0df14648 [3]
2017-07-26 22:04:23 +00:00
Marius Strobl
aca38eab8a o Add support for eMMC HS200 and HS400 bus speed modes at 200 MHz to
sdhci(4), mmc(4) and mmcsd(4). For the most part, this consists of:
  - Correcting and extending the infrastructure for negotiating and
    enabling post-DDR52 modes already added as part of r315598. In
    fact, HS400ES now should work as well but hasn't been activated
    due to lack of corresponding hardware.
  - Adding support executing standard SDHCI initial tuning as well
    as re-tuning as required for eMMC HS200/HS400 and the fast UHS-I
    SD card modes. Currently, corresponding methods are only hooked
    up to the ACPI and PCI front-ends of sdhci(4), though. Moreover,
    sdhci(4) won't offer any modes requiring (re-)tuning to the MMC/SD
    layer in order to not break operations with other sdhci(4) front-
    ends. Likewise, sdhci(4) now no longer offers modes requiring the
    set_uhs_timing method introduced in r315598 to be implemented/
    hooked up (previously, this method was used with DDR52 only, which
    in turn is only available with Intel controllers so far, i. e. no
    such limitation was necessary before). Similarly for 1.2/1.8 V VCCQ
    support and the switch_vccq method.
  - Addition of locking to the IOCTL half of mmcsd(4) to prevent races
    with detachment and suspension, especially since it's required to
    immediately switch away from RPMB partitions again after an access
    to these (so re-tuning can take place anew, given that the current
    eMMC specification v5.1 doesn't allow tuning commands to be issued
    with a RPMB partition selected). Therefore, the existing part_mtx
    lock in the mmcsd(4) softc is additionally renamed to disk_mtx in
    order to denote that it only refers to the disk(9) half, likewise
    for corresponding macros.

  On the system where the addition of DDR52 support increased the read
  throughput to ~80 MB/s (from ~45 MB/s at high speed), HS200 yields
  ~154 MB/s and HS400 ~187 MB/s, i. e. performance now has more than
  quadrupled compared to pre-r315598.

  Also, with the advent of (re-)tuning support, most infrastructure
  necessary for SD card UHS-I modes up to SDR104 now is also in place.
  Note, though, that the standard SDHCI way of (re-)tuning is special
  in several ways, which also is why sending the actual tuning requests
  to the device is part of sdhci(4). SDHCI implementations not following
  the specification, MMC and non-SDHCI SD card controllers likely will
  use a generic implementation in the MMC/SD layer for executing tuning,
  which hasn't been written so far, though.

  However, in fact this isn't a feature-only change; there are boards
  based on Intel Bay Trail where DDR52 is problematic and the suggested
  workaround is to use HS200 mode instead. So far exact details are
  unknown, however, i. e. whether that's due to a defect in these SoCs
  or on the boards.

  Moreover, due to the above changes requiring to be aware of possible
  MMC siblings in the fast path of mmc(4), corresponding information
  now is cached in mmc_softc. As a side-effect, mmc_calculate_clock(),
  mmc_delete_cards(), mmc_discover_cards() and mmc_rescan_cards() now
  all are guaranteed to operate on the same set of devices as there no
  longer is any use of device_get_children(9), which can fail in low
  memory situations. Likewise, mmc_calculate_clock() now longer will
  trigger a panic due to the latter.

o Fix a bug in the failure reporting of mmcsd_delete(); in case of an
  error when the starting block of a previously stored erase request
  is used (in order to be able to erase a full erase sector worth of
  data), the starting block of the newly supplied bio_pblkno has to be
  returned for indicating no progress. Otherwise, upper layers might
  be told that a negative number of BIOs have been completed, leading
  to a panic.

o Fix 2 bugs on resume:
  - Things done in fork1(9) like the acquisition of an SX lock or the
    sleepable memory allocation are incompatible with a MTX_DEF taken.
    Thus, mmcsd_resume() must not call kproc_create(9), which in turn
    uses fork1(9), with the disk_mtx (formerly part_mtx) held.
  - In mmc_suspend(), the bus is powered down, which in the typical
    case of a device being selected at the time of suspension, causes
    the device deselection as part of the bus acquisition by mmc(4) in
    mmc_scan() to fail as the bus isn't powered up again before later
    in mmc_go_discovery(). Thus, power down with the bus acquired in
    mmc_suspend(), which will trigger the deselection up-front.

o Fix a memory leak in mmcsd_ioctl() in case copyin(9) fails. [1]

o Fix missing variable initialization in mmc_switch_status(). [2]

o Fix R1_SWITCH_ERROR detection in mmc_switch_status(). [3]

o Handle the case of device_add_child(9) failing, for example due to
  a memory shortage, gracefully in mmc(4) and sdhci(4), including not
  leaking memory for the instance variables in case of mmc(4) (which
  might or might not fix [4] as the latter problem has been discovered
  independently).

o Handle the case of an unknown SD CSD version in mmc_decode_csd_sd()
  gracefully instead of calling panic(9).

o Again, check and handle the return values of some additional function
  calls in mmc(4) instead of assuming that everything went right or mark
  non-fatal errors by casting the return value to void.

o Correct a typo in the Linux IOCTL compatibility; it should have been
  MMC_IOC_MULTI_CMD rather than MMC_IOC_CMD_MULTI.

o Now that we are reaching ever faster speeds (more improvement in this
  regard is to be expected when adding ADMA support to sdhci(4)), apply
  a few micro-optimizations like predicting mmc(4) and sdhci(4) debugging
  to be off or caching erase sector and maximum data sizes as well support
  of block addressing in mmsd(4) (instead of doing 2 indirections on every
  read/write request for determining the maximum data size for example).

Reported by:	Coverity
CID:		1372612 [1], 1372624 [2], 1372594 [3], 1007069 [4]
2017-07-23 16:11:47 +00:00
Warner Losh
a94a63f0a6 An MMC/SD/SDIO stack using CAM
Implement the MMC/SD/SDIO protocol within a CAM framework. CAM's
flexible queueing will make it easier to write non-storage drivers
than the legacy stack. SDIO drivers from both the kernel and as
userland daemons are possible, though much of that functionality will
come later.

Some of the CAM integration isn't complete (there are sleeps in the
device probe state machine, for example), but those minor issues can
be improved in-tree more easily than out of tree and shouldn't gate
progress on other fronts. Appologies to reviews if specific items
have been overlooked.

Submitted by: Ilya Bakulin
Reviewed by: emaste, imp, mav, adrian, ian
Differential Review: https://reviews.freebsd.org/D4761

merge with first commit, various compile hacks.
2017-07-09 16:57:24 +00:00
Marius Strobl
806202b507 - Unlike as in the PCI case, when attached to ACPI, Intel Bay Trail
and Braswell eMMC and SDXC controllers share the same IDs. Like in
  the PCI case, Braswell eMMC needs the SDHCI_QUIRK_DATA_TIMEOUT_1MHZ
  quirk (see r311794 for the corresponding change to the sdhci(4) PCI
  PCI front-end), though. However, due to the shared ACPI IDs, this
  is trickier to do.
- Intel Apollo Lake eMMC and SDXC controllers are affected by the
  APL18 ("Using 32-bit Addressing Mode With SD/eMMC Controller May
  Lead to Unpredictable System Behavior") silicon bug [1]. When this
  erratum hits, typically both SDHCI and XHCI controllers wedge.
  According to Intel, using ADMA2 with 64-bit addressing and 96-bit
  descriptors serves as a workaround. Until such times when sdhci(4)
  has ADMA2 support, flag DMA as broken for affected interfaces.
  This turns out to work around the problem, too, at the cost of
  performance.
- In the sdhci(4) ACPI front-end, probe the Intel Apollo Lake eMMC
  and SDXC controllers, too.

1: http://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/pentium-celeron-n-series-j-series-datasheet-spec-update.pdf
2017-05-14 21:33:01 +00:00
Marius Strobl
0f34084f95 o Add support for eMMC DDR bus speed mode at 52 MHz to sdhci(4) and
mmc(4). For the most part, this consists of support for:
  - Switching the signal voltage (VCCQ) to 1.8 V or (if supported
    by the host controller) to 1.2 V,
  - setting the UHS mode as appropriate in the SDHCI_HOST_CONTROL2
    register,
  - setting the power class in the eMMC device according to the
    core supply voltage (VCC),
  - using different bits for enabling a bus width of 4 and 8 bits
    in the the eMMC device at DDR or higher timings respectively,
  - arbitrating timings faster than high speed if there actually
    are additional devices on the same MMC bus.

  Given that support for DDR52 is not denoted by SDHCI capability
  registers, availability of that timing is indicated by a new
  quirk SDHCI_QUIRK_MMC_DDR52 and only enabled for Intel SDHCI
  controllers so far. Generally, what it takes for a sdhci(4)
  front-end to enable support for DDR52 is to hook up the bridge
  method mmcbr_switch_vccq (which especially for 1.2 V signaling
  support is chip/board specific) and the sdhci_set_uhs_timing
  sdhci(4) method.

  As a side-effect, this change also fixes communication with
  some eMMC devices at SDR high speed mode with 52 MHz due to
  the signaling voltage and UHS bits in the SDHCI controller no
  longer being left in an inappropriate state.

  Compared to 52 MHz at SDR high speed which typically yields
  ~45 MB/s with the eMMC chips tested, throughput goes up to
  ~80 MB/s at DDR52.

  Additionally, this change already adds infrastructure and quite
  some code for modes up to HS400ES and SDR104 respectively (I did
  not want to add to much stuff at a time, though). Essentially,
  what is still missing in order to be able to activate support
  for these latter is is support for and handling of (re-)tuning.

o In sdhci(4), add two tunables hw.sdhci.quirk_clear as well as
  hw.sdhci.quirk_set, which (when hooked up in the front-end)
  allow to set/clear sdhci(4) quirks for debugging and testing
  purposes. However, especially for SDHCI controllers on the
  PCI bus which have no specific support code so far and, thus,
  are picked up as generic SDHCI controllers, hw.sdhci.quirk_set
  allows for setting the necessary quirks (if required).

o In mmc(4), check and handle the return values of some more
  function calls instead of assuming that everything went right.
  In case failures actually are not problematic, indicate that
  by casting the return value to void.

Reviewed by:	jmcneill
2017-03-19 23:27:17 +00:00
Marius Strobl
c11bbc7dab Again, fixes regarding style(4), to comments, includes and unused
parameters.
2017-03-17 22:57:37 +00:00
Marius Strobl
72dec0792a - Add support for eMMC "partitions". Besides the user data area, i. e.
the default partition, eMMC v4.41 and later devices can additionally
  provide up to:
  1 enhanced user data area partition
  2 boot partitions
  1 RPMB (Replay Protected Memory Block) partition
  4 general purpose partitions (optionally with a enhanced or extended
    attribute)

  Of these "partitions", only the enhanced user data area one actually
  slices the user data area partition and, thus, gets handled with the
  help of geom_flashmap(4). The other types of partitions have address
  space independent from the default partition and need to be switched
  to via CMD6 (SWITCH), i. e. constitute a set of additional "disks".

  The second kind of these "partitions" doesn't fit that well into the
  design of mmc(4) and mmcsd(4). I've decided to let mmcsd(4) hook all
  of these "partitions" up as disk(9)'s (except for the RPMB partition
  as it didn't seem to make much sense to be able to put a file-system
  there and may require authentication; therefore, RPMB partitions are
  solely accessible via the newly added IOCTL interface currently; see
  also below). This approach for one resulted in cleaner code. Second,
  it retains the notion of mmcsd(4) children corresponding to a single
  physical device each. With the addition of some layering violations,
  it also would have been possible for mmc(4) to add separate mmcsd(4)
  instances with one disk each for all of these "partitions", however.
  Still, both mmc(4) and mmcsd(4) share some common code now e. g. for
  issuing CMD6, which has been factored out into mmc_subr.c.

  Besides simply subdividing eMMC devices, some Intel NUCs having UEFI
  code in the boot partitions etc., another use case for the partition
  support is the activation of pseudo-SLC mode, which manufacturers of
  eMMC chips typically associate with the enhanced user data area and/
  or the enhanced attribute of general purpose partitions.

  CAVEAT EMPTOR: Partitioning eMMC devices is a one-time operation.

- Now that properly issuing CMD6 is crucial (so data isn't written to
  the wrong partition for example), make a step into the direction of
  correctly handling the timeout for these commands in the MMC layer.
  Also, do a SEND_STATUS when CMD6 is invoked with an R1B response as
  recommended by relevant specifications. However, quite some work is
  left to be done in this regard; all other R1B-type commands done by
  the MMC layer also should be followed by a SEND_STATUS (CMD13), the
  erase timeout calculations/handling as documented in specifications
  are entirely ignored so far, the MMC layer doesn't provide timeouts
  applicable up to the bridge drivers and at least sdhci(4) currently
  is hardcoding 1 s as timeout for all command types unconditionally.
  Let alone already available return codes often not being checked in
  the MMC layer ...

- Add an IOCTL interface to mmcsd(4); this is sufficiently compatible
  with Linux so that the GNU mmc-utils can be ported to and used with
  FreeBSD (note that due to the remaining deficiencies outlined above
  SANITIZE operations issued by/with `mmc` currently most likely will
  fail). These latter will be added to ports as sysutils/mmc-utils in
  a bit. Among others, the `mmc` tool of the GNU mmc-utils allows for
  partitioning eMMC devices (tested working).

- For devices following the eMMC specification v4.41 or later, year 0
  is 2013 rather than 1997; so correct this for assembling the device
  ID string properly.

- Let mmcsd.ko depend on mmc.ko. Additionally, bump MMC_VERSION as at
  least for some of the above a matching pair is required.

- In the ACPI front-end of sdhci(4) describe the Intel eMMC and SDXC
  controllers as such in order to match the PCI one.
  Additionally, in the entry for the 80860F14 SDXC controller remove
  the eMMC-only SDHCI_QUIRK_INTEL_POWER_UP_RESET.

OKed by:	imp
Submitted by:	ian (mmc_switch_status() implementation)
2017-03-16 22:23:04 +00:00
Marius Strobl
55dae242e6 Add and use a MMC_DECLARE_BRIDGE macro for declaring mmc(4) bridges
as kernel drivers and their dependency onto mmc(4); this allows for
incrementing the mmc(4) module version but also for entire omission
of these bridge declarations for mmccam(4) in a single place, i. e.
in dev/mmc/bridge.h.
2017-03-07 22:42:44 +00:00
Marius Strobl
b440e965da o Another round fixes for mmc(4), mmcsd(4) and sdhci(4) regarding
comments, marking unused parameters as such, style(9), whitespace,
  etc.
o In the mmc(4) bridges and sdhci(4) (bus) front-ends:
  - Remove redundant assignments of the default bus_generic_print_child
    device method (I've whipped these out of the tree as part of r227843
    once, but they keep coming back ...),
  - use DEVMETHOD_END,
  - use NULL instead of 0 for pointers.
o Trim/adjust includes.
2017-03-06 23:47:59 +00:00
Oleksandr Tymoshenko
3bd0d6b434 [sdhci_acpi] Add support for Bay Trail SDHC SD card slot
Add ACPI device 80860F14 with _UID 3 to the list of known devices. It
make SD card available on NUCs and Minnowboard. Previously added _UID 1
covered only eMMC devices.

Reported by:	kib@
MFC after:	1 week
2017-02-14 00:04:36 +00:00
Marius Strobl
1bacf3be8c Fix overly long lines, whitespace and other bugs according to style(9). 2017-01-29 00:05:49 +00:00
Oleksandr Tymoshenko
e5d519fdbc [sdhci] Add ACPI platform support for SDHCI driver
- Create ACPI version of SDHCI attach/detach/accessors logic. Some
    platforms (e.g. BayTrail-based Minnowboard) expose SDHCI devices
    via ACPI, not PCI
- Add sdchi_acpi kernel module

Reviewed by:	ian, imp
MFC after:	1 week
Differential Revision:	https://reviews.freebsd.org/D9112
2017-01-11 01:53:54 +00:00