driver's i/o ops must be locked to avoid chaos. Extend the cambria
bus tag to support ata and add a spin lock. The ata driver is
hacked to use that instead of it's builtin hack for ixp425. Once
the ata driver is fixed to not be confused about byte order we can
generalize the cambria bus tag code and make it generally useful.
While here take advantage of our being ixp435-specific to remove
delays when switching between byte+word accesses and to eliminate
the 2us delay for the uarts (the spin lock overhead looks to do
this for us).
o recognize ixp435 cpu
o change memory layout for for ixp4xx to not assume memory is aliases
to 0x10000000 (Cambria/ixp435 memory starts at zero)
o handle 64 irqs for ixp435
o dual EHCI USB 2.0 controller integral to ixp435
o overhaul NPE code for ixp435 and better MAC+MII naming
o updated NPE firmware (including NPE-A image for ixp435/ixp465)
o Gateworks Cambria board support:
- IDE compact flash
- MCU
- front panel LED on i2c bus
- Octal LED latch
Sanity-tested with NFS-root on Avila and Cambria boards. Requires
pending boot2 mods for CF-boot on Cambria.
the alternate status and the control registers. Remove the local
version of ata_reset.
Add support for the ADI Pronghorn Metro boards. They use CS3 and CS4
instead of Avila's CS1 and CS2.
OKed by: sam, cognet
o ixp425 support
o NPE network driver (requires Intel microcode)
o h/w qmgr support
o True IDE compact flash over expansion bus
o pci (ath and hifn795x parts tested)
o xscale watchdog timer
o ds1672 RTC on i2c bus
o ad7418 voltage + temp monitoring on i2c bus
o uart
Work done together with cognet, kevlo, and jmg. Parts of
the ixp425 support obtaine/derived from netbsd.
Reviewed by: cognet, imp
MFC after: 1 month
