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60 Commits

Author SHA1 Message Date
Neel Natu
4b52a1e497 The ioctl VM_GET_MEMORY_SEG is no longer able to return the host physical 
address associated with the guest memory segment. This is because there is
no longer a 1:1 mapping between GPA and HPA.

As a result 'vmmctl' can only display the guest physical address and the
length of the lowmem and highmem segments.
 2012-10-04 03:07:05 +00:00
Neel Natu
f7d51510f1 Change vm_malloc() to map pages in the guest physical address space in 4KB 
chunks. This breaks the assumption that the entire memory segment is
contiguously allocated in the host physical address space.

This also paves the way to satisfy the 4KB page allocations by requesting
free pages from the VM subsystem as opposed to hard-partitioning host memory
at boot time.
 2012-10-04 02:27:14 +00:00
Neel Natu
e90273829b Add ioctls to control the X2APIC capability exposed by the virtual machine to 
the guest.

At the moment this simply sets the state in the 'vcpu' instance but there is
no code that acts upon these settings.
 2012-09-25 19:08:51 +00:00
Peter Grehan
177fd53318 Add sysctls to display the total and free amount of hard-wired mem for VMs 
# sysctl hw.vmm
   hw.vmm.mem_free: 2145386496
   hw.vmm.mem_total: 2145386496

Submitted by:	Takeshi HASEGAWA hasegaw at gmail com
 2012-08-26 01:41:41 +00:00
Neel Natu
1ff856dbd7 Allow the 'bhyve' process to control whether or not the virtual machine sees an 
ioapic.

Obtained from: NetApp
 2012-08-04 22:46:29 +00:00
Neel Natu
90d4b48f60 API to map an apic id to the vcpu. 
At the moment this is a simple mapping because the numerical values are
identical.
 2012-08-04 02:38:05 +00:00
Neel Natu
32c96bc813 There is no need to explicitly specify the CR4_VMXE bit when writing to guest 
CR4. This bit is specific to the Intel VTX and removing it makes the library
more portable to AMD/SVM.

In the Intel VTX implementation, the hypervisor will ensure that this bit is
always set. See vmx_fix_cr4() for details.

Suggested by: grehan
 2012-08-04 02:14:27 +00:00
Peter Grehan
cd942e0f25 MSI-x interrupt support for PCI pass-thru devices. 
Includes instruction emulation for memory r/w access. This
opens the door for io-apic, local apic, hpet timer, and
legacy device emulation.

Submitted by:	ryan dot berryhill at sandvine dot com
Reviewed by:	grehan
Obtained from:	Sandvine
 2012-04-28 16:28:00 +00:00
John Baldwin
b67e81db43 First cut to port bhyve, vmmctl, and libvmmapi to HEAD. 2011-05-15 04:03:11 +00:00
Peter Grehan
366f60834f Import of bhyve hypervisor and utilities, part 1. 
vmm.ko - kernel module for VT-x, VT-d and hypervisor control
  bhyve  - user-space sequencer and i/o emulation
  vmmctl - dump of hypervisor register state
  libvmm - front-end to vmm.ko chardev interface

bhyve was designed and implemented by Neel Natu.

Thanks to the following folk from NetApp who helped to make this available:
	Joe CaraDonna
	Peter Snyder
	Jeff Heller
	Sandeep Mann
	Steve Miller
	Brian Pawlowski
 2011-05-13 04:54:01 +00:00