only if prepping the adapter failed.
Slight adjustment to comments.
Fix a bug whereby downing the interface didn't preven it from
processing packets.
Submitted by: Navdeep Parhar
MFC after: 1 week
Some hardware easily comes out of sync with regard to whether the current or
the next control transfer should be stalled, if a stall command is always
issued before receiving the SETUP packet. After this patch the stall command
will only be issued when a transfer should actually be stalled.
Submitted by: Hans Petter Selasky
1) Add a sysctl that will say what type of PHYs exist on the card.
2) Fix a bug that occurs when an AEL 2005 PHY resets without a transciever
in the card.
3) Unify the PHY link detection code.
Obtained from: Navdeep Parhar
MFC after: 10 days
and down more cleanly. This addresses a problem where if we have the
link flap during boot the driver would lock up the system.
Reviewed by: jhb
MFC after: 1 week
thread. Multiple RAID events in quick succession can cause an additional
bus rescan to be scheduled before an earlier scan has completed. In this
case the driver was attempting to use the same CCB storage for two requests.
PR: kern/130330
Reviewed by: Riccardo Torrini riccardo.torrini | esaote com
MFC after: 1 week
o Header file cleanup.
o bus_dma(9) conversion.
- Removed all consumers of vtophys(9) and converted to use
bus_dma(9).
- 64bit DMA support was disabled because DP83821 is not capable
of handling the DMA request. 64bit DMA request on DP83820
requires different descriptor structures and it's hard to
dynamically change descriptor format at run time so I disabled
it. Note, this is the same behavior as previous one but
previously nge(4) didn't explicitly disable 64bit mode on
DP83820.
- Added Tx/Rx descriptor ring alignment requirements(8 bytes
alignment).
- Limit maximum number of Tx DMA segments to 16. In fact,
controller does not seem to have limitations on number of Tx
DMA segments but 16 should be enough for most cases and
m_collapse(9) will handle highly fragmented frames without
consuming a lot of CPU cycles.
- Added Rx buffer alignment requirements(8 bytes alignment). This
means driver should fixup received frames to align on 16bits
boundary on strict-alignment architectures.
- Nuked driver private data structure in descriptor ring.
- Added endianness support code in Tx/Rx descriptor access.
o Prefer faster memory mapped register access to I/O mapped access.
Added fall-back mechanism to use alternative register access.
The hardware supports both memory and I/O mapped access.
o Added suspend/resume methods but it wasn't tested as controller I
have does not support PCI PME.
o Removed swap argument in nge_read_eeprom() since endianness
should be handled after reading EEPROM.
o Implemented experimental 802.3x full-duplex flow-control. ATM
it was commented out but will be activated after we have generic
flow-control framework in mii(4) layer.
o Rearranged promiscuous mode settings and simplified logic.
o Always disable Rx filter prior to changing Rx filter functions as
indicated in DP83820/DP83821 datasheet.
o Added an explicit DELAY in timeout loop of nge_reset().
o Added a sysctl variable dev.nge.%d.int_holdoff to control
interrupt moderation. Valid ranges are 1 to 255(default 1) in
units of 100us. The actual delivery of interrupt would be delayed
based on the sysctl value. The interface has to be brought down
and up again before a change takes effect. With proper tuning
value, users do not need to resort to polling(4) anymore.
o Added ALTQ(4) support.
o Added missing IFCAP_VLAN_HWCSUM as nge(4) can offload Tx/Rx
checksum calculation on VLAN tagged frames as well as VLAN tag
insertion/stripping. Also add IFCAP_VLAN_MTU capability as nge(4)
can handle VLAN tagged oversized frames.
o Fixed media header length for VLAN.
o Rearranged nge_detach routine such that it's now used for general
clean-up routine.
o Enabled MWI.
o Accessing EEPROM takes very long time so read 6 bytes ethernet
address with one call instead of 3 separate accesses.
o Don't set if_mtu in device attach, it's already set in
ether_ifattach().
o Don't do any special things for TBI interface. Remove TBI
specific media handling in the driver and have gentbi(4) handle
it. Add glue code to read/write TBI PHY registers in miibus
method. This change removes a lot of PHY handling code in driver
and now its functionality is handled by mii(4).
o Alignment fixup code is now applied only for strict-alignment
architectures. Previously the code was applied for all
architectures except i386. With this change amd64 will get
instant Rx performance boost.
o When driver fails to allocate a new mbuf, update if_qdrops so
users can see what was wrong in Rx path.
o Added a workaround for a hardware bug which resulted in short
VLAN tagged frames(e.g. ARP) was rejected as if runt frame was
received. With this workaround nge(4) now accepts the short VLAN
tagged frame and nge(4) can take full advantage of hardware VLAN
tag stripping. I have no idea how this bug wasn't known so far,
without the workaround nge(4) may never work on VLAN
environments.
o Fixed Rx checksum offload logic such that it now honors active
interface capability configured with ifconfig(8).
o In nge_start()/nge_txencap(), always leave at least one free
descriptor as indicated in datasheet. Without this the hardware
would be confused with ring descriptor structure(e.g. no clue
for the end of descriptor ring).
o Removed dead-code that checks interrupts on PHY hardware. The
code was designed to detect link state changes but it was
disabled as driving nge_tick clock would break auto-negotiation
timer. This code is no longer needed as nge(4) now uses mii(4)
and link state change handling is done with mii callback.
o Rearranged ethernet address programming logic such that it works
on strict-alignment architectures.
o Added IFCAP_VLAN_HWTAGGING/IFCAP_VLAN_HWCSUM handler in
nge_ioctl() such that the functionality is configurable with
ifconfig(8). DP83820/DP83821 can do checksum offload for VLAN
tagged frames so enable Tx/Rx checksum offload for VLAN
interfaces.
o Simplified IFCAP_POLLING selection logic in nge_ioctl().
o Fixed module unload panic when bpf listeners are active.
o Tx/Rx descriptor ring address uses 64bit DMA address for
readability. High address part of DMA would be 0 as nge(4)
disabled 64bit DMA transfers so it's ok for DP83821.
o Removed volatile keyword in softc as bus_dmamap_sync(9) should
take care of this.
o Removed extra driver private structures in descriptor ring. These
extra elements are not part of descriptor structure. Embedding
private driver structure into descriptor ring is not good idea
as its size may be different on 32bit/64bit architectures.
o Added miibus_linkchg method handler to catch link state changes.
o Removed unneeded nge_ifmedia in softc. All TBI access is handled
in gentbi(4). There is no difference between TBI and non-TBI case
now.
o Removed "gigabit link up" message handling in nge_tick. Link
state change notification is already performed by mii(4) and
checking link state by accessing PHY registers in periodic timer
handler of driver is wrong. All link state and speed/duplex
monitoring should be handled in PHY driver.
o Use our own timer for watchdog instead of if_watchdog/if_timer
interface.
o Added hardware MAC statistics counter, users canget current MAC
statistics from dev.nge.%d.stats sysctl node(%d is unit number of
a device).
o Removed unused macros, NGE_LASTDESC, NGE_MODE, NGE_OWNDESC,
NGE_RXBYTES.
o Increased number of Tx/Rx descriptors from 128 to 256. From my
experience on gigabit ethernet controllers, number of descriptors
should be 256 or higher to get an optimal performance on gigabit
link.
o Increased jumbo frame length to 9022 bytes to cope with other
gigabit ethernet drivers. Experimentation shows no problems with
9022 bytes.
o Removed unused member variables in softc.
o Switched from bus_space_{read|write}_4 to bus_{read|write}_4.
o Added support for WOL.
o replace DLT_IEEE802_11 support in net80211 with DLT_IEEE802_11_RADIO
and remove explicit bpf support from wireless drivers; drivers now
use ieee80211_radiotap_attach to setup shared data structures that
hold the radiotap header for each packet tx/rx
o remove rx timestamp from the rx path; it was used only by the tdma support
for debugging and was mostly useless due to it being 32-bits and mostly
unavailable
o track DLT_IEEE80211_RADIO bpf attachments and maintain per-vap and
per-com state when there are active taps
o track the number of monitor mode vaps
o use bpf tap and monitor mode vap state to decide when to collect radiotap
state and dispatch frames; drivers no longer explicitly directly check
bpf state or use bpf calls to tap frames
o handle radiotap state updates on channel change in net80211; drivers
should not do this (unless they bypass net80211 which is almost always
a mistake)
o update various drivers to be more consistent/correct in handling radiotap
o update ral to include TSF in radiotap'd frames
o add promisc mode callback to wi
Reviewed by: cbzimmer, rpaulo, thompsa
bug referencing a destroyed lock within TX callbacks during device
detach.
Submitted by: hps (original version)
Tested by: Lucius Windschuh <lwindschuh at googlemail.com>
possible future I-cache coherency operation can succeed. On ARM
for example the L1 cache can be (is) virtually mapped, which
means that any I/O that uses temporary mappings will not see the
I-cache made coherent. On ia64 a similar behaviour has been
observed. By flushing the D-cache, execution of binaries backed
by md(4) and/or NFS work reliably.
For Book-E (powerpc), execution over NFS exhibits SIGILL once in
a while as well, though cpu_flush_dcache() hasn't been implemented
yet.
Doing an explicit D-cache flush as part of the non-DMA based I/O
read operation eliminates the need to do it as part of the
I-cache coherency operation itself and as such avoids pessimizing
the DMA-based I/O read operations for which D-cache are already
flushed/invalidated. It also allows future optimizations whereby
the bcopy() followed by the D-cache flush can be integrated in a
single operation, which could be implemented using on-chips DMA
engines, by-passing the D-cache altogether.
register 0x52, not ctrl1. This appears to be a mistake in the bcm
reverse engineering page, and has been corrected there. Tracing
through the code, this is more in keeping with the "documented"
register. Sephe thinks it looks interesting and may be worth
fixing. :)
Submitted by: ddkprog at yahoo com
Reviewed by: Sepherosa Ziehau
