little-endian configuration for 64-bit variant is supported.
Reviewed by: mmel
Sponsored by: The FreeBSD Foundation
Differential Revision: https://reviews.freebsd.org/D4113
- boot page table is not allocated in data section, so must be
cleared before use
- map only one section (1 MB) for SOCDEV mapping (*)
- DSB must be used for ensuring of finishing TLB operations
- Invalidate BTB when appropriate
PR: 198360
Reported by: Daisuke Aoyama <aoyama at peach.ne.jp> (*)
Approved by: kib (mentor)
as of r288992 use it to manage the CCNT.
Use the CNNT for get_cyclecount() instead of binuptime() when device pmu
is compiled in; if it fails to attach, fall back to the former method.
Enable by default for the BeagleBoneBlack configuration.
Optained from: Cambridge/L41
Sponsored by: DARPA/AFRL
Reviewed by: andrew
Differential Revision: https://reviews.freebsd.org/D3837
variable during mp_start() which is too late. Move this to mp_setmaxid()
where other architectures set it and move x86 assertions to MI code.
Reviewed by: kib (x86 part)
"rmii", use rmii mode for the MAC, otherwise use MII mode. The code is
somewhat duplicated between these drivers for this.
Also, add AT91RM9200 compatibility strings to the ate driver. In the
future, there's a good chance that ate will lose the MACB support and
only attach to the AT91RM9200 EMAC device since the macb works now
that RMII support has been added to it.
driver. This is taken from the MAC at boot, but can be overridden with
'options AT91_MACB_USE_RMII'.
Switch to macb for HL201 and SAM9G20EK boards. It now works both
places. Also start to sneak up on FDT for the SAM9G20EK board, but
leave disabled due to issues with MMC that haven't been resolved.
Add early debug support for the SAM9G20EK since that is required
for FDT to work presently on these SoC.
interrupt status register to process shared interrupts only if the bit
is active and only on core to which they are routed.
Reviewed by: imp, loos
Approved by: kib (mentor)
Differential Revision: https://reviews.freebsd.org/D3723
- Add bcm2835_mbox_property for generic property request, it accepts
pointer to prepared property chan message and its size, forwards
it to MBOX and copies result back
- Make all bcm2835_mbox_XXX functions that use property channel go
through bcm2835_mbox_property path. Do not accept device_t as
an argument, it's not required: all DMA operatiosn should go
through mbox device, and all API consumers should report errors
on their side.
DEX bit is set to 1 and exception raised whenever vectorized operation is
attempted on the VFP implementation that does not support it (i.e. on Cortex A7)
In the old days, device drivers passed NULL for the parent tag when creating
a new tag, and on arm platforms that resulted in a global tag representing
overall platform constraints being substituted in the busdma code. Now all
drivers use bus_get_dma_tag() and if there is a need to represent overall
platform constraints they will be inherited from a tag supplied by nexus or
some bus driver in the hierarchy.
The only arm platforms still relying on the old global-tag scheme were some
xscale boards with special PCI-bus constraints. This change provides those
constraints through a tag supplied by the xscale PCI bus driver, and
eliminates the few remaining references to the old global var.
Reviewed by: cognet
Previous code supported only "continuous" code without any kind of
branch instructions. To change that, new function was implemented
which parses current instruction and returns an addres where
the jump might happen (alternative addr).
mdthread structure was extended to support two breakpoints
(one directly below current instruction and the second placed
at the alternative location).
One of them must trigger regardless the instruction has or has not been
executed due to condition field.
Upon cleanup, both software breakpoints are removed.
This implementation parses only the most common instructions
that are present in the code (like 99.99% of all), but there
is a chance there are some left, not covered by the parsing routine.
Parsing is done only for 32-bit instruction, no Thumb nor Thumb-2
support is provided.
Reviewed by: kib
Submitted by: Wojciech Macek <wma@semihalf.com>
Obtained from: Semihalf
Sponsored by: Juniper Networks Inc.
Differential Revision: https://reviews.freebsd.org/D4021
receives video memory address from VideoCore through property mailbox
channel. Older versions of firmware (and the one that is currently part
of sysutils/u-boot-rpi and sysutils/u-boot-rpi2) returned real physical
address, newer one returns VideoCore bus address, so we need to convert
it to actual physical address. this version works with both older and
newer interface.
point, e.g. on RaspberryPi 2 when control is passed from loader to kernel
it contains garbage. So we use cpsr as a base for new cpsr value: if we
have reached this point it means current value is OK
Reviewed by: andrew
This commit introduces support for etherswitch devices that utilize SMI as
a way of accessing its registers. SMI register is located in address space
of mge -- access to it was exported through MDIO interface.
Attachment functions were enhanced so as to ensure proper initialisation
in both cases: 1) PHYs attached directly to mge, 2) PHYs attached to
switch device and switch attached to mge. Attachment of etherswitch device
depends on dts entry with compatible="mrvl,sw" property. If none is found,
typical PHY attachment procedure follows.
In case of switch attached, PHYs' status and configuration is accessible
via etherswitchcfg, and ifconfig shows always-up, non-configurable mge
interfaces.
Due to the fact that there may be simultaneous accessess to SMI
registers (e.g. from PHY attached to one of mge instances and switch
to the other), SMI access interlock was added. It is SX lock,
because sleep ability is necessary -- busy-waiting would result
in poor performance due to long delays required by hardware.
Underlying switch driver is obliged to use sleepable locks as well.
Reviewed by: adrian
Obtained from: Semihalf
Submitted by: Bartosz Szczepanek <bsz@semihalf.com>
Differential revision: https://reviews.freebsd.org/D3900
is a dcache invalidate to point of coherency just like dcache_inv_poc(), but
a slightly different version specific to dma operations. Elaborate the
comment about how and why it's different.
per-map. The per-tag scheme is not safe, and a mutex can't be used to
protect it because the mapping routines can't sleep. Code brought in
from armv6 implementation.
The goal is to make these two files cosmetically alike so that the actual
implementation differences are visible. The only changes which aren't
spaces<->tabs and rewrapping and reindenting lines are a couple fields
shuffled around in the tag and map structs so that everything is in the same
order in both versions (which should amount to no functional change).
Similar to r286787 for x86, this treats userspace buffers the same as unmapped buffers and no longer borrows the UVA for sync operations.
Submitted by: Svatopluk Kraus <onwahe@gmail.com> (earlier revision)
Tested by: Svatopluk Kraus
Differential Revision: https://reviews.freebsd.org/D3869
represented in 7-bits format in DT files, but system expect it in 8-bit
format. Also, fix two drivers that locally hack around this bug.
Submitted by: Michal Meloun <meloun@miracle.cz>
the not-SMP case. This is safe because arm_irq_next_cpu() will return
the cpuid of the current/only core in the not-SMP case.
Submitted by: Bartosz Szczepanek @ semihalf
Normally this routine is supposed to loop until the PIC returns a "no more
interrupts pending" indication. I had commented that out to do just one
interrupt per invokation to do some timing tests.
Spotted by: Svata Kraus
Pointy Hat: ian
