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19 Commits

Author SHA1 Message Date
Oleksandr Tymoshenko
c5f8f8946c Replace generic ARM11 option with more specific 
support for ARM1136 and ARM1176

Submitted by:	Daisuke Aoyama <aoyama at peach.ne.jp>
Obtained from:	NetBSD
 2012-12-20 04:32:02 +00:00
Grzegorz Bernacki
f3d01034bc Support identification of new PJ4B cores. 
Obtained from:	Semihalf
 2012-09-14 09:38:54 +00:00
Oleksandr Tymoshenko
cf1a573f04 Merging projects/armv6, part 1 
Cummulative patch of changes that are not vendor-specific:
	- ARMv6 and ARMv7 architecture support
	- ARM SMP support
	- VFP/Neon support
	- ARM Generic Interrupt Controller driver
	- Simplification of startup code for all platforms
 2012-08-15 03:03:03 +00:00
Warner Losh
ee5cac8ab0 trim trailing whitespace 2012-06-13 05:02:51 +00:00
Andrew Turner
0b898a9ef1 Replace the C implementation of __aeabi_read_tp with an assembly version. 
This ensures we follow the ABI by preserving registers r1-r3.

Reviewed by:	jmallett, imp
 2012-04-16 09:38:20 +00:00
Stanislav Sedov
b30d62be27 - Revert part of r234005, which I did not intend to commit. 
Sorry! :(
 2012-04-07 23:51:16 +00:00
Stanislav Sedov
47db1ea0bf - Add kernel config file for QEMU-emulated gumstix board. 2012-04-07 23:48:51 +00:00
Kevin Lo
dbb0e359a7 Correct both FA526/FA626TE cpu ids since the cpu id is always 
masked with 0xfffffff0
 2010-02-20 14:52:07 +00:00
Kevin Lo
4e92112d57 Correct cpu id for FA526. 
While I'm here, add cpu id for FA626TE.
 2010-02-14 05:02:08 +00:00
Sam Leffler
b74f293f33 add IXP465 and generic IXP425 definition 2008-12-23 04:46:13 +00:00
Sam Leffler
d212022417 Merge WIP from p4: 
o recognize ixp435 cpu
o change memory layout for for ixp4xx to not assume memory is aliases
  to 0x10000000 (Cambria/ixp435 memory starts at zero)
o handle 64 irqs for ixp435
o dual EHCI USB 2.0 controller integral to ixp435
o overhaul NPE code for ixp435 and better MAC+MII naming
o updated NPE firmware (including NPE-A image for ixp435/ixp465)
o Gateworks Cambria board support:
  - IDE compact flash
  - MCU
  - front panel LED on i2c bus
  - Octal LED latch

Sanity-tested with NFS-root on Avila and Cambria boards.  Requires
pending boot2 mods for CF-boot on Cambria.
 2008-12-13 01:21:37 +00:00
Rafal Jaworowski
ba6faad63c Introduce low-level support for new Marvell core CPUs: 88FR131, 88FR571. 
They are compliant with ARMv5TE and integrated on 88F6281 (Kirkwood) and
MV78100 (Discovery) system-on-chip families.

Obtained from:	Marvell, Semihalf
 2008-10-13 18:16:54 +00:00
Warner Losh
dfb7d4cdef Merge definitions for ARM9E, ARM10 and ARM11 processors from p4 (which 
got them from NetBSD).
 2007-10-18 05:06:58 +00:00
Olivier Houchard
5f78cb4a35 XScale core 3 definitions. 
Approved by:	re (blanket)
 2007-07-27 14:54:27 +00:00
Olivier Houchard
676b1fbdbf Identify the xscale 81342. 2006-11-07 22:36:57 +00:00
Olivier Houchard
11d1528ce0 Finally bring it support for the i80219 XScale processor. 
Submitted by:	Max M. Boyarov <m.boyarov bsd by>
 2006-08-24 23:51:28 +00:00
Olivier Houchard
f9126cfb8f Add an alternate ID for the arm920t (the real solution is to have 
per-cpu class masks, but oh well).
 2005-11-21 19:06:25 +00:00
Warner Losh
d8315c79d9 Start all license statements with /*- 2005-01-05 21:58:49 +00:00
Olivier Houchard
6fc729af63 Import FreeBSD/arm kernel bits. 
It only supports sa1110 (on simics) right now, but xscale support should come
soon.
Some of the initial work has been provided by :
Stephane Potvin <sepotvin at videotron.ca>
Most of this comes from NetBSD.
 2004-05-14 11:46:45 +00:00