the microcode caused SCB timeouts. Linux driver does not allow
microcode loading for these controllers and jfv also confirmed that
there is no need to do and it shouldn't.
PR: kern/103332
Additional confirmation from: jfv
MFC after: 1 week
floppies, so it will not be used as the start of an emulated floppy
image on a bootable CD which is what the fake BPB was used for.
- Only check that EDD packet mode is available once at the start of
zfsldr rather than for each disk sector now that we read data in one
sector at a time. As a result, collapse the remaining bits of read
up into nread and rename nread to read.
- Restore a return at the end of putstr that I removed in the previous
revision.
Tested by: Henri Hennebert (earlier version)
MFC after: 1 week
Remove message about non empty bootcode, we can not break something
while GEOM_PART_EBR_COMPAT is defined.
But without GEOM_PART_EBR_COMPAT any changes in EBR are allowed and we
can accidentally wipe the boot code. To do not break anything save
the first EBR chunk and keep it untouched each time when we are
changing EBR. Note that we are still not support boot code for EBR.
PR: kern/141235
MFC after: 1 month
disk drive. The boot0cfg(8) utility preserves these 4 bytes when is
writing bootcode to keep a multiboot ability.
Change gpart's bootcode method to keep DSN if it is not zero. Also
do not allow writing bootcode with size not equal to MBRSIZE.
PR: kern/157819
Tested by: Eir Nym
MFC after: 1 month
is defined, but then proceeds to use a hardcoded maximum hostname length
of 64 anyway. Fix this by checking against MAXHOSTNAMELEN instead.
PR: bin/157732
MFC after: 3 days
machine checks (e.g. invalid PCI configuration cycles), but these can
be caught and recovered from. This change also the RTAS PCI driver to
work without modification as a replacement for the Grackle driver on
Grackle-based Powermacs.
The DFS code was tickling the channel set directly whilst going
through the state RUN -> CSA -> RUN. This only changed the channel;
it didn't go via ath_reset(). However in this driver, a channel
change always causes a chip reset, which resets the beacon timer
configuration and interrupt setup. This meant that data would go
out but as the beacon timers never fired, beacons would never
be queued.
The confusing part is that sometimes the state transition was
RUN -> SCAN -> CAC -> RUN (with CSA being in there sometimes);
going via SCAN would clear sc_beacons and thus the transition
to RUN would reprogram beacon transmission.
In case someone tries debugging why suspending a device currently
beaconing (versus just RX'ing beacons which is what occurs in STA
mode), add a silly comment which should hopefully land them at
this commit message. The call to ath_hal_reset() will be clearing
the beacon config and it may not be always reset.
can be tested.
This doesn't at all actually do radar detection! It's just
so developers who wish to test the net80211 DFS code can easily
do so. Without this flag, the DFS channels are never marked
DFS and thus the DFS stuff doesn't run.
latter.
It appears that the addition to uath(4) came in through PR kern/135009,
which had tested another device, the SMCWUSBTG2, successfully with uath(4)
and included the SMCWUSBG as it "has the same chipset". I can find no
other evidence that these two do actually share the same chipset. Moreover,
Linux treats the SMCWUSBG as a zyd(4) device also.
This reverts r223537.
Discussed with: hselasky, kevlo
MFC after: 1 week
In cdregister(), hold the periph lock semaphore during changer
probe/configuration. This removes a window where an open of the
cd device may succeed before probe processing has completed.
In camisr_runqueue(), we need to run the sims queue regardless of
whether or not the current peripheral has more work to do. This
reverts a change mistakenly made in revision 223081.
Reported by: ache
smell that caused me to turn this up was due to a failed fan burning, not
a CPU (plus a healthy dose of paranoia).
Submitted by: Paul Mather <paul at gromit dot dlib dot vt dot edu>
LED controller used to run the load graph on the server's front panel.
Reported by: Paul Mather <paul at gromit dot dlib dot vt dot edu>
MFC after: 3 days
a magnitude smaller than itc_freq. A minimum period of 10*hz is
sufficient precision. As a side-effect, the number of clocks per
second, when the machine is idle, dropped by more than 50%.
Be anal and define the maximum period to be at least 4G seconds.
With a 64-bit counter and an ITC frequency that's expected to be
always less than 4Ghz, it takes longer than that to wrap around.
exit immediately with an error.
If there is an error opening or reading a file to put into the archive,
set the return value for a deferred error exit.
PR: bin/154407
- Implement simple and generic language which can
be used to describe any kind of device ID structures.
- Fix endian issues.
- Add an example format file.
Suggested by: imp @
MFC after: 14 days
