Commit Graph

627 Commits

Author SHA1 Message Date
John Baldwin
df4ce32fcb Properly return success once a matching VPD entry is found in
pci_get_vpd_readonly_method().  Previously the loop was always running
to completion and falling through to failing with ENXIO.

PR:		kern/164313
Submitted by:	Chuck Tuffli  chuck tuffli net
MFC after:	1 week
2012-01-19 21:38:19 +00:00
John Baldwin
a15536c70d Implement BUS_ADD_CHILD() for the isab(4) driver. It already calls
bus_generic_probe() and bus_generic_attach() to handle drivers that add
new children via identify methods.

MFC after:	1 week
2011-12-14 12:34:02 +00:00
John Baldwin
4889af2063 Add a constant for the Advisory Non-Fatal Error bit in AER corrected error
status and mask.
2011-11-30 18:33:23 +00:00
Marius Strobl
4b7ec27007 - There's no need to overwrite the default device method with the default
one. Interestingly, these are actually the default for quite some time
  (bus_generic_driver_added(9) since r52045 and bus_generic_print_child(9)
  since r52045) but even recently added device drivers do this unnecessarily.
  Discussed with: jhb, marcel
- While at it, use DEVMETHOD_END.
  Discussed with: jhb
- Also while at it, use __FBSDID.
2011-11-22 21:28:20 +00:00
Hans Petter Selasky
ff11fd7fa7 Add missing XHCI early takeover code. The XHCI takeover code
is supposed to disable the BIOS from using the XHCI controller
after bootup.

Approved by:	re (kib)
Reported by:	Mike Tancsa
MFC after:	1 week
2011-07-22 15:37:23 +00:00
John Baldwin
34ff71eecd Respect the BIOS/firmware's notion of acceptable address ranges for PCI
resource allocation on x86 platforms:
- Add a new helper API that Host-PCI bridge drivers can use to restrict
  resource allocation requests to a set of address ranges for different
  resource types.
- For the ACPI Host-PCI bridge driver, use Producer address range resources
  in _CRS to enumerate valid address ranges for a given Host-PCI bridge.
  This can be disabled by including "hostres" in the debug.acpi.disabled
  tunable.
- For the MPTable Host-PCI bridge driver, use entries in the extended
  MPTable to determine the valid address ranges for a given Host-PCI
  bridge.  This required adding code to parse extended table entries.

Similar to the new PCI-PCI bridge driver, these changes are only enabled
if the NEW_PCIB kernel option is enabled (which is enabled by default on
amd64 and i386).

Approved by:	re (kib)
2011-07-15 21:08:58 +00:00
Marius Strobl
eb06e7719b PCIB_ALLOC_MSIX() may already fail on the first pass, f.e. when the PCI-PCI
bridge is blacklisted. In that case just return from pci_alloc_msix_method(),
otherwise we continue without a single MSI-X resource, causing subsequent
attempts to use the seemingly available resource to fail or when booting
verbose a NULL-pointer dereference of rle->start when trying to print the
IRQ in pci_alloc_msix_method().

Reviewed by:	jhb
MFC after:	1 week
2011-07-13 18:35:47 +00:00
John Baldwin
a27d4bdc9f Properly align the end of a candidate back region based on the window's
granularity when growing a PCI-PCI window up.

Tested by:	dougb
MFC after:	3 days
2011-07-12 13:28:39 +00:00
Konstantin Belousov
141c08f9c0 Implement pci_find_class(9), the function to find a pci device by its class.
Sponsored by:	The FreeBSD Foundation
Reviewed by:	jhb
MFC after:	1 week
2011-07-09 14:30:13 +00:00
John Baldwin
0dbe859d2f Split out host_pcib_get_busno() from the generic PCI-PCI bridge driver to
start a new file that will hold utility APIs used by various Host-PCI
bridge drivers and drivers that provide PCI domains.
2011-06-24 21:39:38 +00:00
John Baldwin
35d200101a Minor whitespace and style fixes. 2011-06-21 19:31:31 +00:00
John Baldwin
a49dcb469c Fix some off-by-one errors with the ending address of candidate regions
when attempting to grow a window.
2011-06-10 13:24:56 +00:00
John Baldwin
0d439b5f93 More properly handle Cardbus cards that that store their CIS in a BAR after
the recent changes to track BAR state explicitly.  The code would now
attempt to add the same BAR twice in this case.  Instead, change this so
that it recognizes this case and only adds it once and do not delete the
BAR outright after parsing the CIS.

Tested by:	bschmidt
2011-06-06 13:21:11 +00:00
Ruslan Ermilov
934d7bccdb Renamed PCI_INTERFACE_XHCI to PCIP_SERIALBUS_USB_XHCI and moved it
to <dev/pci/pcireg.h>.

Reviewed by:	hselasky
MFC after:	3 days
2011-05-17 11:23:43 +00:00
Henrik Brix Andersen
adc38bf22f Allow direct children of PCI-ISA bridges to allocate resources from
the parent PCI bus.

Heavily inspired by jhb@ and a similar implementation present in
sys/dev/pci/vga_pci.c.

Reviewed by:	jhb
Approved by:	jhb
2011-05-13 15:06:35 +00:00
John Baldwin
83c41143ca Reimplement how PCI-PCI bridges manage their I/O windows. Previously the
driver would verify that requests for child devices were confined to any
existing I/O windows, but the driver relied on the firmware to initialize
the windows and would never grow the windows for new requests.  Now the
driver actively manages the I/O windows.

This is implemented by allocating a bus resource for each I/O window from
the parent PCI bus and suballocating that resource to child devices.  The
suballocations are managed by creating an rman for each I/O window.  The
suballocated resources are mapped by passing the bus_activate_resource()
call up to the parent PCI bus.  Windows are grown when needed by using
bus_adjust_resource() to adjust the resource allocated from the parent PCI
bus.  If the adjust request succeeds, the window is adjusted and the
suballocation request for the child device is retried.

When growing a window, the rman_first_free_region() and
rman_last_free_region() routines are used to determine if the front or
end of the existing I/O window is free.  From using that, the smallest
ranges that need to be added to either the front or back of the window
are computed.  The driver will first try to grow the window in whichever
direction requires the smallest growth first followed by the other
direction if that fails.

Subtractive bridges will first attempt to satisfy requests for child
resources from I/O windows (including attempts to grow the windows).  If
that fails, the request is passed up to the parent PCI bus directly
however.

The PCI-PCI bridge driver will try to use firmware-assigned ranges for
child BARs first and only allocate a "fresh" range if that specific range
cannot be accommodated in the I/O window.  This allows systems where the
firmware assigns resources during boot but later wipes the I/O windows
(some ACPI BIOSen are known to do this) to "rediscover" the original I/O
window ranges.

The ACPI Host-PCI bridge driver has been adjusted to correctly honor
hw.acpi.host_mem_start and the I/O port equivalent when a PCI-PCI bridge
makes a wildcard request for an I/O window range.

The new PCI-PCI bridge driver is only enabled if the NEW_PCIB kernel option
is enabled.  This is a transition aide to allow platforms that do not
yet support bus_activate_resource() and bus_adjust_resource() in their
Host-PCI bridge drivers (and possibly other drivers as needed) to use the
old driver for now.  Once all platforms support the new driver, the
kernel option and old driver will be removed.

PR:		kern/143874 kern/149306
Tested by:	mav
2011-05-03 17:37:24 +00:00
John Baldwin
d2c9344ff9 Add implementations of BUS_ADJUST_RESOURCE() to the PCI bus driver,
generic PCI-PCI bridge driver, x86 nexus driver, and x86 Host to PCI bridge
drivers.
2011-05-02 14:13:12 +00:00
John Baldwin
8adcbaed13 Only align MSI message groups based on the number of messages being
allocated, not the maximum number of messages the device supports.  The
spec only requires the former, and I believe I implemented the latter due
to misunderstanding an e-mail.  In particular, this fixes an issue where
having several devices that all support 16 messages can run out of
IDT vectors on x86 even though the driver only uses a single message.

Submitted by:	Bret Ketchum  bcketchum of gmail
MFC after:	1 week
2011-04-27 20:08:44 +00:00
John Baldwin
a90dd577e7 Explicitly track the state of all known BARs for each PCI device. The PCI
bus driver will now remember the size of a BAR obtained during the initial
bus scan and use that size when doing lazy resource allocation rather than
resizing the BAR.  The bus driver will now also report unallocated BARs to
userland for display by 'pciconf -lb'.  Psuedo-resources that are not BARs
(such as the implicit I/O port resources for master/slave ATA controllers)
will no longer be listed as BARs in 'pciconf -lb'.  During resume, BARs are
restored from their new saved state instead of having the raw registers
saved and restored across resume.  This also fixes restoring BARs at
unusual loactions if said BAR has been allocated by a driver.

Add a constant for the offset of the ROM BIOS BAR in PCI-PCI bridges and
properly handle ROM BIOS BARs in PCI-PCI bridges.  The PCI bus now also
properly handles the lack of a ROM BIOS BAR in a PCI-Cardbus bridge.

Tested by:	jkim
2011-03-31 13:22:12 +00:00
John Baldwin
3b0a4aef96 Do a sweep of the tree replacing calls to pci_find_extcap() with calls to
pci_find_cap() instead.
2011-03-23 13:10:15 +00:00
John Baldwin
e786cbfdd2 Rename pci_find_extcap() to pci_find_cap(). PCI now uses the term
"extended capabilities" to refer to the new set of capability structures
starting at offset 0x100 in config space for PCI-express devices.  For now
both function names will still work.  I will merge this to older branches
to ease driver portability, but 9.0 will ship with a new pci_find_extcap()
function that locates extended capabilities instead.

Reviewed by:	imp
MFC after:	1 week
2011-03-22 12:05:49 +00:00
John Baldwin
54a03acb86 Partially revert previous change. Drop the quirk to disable MSI for HT
chipsets that do not have an HT slave at 0:0:0:0.  The Linux quirk is
actually specific to Nvidia chipsets and the check I had added was in
the wrong place.

Prodded by:	nathanw
2011-03-18 14:06:12 +00:00
John Baldwin
8081bab70b Fix a few issues with HyperTransport devices and MSI interrupts:
- Always enable the HyperTransport MSI mapping window for HyperTransport
  to PCI bridges (these show up as HyperTransport slave devices).
  The mapping windows in PCI-PCI bridges are enabled by existing code
  in the PCI-PCI bridge driver as MSI requests propagate up the device
  tree, but Host-PCI bridges don't really show up in that tree.
- If the PCI device at domain 0 bus 0 slot 0 function 0 is not a
  HyperTransport device, then blacklist MSI on any other HT devices in
  the system.  Linux has a similar quirk.

PR:		kern/155442
Tested by:	Zack Dannar  zdannar of gmail
MFC after:	1 week
2011-03-18 12:13:04 +00:00
John Baldwin
6e2b68aab6 Properly handle BARs bigger than 4G. The '1' was treated as an int
causing the size calculation to be truncated to the size of an int
(32-bits on all current architectures).

Submitted by:	Anish  akgupt3 of gmail
MFC after:	1 week
2011-02-23 12:58:50 +00:00
Marcel Moolenaar
bba39e1034 Use the preload_fetch_addr() and preload_fetch_size() convenience
functions to obtain the address and size of the PCI vendor data.

Sponsored by: Juniper Networks.
2011-02-13 19:26:51 +00:00
John Baldwin
da1781dd59 Don't whine about child drivers calling pci_enable_busmaster(). That is
perfectly normal.

MFC after:	1 week
2010-12-20 14:54:24 +00:00
John Baldwin
9d76324839 Add device IDs for two more ServerWorks Host-PCI bridges so that we can
read their starting PCI bus number for older systems that do not support
ACPI (or have a broken _BBN method).

PR:		kern/148108
MFC after:	1 week
2010-11-25 15:42:33 +00:00
Jung-uk Kim
f68ff88c87 Resume critical PCI devices (and their children) first, then everything else
later.  This give us better chance to catch device driver problems.
2010-11-22 21:58:00 +00:00
Nathan Whitehorn
495ed64c16 The EHCI_CAPLENGTH and EHCI_HCIVERSION registers are actually sub-registers
within the first 4 bytes of the EHCI memory space. For controllers that
use big-endian MMIO, reading them with 1- and 2-byte reads would then
return the wrong values. Instead, read the combined register with a 4-byte
read and mask out the interesting quantities.
2010-10-25 15:51:43 +00:00
John Baldwin
ba577448a2 - Add a new PCI quirk to whitelist an old chipset that doesn't support
PCI-express or PCI-X capabilities if we are running in a virtual machine.
- Whitelist the Intel 82440 chipset used by QEMU.

Tested by:	jfv
MFC after:	1 week
2010-10-22 11:42:02 +00:00
John Baldwin
fb2439a6f6 Clarify a misleading comment. The test in pci_reserve_map() was meant to
ignore BARs that are invalid due to having a size of zero, not to ignore
BARs with an existing base of zero.  While here, reorganize the code
slightly to make the intent clearer.

Reported by:	avg
MFC after:	1 week
2010-10-21 17:46:23 +00:00
Jung-uk Kim
d815d0abb7 Update PCI power management registers per PCI Bus Power Management Interface
Specification Rev. 1.2.  Rename pp_pcmcsr field of PM capabilities to pp_bse
to avoid further confusions and adjust some comments accordingly.  The real
PMCSR (Power Management Control/Status Register) is PCIR_POWER_STATUS and
it is actually BSE (PCI-to-PCI Bridge Support Extensions) register.
2010-10-20 23:41:16 +00:00
Jung-uk Kim
f3e0b10973 Introduce a new tunable 'hw.pci.do_power_suspend'. This tunable lets you
avoid PCI power state transition from D0 to D3 for suspending case.  Default
is 1 or enabled.
2010-10-20 16:47:09 +00:00
Jung-uk Kim
347263c935 Do not apply do_power_resume for suspending P2P bridge as we did in r214064. 2010-10-20 16:40:14 +00:00
Jung-uk Kim
6d018c85e1 Remove PCI header type 0 restriction from power state changes. PCI config.
registers for bridges are saved and restored since r200341.

OK'ed by:	imp, jhb
2010-10-19 17:15:22 +00:00
Jung-uk Kim
b56b75259b Do not apply do_power_resume for suspending case. When do_powerstate was
splitted into do_power_resume and do_power_nodriver, it became stale.
2010-10-19 17:05:51 +00:00
Jung-uk Kim
debfe32ccd Remove unnecessary castings and fix couple of style(9) nits. 2010-10-15 21:41:59 +00:00
Jung-uk Kim
6e877573df Move setting power state for children into a separate function as they were
essentially the same.  This also restores hw.pci.do_power_resume tunable,
which was broken since r211430.

Reviewed by:	jhb
2010-10-15 21:39:51 +00:00
John Baldwin
da6b22afaf - Rename the constant for the Master Data Parity Error flag in the
PCI status register to map its current name.
- Use PCIM_* rather than PCIR_* for constants for fields in various AER
  registers.  I got about half of them right in the previous commit.

MFC after:	1 week
2010-09-09 18:19:15 +00:00
John Baldwin
79c2de35b5 - Add register definitions related to extended capability IDs in
PCI-express.  I used PCIZ_* for ID constants (plain capability IDs use
  PCIY_*).
- Add register definitions for the Advanced Error Reporting, Virtual
  Channels, and Device Serial Number extended capabilities.
- Teach pciconf -c to list extended as well as plain capabilities.   Adds
  more detailed parsing for AER, VC, and device serial numbers.

MFC after:	2 weeks
2010-09-08 17:53:34 +00:00
John Baldwin
62508c531e Add a new method to the PCI bridge interface, PCIB_POWER_FOR_SLEEP(). This
method is used by the PCI bus driver to query the power management system
to determine the proper device state to be used for a device during suspend
and resume.  For the ACPI PCI bridge drivers this calls
acpi_device_pwr_for_sleep().  This removes ACPI-specific knowledge from
the PCI and PCI-PCI bridge drivers.

Reviewed by:	jkim
2010-08-17 15:44:52 +00:00
John Baldwin
7d23a9b3d5 - Retire acpi_pcib_resume(). It is has just been an alias for
bus_generic_resume() since the pci_link(4) driver was added.
- Change the ACPI PCI-PCI bridge driver to inherit most of its methods
  from the generic PCI-PCI bridge driver.  In particular, this will now
  restore PCI config registers for ACPI PCI-PCI bridges.

Tested by:	Oleg Sharoyko  osharoiko of gmail
2010-08-05 16:10:12 +00:00
Pyun YongHyeon
f39cf57f91 Consistently check header type after reading PCIR_HDRTYPE register.
While I'm here use defined macro instead of using magic numbers for
header type.

Reviewed by:	jhb
2010-07-29 20:42:38 +00:00
Neel Natu
762aad8142 Fix 'pciconf -a' by providing an implementation of PCIOCATTACHED.
Reviewed by:	imp
MFC after:	1 week
Pointed out by:	Heymian Wong (heymian at mit.alum.edu)
Sponsored by:	NetApp
2010-07-29 06:27:41 +00:00
Rafal Jaworowski
c5a514a756 Provide more defines for PCI-Express device ctrl. 2010-07-11 20:55:39 +00:00
Alexander Motin
93fc07b434 Virtualize pci_remap_msi_irq() call from general MSI code. It allows MSI
(FSB interrupts) to be used by non-PCI devices, such as HPET.
2010-06-14 07:10:37 +00:00
Alexander Motin
75f5385157 Honor hw.pci.do_power_nodriver on resume. Power-down devices without
driver attached.
2010-05-22 03:19:30 +00:00
Nathan Whitehorn
ca2c19312e Add support for the U4 PCI-Express bridge chipset used in late-generation
Powermac G5 systems. MSI and several other things are not presently
supported.

The U3/U4 internal device support portions of this change were contributed
by Andreas Tobler.

MFC after:	1 week
2010-05-16 15:18:25 +00:00
John Baldwin
5d82e6d067 Small whitespace fixes. 2010-03-11 15:25:47 +00:00
Alexander Motin
24d6a5ed27 Add pci_get|set_max_read_req() helper functions to control maximum PCIe
read request size.

Reviewed by:	jhb@
2010-02-05 17:18:48 +00:00