Commit Graph

27 Commits

Author SHA1 Message Date
Justin Hibbits
7b25dcca76 Implement hwpmc counting PMC support for PowerPC G4+ (MPC745x/MPC744x).
Sampling is in progress.

Approved by:	nwhitehorn (mentor)
MFC after:	9.0-RELEASE
2011-12-24 19:34:52 +00:00
Marcel Moolenaar
ebfbeb83f6 o Add system versions for the P4040(E) and P4080(E).
o   In bare_probe(), change the logic that determines the maximum
    number of processors/cores into a switch statement and take
    advantage of the fact that bit 3 of the SVR value indicates
    whether we're running on a security enabled version. Since we
    don't care about that here, mask the bit. All -E versions
    are taken care of automatically.
2011-05-29 00:27:42 +00:00
Marcel Moolenaar
df697aa015 o Swap the SVR numbers for MPC8533 & MPC8533E
o   Add SVR defines for P1011(E), P1020(E), P2010(E) & P2020(E)
2011-05-27 05:58:10 +00:00
Nathan Whitehorn
ff30eecffe Fix handling of NX pages on capable CPUs. Thanks to kib for prodding me
in the right direction.
2011-01-13 04:37:48 +00:00
Nathan Whitehorn
2971d3bb6e Add CPU support code for the IBM Cell Broadband Engine. 2010-11-12 15:20:10 +00:00
Nathan Whitehorn
c3e289e1ce MFppc64:
Kernel sources for 64-bit PowerPC, along with build-system changes to keep
32-bit kernels compiling (build system changes for 64-bit kernels are
coming later). Existing 32-bit PowerPC kernel configurations must be
updated after this change to specify their architecture.
2010-07-13 05:32:19 +00:00
Joel Dahl
2598954edc The NetBSD Foundation has granted permission to remove clause 3 and 4 from
their software.

Obtained from:	NetBSD
2010-03-03 17:07:02 +00:00
Nathan Whitehorn
999987e51a Add SMP support on U3-based G5 systems. This does not yet work perfectly:
at least on my Xserve, getting the decrementer and timebase on APs to tick
requires setting up a clock chip over I2C, which is not yet done.

While here, correct the 64-bit tlbie function to set the CPU to 64-bit
mode correctly.

Hardware donated by:	grehan
2009-10-23 03:17:02 +00:00
Nathan Whitehorn
7f0ad28f28 Fix copy/paste typo in last revision. PMC0 control should be shifted 8
bits, not 6, on the PPC 970.
2009-06-23 04:02:36 +00:00
Nathan Whitehorn
30a2bd2f78 Teach cpu_est_clockrate() about the G5's slightly different PMC. This
allows the boot messages to include the CPU speed and makes possible
the forthcoming cpufreq support for the PPC 970.
2009-06-17 16:34:40 +00:00
Rafal Jaworowski
28bb01e5ba Initial support for SMP on PowerPC MPC85xx.
Tested with Freescale dual-core MPC8572DS development system.

Obtained from:	Freescale, Semihalf
2009-05-21 11:43:37 +00:00
Rafal Jaworowski
7ad9c533ef PowerPC common SMP startup and time base rework.
- make mftb() shared, rewrite in C, provide complementary mttb()
- adjust SMP startup per the above, additional comments, minor naming
  changes
- eliminate redundant TB defines, other minor cosmetics

Reviewed by:	marcel, nwhitehorn
Obtained from:	Freescale, Semihalf
2009-05-14 16:48:25 +00:00
Nathan Whitehorn
b40ce02a2f Factor out platform dependent things unrelated to device drivers into a
new platform module. These are probed in early boot, and have the
responsibility of determining the layout of physical memory, determining
the CPU timebase frequency, and handling the zoo of SMP mechanisms
found on PowerPC.

Reviewed by:	marcel, raj
Book-E parts by: raj
2009-05-14 00:34:26 +00:00
Nathan Whitehorn
8cf9d6cd7e Rework the way we get the cacheline size. Instead of having a table of
CPUs known to use 128 byte cache lines and defaulting to 32, use the dcbz
instruction to measure it. Also make dcbz behave the way you would
expect on PPC 970.
2009-04-12 03:03:55 +00:00
Nathan Whitehorn
1c96bdd146 Add support for 64-bit PowerPC CPUs operating in the 64-bit bridge mode
provided, for example, on the PowerPC 970 (G5), as well as on related CPUs
like the POWER3 and POWER4.

This also adds support for various built-in hardware found on Apple G5
hardware (e.g. the IBM CPC925 northbridge).

Reviewed by:    grehan
2009-04-04 00:22:44 +00:00
Rafal Jaworowski
389e4721e9 Make MPC85xx LAW handling and reset routines aware of the MPC8548 variant.
Inspired by discussion with Alexey V Fedorov on freebsd-powerpc@.
2009-03-13 06:28:20 +00:00
Rafal Jaworowski
fe48da3f41 Improve MPC85XX helper routines.
- Move CCSR accessors to the shared MPC85XX area
- Simplify SVR version subfield handling
- Adjust OCP
2008-12-17 15:27:49 +00:00
Marcel Moolenaar
cf0c300484 o Remove SPR_TSR & SPR_TCR for AIM.
o  Remove SPR_HID2.
o  Add more SPR_L3CR bit definitions.
2008-09-15 02:51:07 +00:00
Rafal Jaworowski
653b7b4943 Move System Revision defines to a bit better place, add MPC8572 systems IDs. 2008-04-26 17:39:55 +00:00
Rafal Jaworowski
ffb5669540 Rework and extend PowerPC headers definitons towards Book-E/e500 CPUs support.
Approved by:	cognet (mentor)
Obtained from:	Juniper, Semihalf
MFp4:		e500
2008-03-03 13:20:52 +00:00
Rafal Jaworowski
cb9bdc649d Teach PowerPC CPU identification routines to recognize e500 cores. Fix style
issues in this area.

Approved by:	cognet (mentor)
MFp4:		e500
2008-02-25 00:09:23 +00:00
Peter Grehan
4e895c543a - add definitions for MPC7447A/7448 (i.e. miniMac)
- expand MPC745X_P macro to include these

Obtained from:	NetBSD
2005-02-04 01:17:04 +00:00
Warner Losh
60727d8b86 /* -> /*- for license, minor formatting changes 2005-01-07 02:29:27 +00:00
Peter Grehan
e6d3e1c2c6 Definitions for MPC7457 CPU type and HID0 bits 2004-02-09 00:12:50 +00:00
Benno Rice
19ca68d921 - Update spr.h
- Add hid.h

Obtained from:	NetBSD

NOTE: This undoes some changes I'd made to prefix the processor name defines
with PVR_.  This was due to my original decision to use MPC750 as a cpu name.
With this changed, the PVR_ change is no longer required.
2003-02-05 12:04:29 +00:00
Benno Rice
3bc5121f01 Rename the constants for the contents of the PVR register so as not to
conflict with cpu names used in config files..
2002-05-09 14:04:43 +00:00
Benno Rice
b57e802a85 Commit of stuff that's been sitting in my tree for a while.
Highlights include:
- New low-level trap code from NetBSD.  The high level code still needs a lot
  of work.
- Fixes for some pmap handling in thread switching.
- The kernel will now get to attempting to jump into init in user mode.  There
  are some pmap/trap issues which prevent it from actually getting there though.

Obtained from:	NetBSD (parts)
2002-04-29 12:14:31 +00:00