Basically the msg ring interrupt was being re-enabled
inside a spinlock as the thread set it self up for rescheduling.
This won't work since inside the re-enable is another
spin lock.. which means on return from the reenable
the interrupts have been reenabled. Thus you would
get a clock int and end up panicing holding a spin
lock to long :-o
the mi_startup (or to the last of it).. and
hit a panic after :
uart0: <16550 or compatible> on iodi0
Trap cause = 2 (TLB miss....)
I did have to take the pci bus OUT of the
build to get this far, hit a cache error with
the PCI code in. Interesting thing is the machine
reboots too ;-)
compile and many of them may disappear. For example
the xlr_boot1_console.c is old code that is ifdef'd out.
I will clean these sorts of things up as I make progress
on the port. So far the only thing I have I think straightened
out is the bits around the interupt handling... and hey that
may be broke ;-)
