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9 Commits

Author SHA1 Message Date
Ruslan Bukin
9a6eb971a1 o Update QEMU device tree. 
QEMU was updated to privileged architecture v1.9
and we now fully support it.

Sponsored by:	DARPA, AFRL
Sponsored by:	HEIF5
 2016-09-07 15:48:44 +00:00
Ruslan Bukin
9862cef040 o Separate rtc and timecmp registers: they are different across 
RISC-V cpu implementations.
o Update RocketChip device tree source (DTS).

We now support latest verison of RocketChip synthesized on
Xilinx FPGA (Zedboard).

RocketChip is an implementation of RISC-V processor written on
Chisel hardware construction language.

Sponsored by:	DARPA, AFRL
Sponsored by:	HEIF5
 2016-09-01 14:58:11 +00:00
Ruslan Bukin
5f8228b2f3 o Remove operation in machine mode. 
Machine privilege level was specially designed to use in vendor's
  firmware or bootloader. We have implemented operation in machine
  mode in FreeBSD as part of understanding RISC-V ISA, but it is time
  to remove it.
  We now use BBL (Berkeley Boot Loader) -- standard RISC-V firmware,
  which provides operation in machine mode for us.
  We now use standard SBI calls to machine mode, instead of handmade
  'syscalls'.
o Remove HTIF bus.
  HTIF bus is now legacy and no longer exists in RISC-V specification.
  HTIF code still exists in Spike simulator, but BBL do not provide
  raw interface to it.
  Memory disk is only choice for now to have multiuser booted in Spike,
  until Spike has implemented more devices (e.g. Virtio, etc).

Sponsored by:	DARPA, AFRL
Sponsored by:	HEIF5
 2016-08-10 12:41:36 +00:00
Ruslan Bukin
98f50c44e3 Update RISC-V port to Privileged Architecture Version 1.9. 
Sponsored by:	DARPA, AFRL
Sponsored by:	HEIF5
 2016-08-02 14:50:14 +00:00
Ruslan Bukin
3f8f5599a3 o Add device tree files and kernel configuration files 
for RISC-V cpus synthesized on FPGA hardware.
o Include new files to the build.
 2016-04-26 13:22:08 +00:00
Ruslan Bukin
17696c12f5 Add support for symmetric multiprocessing (SMP). 
Tested on Spike simulator with 2 and 16 cores (tlb enabled),
so set MAXCPU to 16 at this time.

This uses FDT data to get information about CPUs
(code based on arm64 mp_machdep).

Invalidate entire TLB cache as it is the only way yet.

Sponsored by:	DARPA, AFRL
Sponsored by:	HEIF5
 2016-02-24 16:50:34 +00:00
Ruslan Bukin
cea32c0742 o Grab physical memory regions information from the device tree. 
o Increase memory size.
 2016-02-23 14:21:46 +00:00
Ruslan Bukin
cfddfe4cd5 o Move non-generic kernel configuration out from GENERIC. 
o Add kernel configuration for QEMU.

Both SPIKE and QEMU kernel configs are temporary (until
we will be able to obtain DTB from loader).

Sponsored by:	DARPA, AFRL
Sponsored by:	HEIF5
 2016-02-11 13:28:52 +00:00
Ruslan Bukin
28029b68c0 Welcome the RISC-V 64-bit kernel. 
This is the final step required allowing to compile and to run RISC-V
kernel and userland from HEAD.

RISC-V is a completely open ISA that is freely available to academia
and industry.

Thanks to all the people involved! Special thanks to Andrew Turner,
David Chisnall, Ed Maste, Konstantin Belousov, John Baldwin and
Arun Thomas for their help.
Thanks to Robert Watson for organizing this project.

This project sponsored by UK Higher Education Innovation Fund (HEIF5) and
DARPA CTSRD project at the University of Cambridge Computer Laboratory.

FreeBSD/RISC-V project home: https://wiki.freebsd.org/riscv

Reviewed by:	andrew, emaste, kib
Relnotes:	Yes
Sponsored by:	DARPA, AFRL
Sponsored by:	HEIF5
Differential Revision:	https://reviews.freebsd.org/D4982
 2016-01-29 15:12:31 +00:00