Commit Graph

57 Commits

Author SHA1 Message Date
Doug Rabson
ac19291f35 Add a workaround to allow us to detect the second pci bus on an HP
Netserver LS/2.

Approved by: jkh
2000-02-23 20:25:06 +00:00
Doug Rabson
9a1498a435 Fix an uninitialised variable which affected probing on some machines.
Approved by: jkh
Reviewed by: gallatin
2000-02-13 09:49:05 +00:00
Andrew Gallatin
da4009202a Allow allows peer pci buses which are directly connected to the RCC host pci
chipset to be probed & attached on newer Dell PowerEdge servers, such as
the 2400 and 4400.

Reviewed by: 	dfr, msmith, jlemon
Tested by:	hnokubi@yyy.or.jp (in a previous incantation)
Approved by:	jkh
2000-02-09 20:05:30 +00:00
Nick Hibma
4f2e8d6383 Add PCI Id's for i810 chipsets.
PR:		16517
Submitted by:	SAKIYAMA Nobuo <sakichan@lares.dti.ne.jp>
Approved by:	jhk
2000-02-07 12:50:33 +00:00
Peter Wemm
4a1e4cb727 Clean up the cfgmech/pci_mechanism debris. The reason for the existance
of this is no longer an issue as we have a replacement driver for the
one that needed it.

Reviewed by:	dfr
2000-01-08 08:31:24 +00:00
Doug Rabson
c954d7368a Don't use a bogus bus number for Ross host-pci bridges.
PR:	kern/15278
Submitted by: Ahmed Benani <ahmed_benani@urbanet.ch>
1999-12-05 18:41:34 +00:00
Matthew N. Dodd
fe0d408987 Remove the 'ivars' arguement to device_add_child() and
device_add_child_ordered().  'ivars' may now be set using the
device_set_ivars() function.

This makes it easier for us to change how arbitrary data structures are
associated with a device_t.  Eventually we won't be modifying device_t
to add additional pointers for ivars, softc data etc.

Despite my best efforts I've probably forgotten something so let me know
if this breaks anything.  I've been running with this change for months
and its been quite involved actually isolating all the changes from
the rest of the local changes in my tree.

Reviewed by:	peter, dfr
1999-12-03 08:41:24 +00:00
Peter Wemm
cde35e1a3d If we have found pci devices via pci_cfgopen(), but don't find a
host->pci bridge specifically, then add a pcib0 device on the motherboard
for the pci bus to hang off.

Requested by:  Anders Andersson <anders@sanyusan.se>
Obtained from: dfr
1999-11-18 08:58:37 +00:00
Alan Cox
eab7cc95c4 Add text for the AMD-751 host-to-PCI and PCI-to-PCI (AGP) bridges. 1999-10-25 06:28:04 +00:00
Peter Wemm
c3aac50f28 $Id$ -> $FreeBSD$ 1999-08-28 01:08:13 +00:00
Peter Wemm
f3b63bd388 Make the identify routine add itself with priority 100 to make sure it
goes after the npx/apm devices and any other motherboard devices that
may get added down the track.
1999-08-22 19:54:11 +00:00
Peter Wemm
accc665bbe Hopefully fix the previous commit, it caused *all* bridges to be detected
as PCI->HOST bridges on my (440BX) box.

My change is to remove the test at the beginning entirely, letting the
switch on the device ID happen first.  If the device ID is unknown, then
(in the default case) check for the generic PCIS_BRIDGE_HOST tag.  This
should allow wierd cases (eg: wpaul's IMS VL bridge) to work by using the
id override.  This strategy is more in line with the other PCI match
methods we use elsewhere,

I only have a limited testbed, but having my USB etc devices detected as
PCI->HOST bridges doesn't look good.
1999-08-10 09:22:21 +00:00
Bill Paul
d9d628b000 Fix nexus_pcib_is_host_bridge() so that it detects my 486's PCI bus
correctly. It has the following code:

        if (class != PCIC_BRIDGE || subclass != PCIS_BRIDGE_HOST)
                return NULL;

My 486 has an Integrated Micro Solutions PCI bridge which identifies
itself as subclass PCIS_BRIDGE_OTHER, not PCIS_BRIDGE_HOST. Consequently,
it gets ignored. In my opinion, the correct test should be:

        if ((class != PCIC_BRIDGE) && (subclass != PCIS_BRIDGE_HOST))
                return NULL;

That way the test still succeeds because the chip's class is PCIC_BRIDGE.
Clearly it's not reasonable to expect all host to PCI bridges to always
have a subclass of PCIS_BRIDGE_HOST since I've got one that doesn't.
This way the sanity test should remain relatively sane while still allowing
some oddball yet correct hardware to work. If somebody has a better way
to do it, go ahead and tweak the test, but be aware that
class == PCIC_BRIDGE and subclass == PCIS_BRIDGE_OTHER is a valid case.

While I was here, I also added an explicit ID string for the IMS chipset.
I also dealt with a minor style nit: it's bad karma not to have a default
case for your switch statements, but the one in this routine doesn't have
one. The default string of "Host to PCI bridge" is now assigned in a
default case of the switch statement instead of initializing "s" with the
string before the switch and then not having any default case.
1999-08-09 21:12:18 +00:00
Peter Wemm
cac6a04400 Don't probe if pci_cfgopen() fails to find pci hardware, like we used to
to.  This might have caused interesting things on non-PCI hardware if
PCI was compiled in.
1999-08-04 13:38:24 +00:00
Mike Smith
850013034a Add support for multiple PCI busses directly connected to the nexus.
This is only partially complete, but allows 450NX-based systems with
more than one PCI bus to be used again.

Submitted by:	dfr
1999-07-16 01:00:30 +00:00
Peter Wemm
8dc26439da Move pcibus (host -> pci bus) probe/attach routines from nexus
to pcibus.c.  pci_cfgopen() becomes static and there are no more
bus #ifdef's in nexus.c.
1999-05-18 20:48:43 +00:00
Stefan Eßer
8277ac255e Make the class code checks in function pci_cfgcheck less strict.
It failed to recognize the PCI bus in a system that had only an
old chip-set (class code 000000) and a Cyclom multiport serial
card on PCI bus 0, but no VGA card or disk or network controller.

PR:		i386/5300
Submitted by:	Nickolay N. Dudorov <nnd@itfs.nsk.su>
1997-12-20 09:04:25 +00:00
Bruce Evans
f71d35e402 Removed unused #includes. 1997-07-20 14:10:18 +00:00
Stefan Eßer
b3daa02e72 Yet another fix for configuration mechanism 1 register accesses:
Adjust the data port address by adding the two low order bits of
the register number. The address port takes only a word address
(i.e. ignores the two low order bits written to it).
1997-05-26 21:52:41 +00:00
Stefan Eßer
64039d403f Fix previous fix: The enable bit is bit 31 (0x8000000) and not bit 15. 1997-05-26 21:25:24 +00:00
Stefan Eßer
e0c57a9615 Set enable bit when writing the configuration address in configuration
mode 1. Omission of this bit makes all config register accesses fail in
on recent chip sets ...

(The problem was reported and debug output provided by: Steve Passe)
1997-05-26 21:11:05 +00:00
Stefan Eßer
5bec615793 Completely replace the PCI bus driver code to make it better reflect
reality. There will be a new call interface, but for now the file
pci_compat.c (which is to be deleted, after all drivers are converted)
provides an emulation of the old PCI bus driver functions. The only
change that might be visible to drivers is, that the type pcici_t
(which had been meant to be just a handle, whose exact definition
should not be relied on), has been converted into a pcicfgregs* .

The Tekram AMD SCSI driver bogusly relied on the definition of pcici_t
and has been converted to just call the PCI drivers functions to access
configuration space register, instead of inventing its own ...

This code is by no means complete, but assumed to be fully operational,
and brings the official code base more in line with my development code.

A new generic device descriptor data type has to be agreed on. The PCI
code will then use that data type to provide new functionality:

1) userconfig support
2) "wired" PCI devices
3) conflicts checking against ISA/EISA
4) maps will depend on the command register enable bits
5) PCI to Anything bridges can be defined as devices,
   and are probed like any "standard" PCI device.

The following features are currently missing, but will be added back,
soon:

1) unknown device probe message
2) suppression of "mirrored" devices caused by ancient, broken chip-sets

This code relies on generic shared interrupt support just commited to
kern_intr.c (plus the modifications of isa.c and isa_device.h).
1997-05-26 15:08:43 +00:00
Stefan Eßer
5c03639065 Mask out revision register in consistency test of class register. 1997-04-09 11:34:50 +00:00
Stefan Eßer
6df09d1e0b Fix spelling of align and interrupt in comments. 1997-04-09 09:16:27 +00:00
Stefan Eßer
b4b8847934 Fix consistency test to not fail on pre PCI 2.0 motherboards 1997-04-09 09:15:03 +00:00
Stefan Eßer
81cf5d7aae improve pcibus_check: Only assume PCI if at least one PCI to anything bridge
on bus 0.
This fixes problems with EISA-only systems mistakenly being assumed to support PCI.
1997-03-05 20:52:00 +00:00
Peter Wemm
6875d25465 Back out part 1 of the MCFH that changed $Id$ to $FreeBSD$. We are not
ready for it yet.
1997-02-22 09:48:43 +00:00
Bruce Evans
4123678332 Sync with <pci/pcibus.h>. pcibus.c unfortunately still compiled (with
only 3 or 4 warnings) when pb_maxirq went away.
1997-01-25 18:51:01 +00:00
Jordan K. Hubbard
1130b656e5 Make the long-awaited change from $Id$ to $FreeBSD$
This will make a number of things easier in the future, as well as (finally!)
avoiding the Id-smashing problem which has plagued developers for so long.

Boy, I'm glad we're not using sup anymore.  This update would have been
insane otherwise.
1997-01-14 07:20:47 +00:00
Nate Williams
62ce633d36 Make the code more consistant by using the INTR*MASK macros througout the
code.

Reviewed by:	bde

[
Bruce suggest removing the macros completely, but I'm not up to that
task quite yet.
]
1997-01-08 16:12:56 +00:00
Satoshi Asami
e30f001135 More merge and update.
(1) deleted #if 0

    pc98/pc98/mse.c

(2) hold per-unit I/O ports in ed_softc

    pc98/pc98/if_ed.c
    pc98/pc98/if_ed98.h

(3) merge more files by segregating changes into headers.

  new file (moved from pc98/pc98):

    i386/isa/aic_98.h

  deleted:

    well, it's already in the commit message so I won't repeat the
    long list here ;)

Submitted by:	The FreeBSD(98) Development Team
1996-10-30 22:41:46 +00:00
Bruce Evans
9b2b0822b7 Removed unused #includes of <i386/isa/icu.h> and <i386/isa/icu.h>. icu.h
is only used by the icu support modules and by a few drivers that know
too much about the icu (most only use it to convert `n' to `IRQn').  isa.h
is only used by ioconf.c and by a few drivers that know too much about
isa addresses (a few have to, because config is deficient).
1996-06-18 01:22:40 +00:00
Stefan Eßer
21219d2116 Change CONF1_ENABLE_MSK to 0x7ff00000 in another attempt to decide
whether a system could possibly support PCI configuration mechanism 1
(or whether it rather is an EISA only system ...).
1996-06-13 21:50:41 +00:00
Stefan Eßer
e20df7fc31 Make pcibus_check() ignore Device/Vendor IDs of all 0. 1996-04-30 21:37:21 +00:00
Bruce Evans
3157adc8af Removed now-unused #includes of <machine/cpu.h>. They were for bootverbose
being declared in the wrong place.
1996-04-07 17:32:42 +00:00
Bruce Evans
a680ab7537 Count PCI irqs in up to 4 ISAish counters named `pci irqnn' instead of
in the clk0 counter.

Reviewed by:	s
1996-03-29 15:01:51 +00:00
Bruce Evans
6ea3e9d839 Completed function declarations and/or added prototypes and/or added
#includes to get prototypes.

pci now uses a different interrupt handler type for interrupts that it
dispatches and the isa interrupt handler type for the interrupts that
it handles.
1995-12-16 00:27:59 +00:00
Poul-Henning Kamp
6f4e0beb7e Staticize and cleanup. 1995-12-10 13:40:44 +00:00
Stefan Eßer
2e80ea0536 Make CONF1_ENABLE_MSK1 even less restriktive: Ignore slot ID ... 1995-10-17 23:30:11 +00:00
Stefan Eßer
0e2f699b9e At least the ASUS Triton motherboards don't disable the PCI bus configuration
accesses after the BIOS bus scan. The previous revision made the assumption,
that every PCI motherboard did ...

Change the test on the initial value of the CONF1_ADDR_PORT register in a way
that makes the probe succeed on triton based motherboards, without breaking
the EISA motherboard that has some non-PCI register at the same address.
1995-10-17 15:23:14 +00:00
Stefan Eßer
287911bd50 Go back to separate tests for configuration mechanism 1 and mechanism 2.
Require the state of the configuration enable bits to be OFF assuming
that the BIOS left them that way, as it should anyway to avoid bad things
to happen.

The tests themselves are copied from the previous release, with the
exception of CONF1_ENABLE_MSK1 having the LSB set. This bit should be
read back as '0', since only DWORD addresses are legal.
1995-10-15 23:43:08 +00:00
Stefan Eßer
c7483249e7 Fix bad typo: CONF1_ENABLE_RES1 was written CONF1_ENABLE_CHK1 ... 1995-10-09 21:56:24 +00:00
Stefan Eßer
77b573149a New approach to the PCI bus configuration mechanism probe problem:
- try to make sure there is any kind of PCI device
- if there is anything at port 0x0cf8, then check for mech. 1 or 2
1995-09-22 19:10:54 +00:00
Stefan Eßer
a3adc4f8c5 Revert most changes of previous commit.
Changes relative to 1.12:
- Put extra instruction between outl()/inl() sequence to prevent the
  old value being read back because of the bus capacitance.
- Additional check for existence of register at CONF2_ENABLE_PORT.
1995-09-18 21:48:39 +00:00
Stefan Eßer
2d14418625 Another try to determine the PCI bus configuration mode (and whether
there is a PCI bus at all) ...

- Do not expect the chip sets to follow even very clearly expressed
  requirements of the PCI 2.0 spec.
- Do not read back the value just written to an I/O port without making
  sure that some other data have crossed the bus in between ...
1995-09-15 21:43:45 +00:00
Stefan Eßer
d7ea35fc88 Improved verification of configuration space accesses working:
Scan for devices instead of assuming that device 0 is present on bus 0
of every PCI motherboard.
1995-09-14 20:27:31 +00:00
Stefan Eßer
cda6791190 Make the PCI host bridge probe code more robust when dealing with chip sets
that use configuration mode 1, but still violate the PCI 2.0 specs ...
(Required for the Compaq Proliant, for example.)
1995-09-13 17:03:47 +00:00
Stefan Eßer
d2a2d5ec41 The PCI config mechanism 1 test failed for the Intel Aries.
Make it less strict ...

Submitted by:	NIIMI Satoshi <sa2c@and.or.jp>
1995-06-30 16:11:42 +00:00
Stefan Eßer
0847c06d2e PCI configuration mechanism now determined by a method, that doesn't
fail on new hardware (Compaq Prolinea and Compaq Prosignea), and that
doesn't erroneously identify old mech. 2 chip sets as using mech. 1.
(See section 3.6.4.1.1 of the PCI bus specs rev. 2.0)
1995-06-28 15:54:57 +00:00
Stefan Eßer
0f29bf015c Correct pcibus_setup() to return as soon as one test succeeds. 1995-03-22 21:35:39 +00:00