and set up the hardware accordingly on each transfer. This replaces the old
configuration done via sysctl, and allows both fdt configuration data and
userland control via the spigen device to work.
Submitted by: Bob Frazier
Differential Revision: https://reviews.freebsd.org/D15031
The test for checking if the clock have a mux was inverted and the mask
to calculate the parent index was wrong was wrong too.
It means that upon creation the incorrect parent was resolved as the current
one and upon reparent the switch was never made.
Pointy hat (lots of them): manu
Using MMCCAM on AllWinner boards is now possible, reaching highest
possible data transfer speed.
For now, MMCCAM doesn't scan cards on boot. This means that scanning
has to be done manually and that it's not possible to mount root FS
from MMC/SD card since there is no block device at the boot time.
For manually scanning the cards, run:
# camcontrol rescan X:0:0
Where X is the bus number (look at camcontrol devlist to determine
bus number assigned to the MMC controller).
Reviewed by: manu
Approved by: imp (mentor)
Differential Revision: https://reviews.freebsd.org/D15891
Each clock drivers if now fully subclassed, this have the advantage that
we can control the probe order.
Some clocks can have parents from other drivers, for example clocks in the
sun8i_r driver uses clocks from the main clock driver.
This worked before because the sun8i_r node is after the main ccu node in the
dtb and driver are probed in DTB order. This cannot work with the Display
Engine clocks as it is the first node in the DTB.
Tested on: A83T, H5 A64
Tested on: A20 (kevans)
r329104 imported 4.15 DTS which brought CCU to a10/a20. In the process, they
swapped the ordering of 'clocks' for allwinner,sun4i-a10-ahci on both
sun4i-a10 and sun7i-a20 from PLL, Gate to Gate, PLL.
Swap it in the driver.
Note: At this time, this has only been tested on a single board from one of
the supported SoCs. This is enough to boot the board from MMC and have
functional USB- which is still an improvement over where we were at just
before with no functional clocks.
Differential Revision: https://reviews.freebsd.org/D15810
This happens in two cases for a20 clocks:
pll_core for 'n' factor:
factor=0, val=1
factor=n, val=n
ahb divisor:
factor=0,val=/2
factor=n,val=/2^n
Reviewed by: manu
Differential Revision: https://reviews.freebsd.org/D15806
The timer present in allwinner A64 SoC is unstable, value can jump backward
or forward.
It was found that when bit 11 and upper roll over the low bits can sometimes
being read as all as 1 or all as 0.
Simply ignore the values for those cases.
pmc_process_interrupt takes 5 arguments when only 3 are needed.
cpu is always available in curcpu and inuserspace can always be
derived from the passed trapframe.
While facially a reasonable cleanup this change was motivated
by the need to workaround a compiler bug.
core2_intr(cpu, tf) ->
pmc_process_interrupt(cpu, ring, pmc, tf, inuserspace) ->
pmc_add_sample(cpu, ring, pm, tf, inuserspace)
In the process of optimizing the tail call the tf pointer was getting
clobbered:
(kgdb) up
at /storage/mmacy/devel/freebsd/sys/dev/hwpmc/hwpmc_mod.c:4709
4709 pmc_save_kernel_callchain(ps->ps_pc,
(kgdb) up
1205 error = pmc_process_interrupt(cpu, PMC_HR, pm, tf,
resulting in a crash in pmc_save_kernel_callchain.
- Calculate the number of segments based on the page size
- Add some comments on dma function so it's easier to read
- Only enable interrupts on the last dma segment
- If the segments size is the max transfer size, use the special size 0
for the controller.
- The max_data ivars is in block so calculate it properly.
It was introduced to the tree in r169320 and r169321 in May 2007.
It never got much use and never became a kernel default. The code
duplicates the default path quite a bit, with slight modifications. Just
yank out the cruft. Whatever goals were being aimed for can probably be met
within the existing framework, without a flag day option.
Mostly mechanical change: 'unifdef -m -UINTR_FILTER'.
Reviewed by: mmacy
Sponsored by: Dell EMC Isilon
Differential Revision: https://reviews.freebsd.org/D15546
the DMAP region on arm64.
We already have the needed information to build these tables, we just need
to extract it. This significantly simplifies the code.
Obtained from: ABT Systems Ltd
Sponsored by: Turing Robotic Industries
On arm64 we will need to get the phys_avail array from before the kernel
is excluded to create teh DMAP region. In preperation for this pass in the
array length into regions_to_avail.
This will help simplify the arm64 code and allow us to properly exclude
memory that should never be mapped.
Obtained from: ABT Systems Ltd
Sponsored by: Turing Robotic Industries
This reduces the overhead when we have many small mappings, e.g. on some
EFI systems. This is to help use this code on arm64 where we may have a
large number of entries from the EFI firmware.
Obtained from: ABT Systems Ltd
Sponsored by: Turing Robotic Industries
Differential Revision: https://reviews.freebsd.org/D15477
Always disable FIFO access as we don't use it.
Rename some register bits so they are in sync with the register name.
While here add my copyright as I've probably wrote 70% of the code here.
The module uses the mod clock and not the ahb one.
We need to set the mod clock to twice the speed requested as the smallest
divider in the controller is 2.
The clock test function weren't calculating the register value best on the
best div but on the max one.
The cdr2 test function was using the cdr1 formula.
Pointy Hat: manu
This change updates arm, arm64 and mips achitectures. Additionally, it
removes redundant checks for kdb_active where it already results in
kdb_reenter() and adds kdb_reenter() calls where they were missing.
Some architectures check the return value of kdb_trap(), but some don't.
I haven't changed any of that.
Some trap handling routines have a return code. I am not sure if I
provided correct ones for returns after kdb_reenter(). kdb_reenter
should never return unless kdb_jmpbufp is NULL for some reason.
Only compile tested for all affected architectures. There can be bugs
resulting from my poor understanding of architecture specific details.
Reported by: jhb
Reviewed by: jhb, eadler
MFC after: 4 weeks
Differential Revision: https://reviews.freebsd.org/D15431
Don't enable regulator on attach but dealt with them on power_up/power_off
Only set the voltage for the signaling regulator since I don't have boards
that can change the supply voltage.
Enable 1.8v signaling voltage.
Only do a reset of the controller at attach and init it at power_up.
We use to enable some interrupts in reset, only enable the interrupts
we are interested in when doing a request.
While here remove the regulators handling in power_on as it is very wrong
and will be dealt with in another commit.
Tested on: A31, A64
With Linux 4.17 dts the compatible for the prcm added 'simplebus' we mean
that the simplebus driver will attach to it at the BUS_PASS_BUS pass.
Change the pass for the prcm driver to be at BUS_PASS_BUS so we will win
the attach.
This introduce a problem as this driver needs the ti_scm one to be already
attached. ti_scm also attach at BUS_PASS_BUS but after the prcm one as it is
after in the dtb and the simplebus driver simpy walk the tree to attach it's
children.
Use the bus_new_pass method to defer the frequencies read at BUS_PASS_TIMER.
This fixes booting on BeagleBone*
Reported by: many
a gpio pin. If neither of the options is specified, pre-set the pin's
output value to the pin's current input value, to achieve glitch-free
transitions to output mode on pins that are pulled up or down at reset
or via fdt pinctrl data.
mode or not. An earlier attempt to make this work was done in r320456, by
always reading the pad status register (PSR) instead of the data register.
But it turns out the values in PSR only reflect the electrical level of an
output pin if the pad is configured with the SION (Set Input On) bit in the
pinmux config, and most output gpio pads are not configured that way.
So now a gpio read is done by returning the value from the data register,
which works right whether the pin is configured for input or output, unless
the pin has been set for OPENDRAIN mode, in which case the PSR is read
instead. For this to work, the pin must also be configured with SION turned
on in the fdt pinmux data, which is a reasonable thing to require for the
unusual case of reading an open-drain output pin.
Include source files and drivers for Marvell ArmadaXP and Armada38X
in GENERIC kernel config.
Submitted by: Michal Mazur <mkm@semihalf.com>
Rafal Kozik <rk@semihalf.com>
Reviewed by: manu
Tested by: manu
Obtained from: Semihalf
Sponsored by: Stormshield
Marvell SoC identification function was called by SYSINIT on all armv7
platforms, which brakes platforms other than Marvell built with
GENERIC config. Fix this by shifting SoC identifying to Marvell platform
initialization.
Submitted by: Patryk Duda <pdk@semihalf.com>
Reviewed by: manu
Tested by: manu
Obtained from: Semihalf
Sponsored by: Stormshield
r332839 changed number of cells per interrupt for local_intc from 1 to 2
to pass type of IRQ. Driver expected only 1 cell so after r332839
all interrupt children of local_intc failed to allocate IRQ resource.
Fix this regression by relaxing check for number of cells in interrupt
property to be either 1 or 2.
PR: 227904
Dumpers may wish to print messages from an initialization hook; this
change ensures that such messages aren't mixed with output from the
generic dump code.
MFC after: 1 week
always use 'M. Warner Losh' for consistency.
'All Rights Reserved.' was prescribed by the Buenos Aires Copyright
Convention of 1910, but has been mostly dead since the early 1990's
and completely meaningless since 2000 when Nicaragua ratified the
Berne convention.
Some files not done due to ambiguity of various types.
Move the allwinner early printf support to the snps driver as it
should work with all implementation.
While here add instruction for enabling it on 64bits SoCs.
Name each ehci driver uniquely.
This remove the warning printed at each arm boot :
module_register: cannot register simplebus/ehci from kernel; already loaded from kernel
Name each ahci driver uniquely.
This remove the warning printed at each arm boot :
module_register: cannot register simplebus/ahci from kernel; already loaded from kernel
