take advantage of it instead of duplicating it. This reduces the size of
the i386 GENERIC kernel by about 4k. The only potential in-tree user left
unconverted is xe(4), which generally should be changed to use miibus(4)
instead of implementing PHY handling on its own, as otherwise it makes not
much sense to add a dependency on miibus(4)/mii_bitbang(4) to xe(4) just
for the MII bitbang'ing code. The common MII bitbang'ing code also is
useful in the embedded space for using GPIO pins to implement MII access.
- Based on lessons learnt with dc(4) (see r185750), add bus barriers to the
MII bitbang read and write functions of the other drivers converted in
order to ensure the intended ordering. Given that register access via an
index register as well as register bank/window switching is subject to the
same problem, also add bus barriers to the respective functions of smc(4),
tl(4) and xl(4).
- Sprinkle some const.
Thanks to the following testers:
Andrew Bliznak (nge(4)), nwhitehorn@ (bm(4)), yongari@ (sis(4) and ste(4))
Thanks to Hans-Joerg Sirtl for supplying hardware to test stge(4).
Reviewed by: yongari (subset of drivers)
Obtained from: NetBSD (partially)
- Turn on WOL bits in suspend/shutdown method.
- WOL is disabled in resume routine as WOL can interfere normal
Rx operation.
- Move stge_reset() to stge_init_locked() as resetting hardware
clears configured Rx information which in turn results in
non-working Rx module after suspend/shutdown operation.
controller ported from NetBSD. It supports the following Gigabit
Ethernet adapters.
o Antares Microsystems Gigabit Ethernet
o ASUS NX1101 Gigabit Ethernet
o D-Link DL-4000 Gigabit Ethernet
o IC Plus IP1000A Gigabit Ethernet
o Sundance ST-2021 Gigabit Ethernet
o Sundance ST-2023 Gigabit Ethernet
o Sundance TC9021 Gigabit Ethernet
o Tamarack TC9021 Gigabit Ethernet
The IP1000A Gigabit Ethernet is also found on some motherboards
(LOM) from ABIT.
Unlike NetBSD stge(4) it does not require promiscuous mode operation
to revice packet and it supports all hardware features(TCP/UDP/IP
checksum offload, VLAN tag stripping/insertion features and JUMBO
frame) and polling(4).
Due to lack of hardware, hardwares that have TBI trantransceivers
were not tested at all.
Special thanks to wpaul who provided valauble datasheet for the
controller and helped to debug jumbo frame related issues. Whitout
his datasheet I would have spent many hours to debug this chip.
Tested on: i386, sparc64
