Commit Graph

24 Commits

Author SHA1 Message Date
Scott Long
c68534f1d5 Update PCI drivers to no longer look at the MEMIO-enabled bit in the PCI
command register.  The lazy BAR allocation code in FreeBSD sometimes
disables this bit when it detects a range conflict, and will re-enable
it on demand when a driver allocates the BAR.  Thus, the bit is no longer
a reliable indication of capability, and should not be checked.  This
results in the elimination of a lot of code from drivers, and also gives
the opportunity to simplify a lot of drivers to use a helper API to set
the busmaster enable bit.

This changes fixes some recent reports of disk controllers and their
associated drives/enclosures disappearing during boot.

Submitted by:	jhb
Reviewed by:	jfv, marius, achadd, achim
MFC after:	1 day
2013-08-12 23:30:01 +00:00
Juli Mallett
f1bd1e9dd7 Remove comments about creating DMA tags as children of the DMA tags of their
parent bus where the code has now been modified to do so.

Reviewed by:	scottl
2012-03-12 19:29:32 +00:00
Attilio Rao
884015f6fc Add sysctls in ahd(4) in order to keep track of different classes of
errors. So far 3 different classes are present (correctable,
uncorrectable and fatal) but more can be added easilly.

Obtained from:	Sandvine Incorporated
Reviewed by:	emase, gibbs
Sponsored by:	Sandvine Incorporated
MFC:		2 weeks
2009-11-13 22:57:20 +00:00
Warner Losh
155a83e87a remove now-redunant cardbus attachment. 2009-03-09 13:23:54 +00:00
John-Mark Gurney
378f231e7d add a newbus method for obtaining the bus's bus_dma_tag_t... This is
required by arches like sparc64 (not yet implemented) and sun4v where there
are seperate IOMMU's for each PCI bus...  For all other arches, it will
end up returning NULL, which makes it a no-op...

Convert a few drivers (the ones we've been working w/ on sun4v) to the
new convection...  Eventually all drivers will need to replace the parent
tag of NULL, w/ bus_get_dma_tag(dev), though dev is usually different for
each driver, and will require hand inspection...

Reviewed by:	scottl (earlier version)
2006-09-03 00:27:42 +00:00
Justin T. Gibbs
6bdc5bdf68 Set allow_memio to 1 if fetching the allow_memio hint fails. This
is the default behavior according the the bootverbose printf in the
failure case.
2005-09-22 04:56:59 +00:00
Warner Losh
494f3ca182 Use BUS_PROBE_DEFAULT for pci probe return value 2005-03-05 19:24:22 +00:00
Warner Losh
098ca2bda9 Start each of the license/copyright comments with /*-, minor shuffle of lines 2005-01-06 01:43:34 +00:00
Nate Lawson
5f96beb9e0 Convert callers to the new bus_alloc_resource_any(9) API.
Submitted by:	Mark Santcroos <marks@ripe.net>
Reviewed by:	imp, dfr, bde
2004-03-17 17:50:55 +00:00
Justin T. Gibbs
b3b25f2cbf ahc_eisa.c:
ahc_pci.c:
ahd_pci.c:
aic7xxx.c:
aic79xx.c:
aic_osm_lib.c:
aic_osm_lib.h:
	Use common OSM routines from aic_osm_lib for bus dma operations,
	delay routines, accessing CCBs, byte swapping, etc.

aic7xxx_pci.c:
	Provide a better description for the 2915/30LP on attach.

aic7xxx.c:
aic79xx.c:
aic7770.c:
aic79xx_pci.c:
aic7xxx_pci.c:
aic7xxx_93cx6.c:
	Move FBSDID behind an ifdef so that these core files will
	still compile under other OSes.

aic79xx.h:
aic79xx_pci.c:
aic79xx.seq:
	To speed up non-packetized CDB delivery in Rev B, all CDB
	acks are "released" to the output sync as soon as the
	command phase starts.  There is only one problem with this
	approach.  If the target changes phase before all data are
	sent, we have left over acks that can go out on the bus in
	a data phase.  Due to other chip contraints, this only
	happens if the target goes to data-in, but if the acks go
	out before we can test SDONE, we'll think that the transfer
	has completed successfully.  Work around this by taking
	advantage of the 400ns or 800ns dead time between command
	phase and the REQ of the new phase.  If the transfer has
	completed successfully, SCSIEN should fall *long* before we
	see a phase change.  We thus treat any phasemiss that
	occurs before SCSIEN falls as an incomplete transfer.

	aic79xx.h:
		Add the AHD_FAST_CDB_DELIVERY feature.

	aic79xx_pci.c:
		Set AHD_FAST_CDB_DELIVERY for all Rev. B parts.

	aic79xx.seq:
		Test for PHASEMIS in the command phase for
		all AHD_FAST_CDB_DELIVERY controlelrs.

ahd_pci.c:
ahc_pci.c:
aic7xxx.h:
aic79xx.h:
	Move definition of controller BAR offsets to core header files.

aic7xxx.c:
aic79xx.c:
	In the softc free routine, leave removal of a softc from the
	global list of softcs to the OSM (the caller of this routine).
	This allows us to avoid holding the softc list_lock during device
	destruction where we may have to sleep waiting for our recovery
	thread to halt.

ahc_pci.c:
	Use ahc_pci_test_register access to validate I/O mapped in
	addition to the tests already performed for memory mapped
	access.

	Remove unused ahc_power_state_change() function.  The PCI
	layer in both 4.X and 5.X now offer this functionality.

ahd_pci.c:
	Remove reduntant definition of controller BAR offsets.  These
	are also defined in aic79xx.h.

	Remove unused ahd_power_state_change() function.  The PCI
	layer in both 4.X and 5.X now offer this functionality.

aic7xxx.c:
aic79xx.c:
aic79xx.h:
aic7xxx.h:
aic7xxx_osm.c:
aic79xx_osm.c:
	Move timeout handling to the driver cores.  In the case
	of the aic79xx driver, the algorithm has been enhanced
	to try target resets before performing a bus reset.  For
	the aic7xxx driver, the algorithm is unchanged.  Although
	the drivers do not currently sleep during recovery (recovery
	is timeout driven), the cores do expect all processing to
	be performed via a recovery thread.  Our timeout handlers
	are now little stubs that wakeup the recovery thread.

aic79xx.c:
aic79xx.h:
aic79xx_inline.h:
	Change shared_data allocation to use a map_node so
	that the sentinel hscb can use this map node in
	ahd_swap_with_next_hscb.  This routine now swaps
	the hscb_map pointer in additon to the hscb
	contents so that any sync operations occur on
	the correct map.

	physaddr -> busaddr

	Pointed out by: Jason Thorpe <thorpej@wasabisystems.com>

aic79xx.c:
	Make more use of the in/out/w/l/q macros for accessing
	byte registers in the chip.

	Correct some issues in the ahd_flush_qoutfifo() routine.
	    o Run the qoutfifo only once the command channel
	      DMA engine has been halted.  This closes a window
	      where we might have missed some entries.
	    o Change ahd_run_data_fifo() to not loop to completion.
	      If we happen to start on the wrong FIFO and the other
	      FIFO has a snapshot savepointers, we might deadlock.
	      This required our delay between FIFO tests to be
	      moved to the ahd_flush_qoutfifo() routine.
	    o Update/add comments.
	    o Remove spurious test for COMPLETE_DMA list being empty
	      when completing transactions from the GSFIFO with
	      residuals.  The SCB must be put on the COMPLETE_DMA
	      scb list unconditionally.
	    o When halting command channel DMA activity, we must
	      disable the DMA channel in all cases but an update
	      of the QOUTFIFO.  The latter case is required so
	      that the sequencer will update its position in the
	      QOUTFIFO.  Previously, we left the channel enabled
	      for all "push" DMAs.  This left us vulnerable to
	      the sequencer handling an SCB push long after that
	      SCB was already processed manually by this routine.
	    o Correct the polarity of tests involving
	      ahd_scb_active_in_fifo().  This routine returns
	      non-zero for true.

	Return to processing bad status completions through
	the qoutfifo.  This reduces the time that the sequencer
	is kept paused when handling transactions with bad
	status or underruns.

	When waiting for the controller to quiece selections,
	add a delay to our loop.  Otherwise we may fail to wait
	long enough for the sequencer to comply.

	On H2A4 hardware, use the slow slewrate for non-paced
	transfers.  This mirrors what the Adaptec Windows
	drivers do.

	On the Rev B. only slow down the CRC timing for
	older U160 devices that might need the slower timing.
	We define "older" as devices that do not support
	packetized protocol.

	Wait up to 5000 * 5us for the SEEPROM to become unbusy.
	Write ops seem to take much longer than read ops.

aic79xx.seq:
	For controllers with the FAINT_LED bug, turn the diagnostic
	led feature on during selection and reselection.  This covers
	the non-packetized case.  The LED will be disabled for
	non-packetized transfers once we return to the top level idle
	loop.  Add more comments about the busy LED workaround.

	Extend a critical section around the entire
	command channel idle loop process.  Previously
	the portion of this handler that directly manipulated
	the linked list of completed SCBs was not protected.
	This is the likely cause of the recent reports of
	commands being completed twice by the driver.

	Extend critical sections across the test for,
	and the longjump to, longjump routines.  This
	prevents the firmware from trying to jump to
	a longjmp handler that was just cleared by the
	host.

	Improve the locations of several critical section
	begin and end points.  Typically these changes
	remove instructions that did not need to be
	inside a critical section.

	Close the "busfree after selection, but before busfree
	interrupts can be enabled" race to just a single sequencer
	instruction.  We now test the BSY line explicitly before
	clearing the busfree status and enabling the busfree
	interrupt.

	Close a race condition in the processing of HS_MAILBOX
	updates.  We now clear the "updated" status before the
	copy.  This ensures that we don't accidentally clear
	the status incorrectly when the host sneaks in an update
	just after our last copy, but before we clear the status.
	This race has never been observed.

	Don't re-enable SCSIEN if we lose the race to disable SCSIEN
	in our interrupt handler's workaround for the RevA data-valid
	too early issue.

aic79xx_inline.h:
	Add comments indicating that the order in which bytes are
	read or written in ahd_inw and ahd_outw is important.  This
	allows us to use these inlines when accessing registers with
	side-effects.

aic79xx_pci.c:
	The 29320 and the 29320B are 7902 not 7901 based products.
	Correct the driver banner.

aic7xxx.h:
	Enable the use of the auto-access pause feature
	on the aic7870 and aic7880.  It was disabled due
	to an oversight.

aic7xxx.reg:
	Move TARG_IMMEDIATE_SCB to alias LAST_MSG to
	avoid leaving garbage in MWI_RESIDUAL.  This
	prevents spurious overflows whn operating target
	mode on controllers that require the MWI_RESIDUAL
	work-around.

aic7xxx.seq:
	AHC_TMODE_WIDEODD_BUG is a bug, not a softc flag.
	Reference the correct softc field when testing
	for its presence.

	Set the NOT_IDENTIFIED and NO_CDB_SENT bits
	in SEQ_FLAGS to indicate that the nexus is
	invalid in await busfree.

aic7xxx_93cx6.c:
	Add support for the C56/C66 versions of the EWEN and EWDS
	commands.

aic7xxx.c:
aic7xxx_pci.c:
	Move test for the validity of left over BIOS data
	to ahc_test_register_access().  This guarantees that
	any left over CHIPRST value is not clobbered by our
	register access test and lost to the test that was
	in ahc_reset.
2003-12-17 00:02:10 +00:00
Warner Losh
347934fa63 Sometimes cardbus attachments don't attach, so while we track down
this problem put these lines back in.  While they should be
unnecessary, they appear to be sometimes necessary.

Reviewed in concept: dfr
Approved by: re (scottl@)
2003-11-28 05:28:29 +00:00
Doug Rabson
0be389f3ca Remove explicit cardbus attachments from drivers where this is identical
to the pci attachment. Cardbus is a derived class of pci so all pci
drivers are automatically available for matching against cardbus devices.

Reviewed by: imp
2003-11-03 09:22:18 +00:00
Dag-Erling Smørgrav
76bfe7b119 0x7FFFFFFFFF is >32 bits and needs an explicit LL. 2003-10-23 13:42:03 +00:00
John Baldwin
e27951b29c Use PCIR_BAR(x) instead of PCIR_MAPS.
Glanced over by:	imp, gibbs
Tested by:		i386 LINT
2003-09-02 17:30:40 +00:00
David E. O'Brien
aad970f1fe Use __FBSDID().
Also some minor style cleanups.
2003-08-24 17:55:58 +00:00
Scott Long
f6b1c44d1f Mega busdma API commit.
Add two new arguments to bus_dma_tag_create(): lockfunc and lockfuncarg.
Lockfunc allows a driver to provide a function for managing its locking
semantics while using busdma.  At the moment, this is used for the
asynchronous busdma_swi and callback mechanism.  Two lockfunc implementations
are provided: busdma_lock_mutex() performs standard mutex operations on the
mutex that is specified from lockfuncarg.  dftl_lock() is a panic
implementation and is defaulted to when NULL, NULL are passed to
bus_dma_tag_create().  The only time that NULL, NULL should ever be used is
when the driver ensures that bus_dmamap_load() will not be deferred.
Drivers that do not provide their own locking can pass
busdma_lock_mutex,&Giant args in order to preserve the former behaviour.

sparc64 and powerpc do not provide real busdma_swi functions, so this is
largely a noop on those platforms.  The busdma_swi on is64 is not properly
locked yet, so warnings will be emitted on this platform when busdma
callback deferrals happen.

If anyone gets panics or warnings from dflt_lock() being called, please
let me know right away.

Reviewed by:	tmm, gibbs
2003-07-01 15:52:06 +00:00
Justin T. Gibbs
8270490a58 hc_eisa.c:
ahc_pci.c:
ahd_pci.c:
        Don't bogusly use the BUS_DMA_ALLOCNOW flag in our psuedo
        parent bus dma tag.
2003-05-03 23:27:57 +00:00
Scott Long
1c75404899 Convert the use of MAXBSIZE in the dma tag to more appropriate values.
Use BUS_SPACE_MAXSIZE_32BIT for the parent dma tags, and
(NSEGS - 1) * PAGE_SIZE for the data buffer tags.  FreeBSD/sparc64 is
more strict about checking these values that other arches.
2002-12-31 04:22:36 +00:00
Scott Long
97cae63d7f Last minute fixes to ahc and ahd:
ahd_pci.c:
	Retrieve the allow_memio hint from the resource manager to
	determine whether or not to try PCI MEMIO.

aic79xx_osm.h:
aic7xxx_osm.h:
	Don't wrongly abuse the callout_reset() interface when trying
	to abuse timeouts generated from the CAM layer.  This fixes the
	console freeze and lost timeout problem that many have reported,
	especially on SMP systems.

aic79xx_pci.c
aic7xxx_pci.c
	Rewrite the MEMIO test routine to prevent certain broken chipsets
	from trying to burst multiple DWORDs to the registers.  Also make
	the routine better detect byte merging by the host bridge and
	deal with it.

aic79xx.reg:
	Correct an incorrect register definition.

Approved by:	re (rwatson, jhb)
2002-12-04 22:51:29 +00:00
Scott Long
add6879424 Remove redundant check for chip type being PCI-X.
PCI-X only workarounds are automatically masked out
if we are operating in PCI mode.

Make use of ahd_pci_test_register_access()

Approved by:	re (blanket)
2002-12-01 07:52:35 +00:00
Justin T. Gibbs
ccbe423c8f Never allow memory mapped I/O in PCI-X mode on controllers that
do not support that configuration.  This should fix problems with
embedded 7902 controllers running in PCI-X mode.
2002-10-16 02:59:03 +00:00
Justin T. Gibbs
0889fb1da5 Expand vendor ID. 2002-09-26 21:50:27 +00:00
Justin T. Gibbs
cdd49e97b4 Hook up the ahd driver. 2002-06-06 16:35:58 +00:00
Justin T. Gibbs
17d2475554 Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X
SCSI Controller chip.
2002-06-05 19:52:45 +00:00