Commit Graph

2454 Commits

Author SHA1 Message Date
Rui Paulo
9e63671c57 Updates to i.MX53:
* Define support for the SDHCI driver, although it doesn't work yet
* Fix the memory mappings for IPU [1]

Reviewed by:	ray [1]
2014-04-08 04:05:04 +00:00
Rui Paulo
9d3cc729fb Move sys/arm/econa to sys/arm/cavium/cns11xx. 2014-04-07 05:33:30 +00:00
Ian Lepore
0b7d5b8f89 Tell VM we now have ARM platforms with physically discontiguous memory. 2014-04-06 21:40:39 +00:00
Luiz Otavio O Souza
1f1e8f1681 Partially revert r264083.
While it is the recommended initialization procedure, it hangs on the reset
of the second GPIO module on pandaboard.

Removes the module reset for now as more investigation would be needed.

Reported by:	jceel
2014-04-06 17:09:51 +00:00
Ian Lepore
2d1e88da97 Add a couple more required TLB flushes.
These should have been part of r264129, they are part of the overall set
of changes that got several weeks of testing.  I must have fumbled them
while merging various patchsets.
2014-04-06 00:17:41 +00:00
Rui Paulo
87c6502bba Follow files.imx51 and add vt support. 2014-04-05 23:16:51 +00:00
Rui Paulo
9fe6f910fd Remove code under PMAP_CACHE_VIVT that is not compiled anymore.
This is for ARMv4/ARMv5 and it doesn't belong in ARMv6 code.

Reviewed by:	ian
2014-04-05 18:13:28 +00:00
Luiz Otavio O Souza
db8a14ec74 - Fix the setup of interrupts for banks 2 and 3 on AM335x.
On AM335x each one of the four GPIO banks has two physical interrupt
    lines, so we now allocate resources and setup our interrupt handler for
    all the (8) available interrupts.

    On OMAP3 and OMAP4 there is only one interrupt for each GPIO bank (6
    banks, 6 interrupts), but there are two set of registers where the
    first one is used to setup the delivery of interrupts to the MPU and
    the second set, setup the delivery of interrupts to the DSP.

    On AM335x, each set of registers controls each one of the interrupt
    lines.

- Remove nonexistent registers for OMAP4 and AM335x, replace their use with
  the correct ones for these SoCs.

- Remove stray whitespace.

Based on OMAP3, OMAP4 and AM335x TRMs.

Tested on Beaglebone-black.
2014-04-05 17:53:59 +00:00
Ruslan Bukin
11a99c6984 Correct the end address of the video frame buffer.
This fixes problem that sometimes display suddenly
goes blank.
2014-04-05 16:38:27 +00:00
Ian Lepore
78806b5ec8 Enable SMP for Pandaboard. 2014-04-04 20:58:45 +00:00
Ian Lepore
de6a23b300 Switch wandboards over to the common IMX6 kernel config, which has SMP
enabled.  Also switch IMX6 to use SCHED_ULE.

The now-unreferenced WANDBOARD.common config will be deleted after giving
folks who may be including it a heads-up to switch to IMX6.
2014-04-04 20:42:44 +00:00
Ian Lepore
e69ba7c708 We don't support any ARM systems with an ISA bus and don't need a freelist
of memory to support ISA addressing limitations.
2014-04-04 19:35:38 +00:00
Ian Lepore
24ca71778e Allocate per-cpu resources for doing pmap_zero_page() and pmap_copy_page().
This is performance enhancement rather than bugfix.
2014-04-04 17:57:49 +00:00
Ian Lepore
a2f5bf29cd Fix TLB maintenance issues for armv6 and armv7.
- Add cpu_cpwait to comply with the convention.
  - Add missing TLB invalidations, especially in pmap_kenter & pmap_kremove
    with distinguishing between D and ID pages.
  - Modify pmap init/bootstrap invalidations to ID, just to be safe.
  - Fix TLB-inv and PTE_SYNC ordering.

This combines changes submitted by ian@, cognet@, and Wojciech Macek,
which have all been tested together as a unit.
2014-04-04 17:45:39 +00:00
Ian Lepore
028a159090 Fix TTB set operation for armv7.
Perform sychronization (by "isb" barrier) after TTB is set.  This
is done to ensure that TLB invalidation always executes after
TTB modification and operates on valid CP15 data (per specification).

Submitted by:	Wojciech Macek <wma@semihalf.com>
Reviewed by:	ian@, cognet@
2014-04-04 17:39:05 +00:00
Ian Lepore
453efe588d Flag several sysctl variables as tunables. 2014-04-04 15:31:57 +00:00
Ian Lepore
922e7b19a7 Adjust the comments about translating clock divisor bits to match recent
code changes.
2014-04-04 15:03:03 +00:00
Ruslan Bukin
10b54ef6a9 Remove unused prototype. 2014-04-04 05:05:43 +00:00
Ian Lepore
05f1e1778e Let's try having just one mmc/sd controller driver.
Pointed out by:	gjb
2014-04-04 03:48:43 +00:00
Ian Lepore
d9da5f55cd Use the sdhci driver for Pandaboard. 2014-04-04 03:24:19 +00:00
Ian Lepore
8a9361b862 Switch OMAP4 (Pandaboard et. al.) to use the ti_sdhci driver. 2014-04-04 03:11:06 +00:00
Ian Lepore
927f53548b Fix the logic for translating between MMCHS and SDHCI clock divisors.
Submitted by:	Svatopluk Kraus <onwahe@gmail.com>
2014-04-04 03:04:29 +00:00
Ian Lepore
ef3c56a250 Various fixes to the ti_sdhci driver, mostly to make it work on Pandaboard.
- Don't allow high-speed mode on OMAP4 due to hardware erratum.
 - Check the proper bit in the status register when waiting for the
   controller to come out of reset.
 - Add handling for the "non-removable" fdt property by always returning
   "card is present" status.
 - Add the non-removable property for the MMC card on a Beaglebone Black.
 - Add the non-removable property for Pandaboard as a workaround.

For Pandaboard the card detect pin is handled by the twl6030 fpga device
which gets an interrupt on pin change and then has to query the fpga
for the actual status.  We don't have code to do that yet.

Submitted by:	Svatopluk Kraus <onwahe@gmail.com>
2014-04-04 00:59:40 +00:00
Ian Lepore
e354cdacde Actually save the clock frequency retrieved from fdt data. I fumbled
this when I converted getprop to getencprop.

Submitted by:	Thomas Skibo
Pointy hat to:	ian
2014-04-04 00:00:05 +00:00
Luiz Otavio O Souza
9b1cba84ac Move the GPIO bank initialization to a new function to make easier to detect
errors.

Reset the GPIO module during the initialization.  This is guaranteed to be
the same as a hardware reset.  Tested on AM335x (BBB) and checked against
the omap3 and omap4 TRM.

Do a better job freeing resources when there are errors and on
ti_gpio_detach().
2014-04-03 17:55:08 +00:00
Ruslan Bukin
12899ea195 - Setup both secure and non-secure timer IRQs.
We don't know our ARM security state, so one of them will operate.
- Don't set frequency, since it's unpossible in non-secure state.
  Only rely on DTS clock-frequency value or get clock from timer.

Discussed with:	ian, cognet
2014-04-03 05:48:56 +00:00
Ian Lepore
0140748043 Rework the cpu frequency management code for imx6.
This adds the concept of "operating points," combinations of frequency
and voltage at which the cpu is known to work correctly.  Some day these
should come from FDT data, but for now the table is hard-coded.

This also allows tuning the min and max operating frequencies.  The min
frequency is what the thermal management code will slow down to if the
core temperature gets too high.  The max frequency is what gets used if
the temperature is okay.

Normally the max cannot be set higher than the value burned into the
ocotp fuses as the chip's rated max, but there is now a new sysctl+tunable
cpu_overclock_enable; when set to non-zero it allows raising the frequency
above the ocotp value: USE WITH CARE!  (At least one of my imx6 boards
has a cpu whose ocotp values never got set correctly; they claim a max
of 792mhz, but the physical markings on the chip say it's good to 1ghz.)

Because all these values affect the entire SoC, there is a new sysctl
node, hw.imx6, where all these values live.  The values that are currently
under dev.imx6_anatop.0 should probably move to hw.imx6 too, because
"anatop" doesn't even mean anything to me, let alone to an end user.
2014-04-02 21:34:48 +00:00
Ian Lepore
a3ff7ef69c Switch imx6 to using the mpcore per-cpu event timers, but continue to use
the GPT timer, which is fixed-frequency, as a timecounter.
2014-04-02 21:06:43 +00:00
Ian Lepore
647c8464a6 Don't call sdhci_init_slot() until after handling the FDT properties
related to detecting card presence.  This actually makes no difference
now, but will when we get support for gpio-based card detection.
2014-04-02 19:06:53 +00:00
Ian Lepore
5b9b849b45 Trivial changes/forced-commit to document previous change r264050 whose
description was eaten by the dog (or an editor crash or something).

Add variable-frequency support to the arm mpcore eventtimer driver.

This allows a platform's early init code to tell the mpcore driver that the
clock frequency can vary.  That causes the mpcore driver to register an
eventtimer, but not a timecounter.  The platform has to provide a time
counter using some other fixed-frequency clock, but can still use the
per-cpu goodness of the mpcore hardware for event timers.

When the platform support code does something to change the frequency of
the CPU clocks (power saving, thermal management) it must tell the mpcore
driver code about it using arm_tmr_change_frequency().
2014-04-02 18:49:50 +00:00
Ian Lepore
b24b2743ce 2014-04-02 18:43:56 +00:00
Ian Lepore
c878f70aae Disable the timer and clear any pending bit, then setup the new counter
register values, then restart the timer.  This prevents a situation where
an old event fires just as we're about to load a new value into the timer,
when the start routine is called to change the time of the current event.

Also re-nest the parens properly for casting the result of converting
time and frequency to a count.  This doesn't actually change the result of
the calcs, but will some day prevent a loss-of-precision warning on the
assignment, if that warning gets enabled.
2014-04-02 18:32:27 +00:00
Luiz Otavio O Souza
ff5823beea Fix some of the style(9) problems on ti_gpio. Note that this commit does
not fix all the style(9) problems, but will open room for the next commits.

Remove redundant code and declarations.

No functional changes.
2014-04-01 18:46:56 +00:00
Tijl Coosemans
0a4c54d606 Rename __wchar_t so it no longer conflicts with __wchar_t from clang 3.4
-fms-extensions.

MFC after:	2 weeks
2014-04-01 14:46:11 +00:00
Ruslan Bukin
66e227bf1e Add Cortex-A15 cpu id revisions. 2014-04-01 04:56:40 +00:00
Ruslan Bukin
2638cebe23 Release i2c bus on detach. 2014-04-01 04:40:08 +00:00
Ruslan Bukin
657fae63fc Add support for keyboard used in Samsung Chromebook (ARM machine)
Support covers device drivers for:
- Interrupt Combiner
- gpio/pad, External Interrupts Controller (pad)
- I2C Interface
- Chrome Embedded Controller
- Chrome Keyboard

Also:
- Use new gpio dev class in EHCI driver
- Expand device tree information
2014-03-30 15:22:36 +00:00
Ruslan Bukin
a3fcf1f8d9 Add lowercase postfix, so SoC-common file will be ignored by tinderbox. 2014-03-30 14:57:00 +00:00
Ruslan Bukin
1a59c06c73 Directly call kmem_alloc_contig to allocate framebuffer memory
and pass VM_MEMATTR_UNCACHEABLE (no-cache, no-buffer).
This fixes screen refreshing problem when data is updated too slowly.

Discussed with:	ian
2014-03-30 14:42:53 +00:00
Ruslan Bukin
89eecf5b97 - Merge SoC-common parts
- Enable iicbus device
2014-03-30 14:25:14 +00:00
Andrew Turner
d4f9011c2e VFP fixes/cleanups for ARM11:
* Save the required VFP registers on context switch. If the exception bit
   is set we need to save and restore the FPINST register, and if the fp2v
   bit is also set we need to save and restore FPINST2.
 * Move saving and restoring the floating point control registers to C.
 * Clear the fpexc exception and fp2v flags on a floating-point exception.
 * Signal a SIGFPE if the fpexc exception flag is set on an undefined
   instruction. This is how the ARM core signals to software there is a
   floating-point exception.
2014-03-29 14:35:36 +00:00
Andrew Turner
2819cfdf3f Initialise fpscr to a sane value when we create the pcb. This sets NaNs to
be the default NaN and for denormalised numbers to be flushed to zero.
2014-03-29 14:17:04 +00:00
Andrew Turner
4797432ff7 Add more flags for the fpexc register from the ARM1176JZF-S Manual 2014-03-29 10:11:19 +00:00
Ganbold Tsagaankhuu
fe47fb7b1c Switch to my freebsd.org emal address in copyright.
Approved by:	stas (mentor)
2014-03-25 08:31:47 +00:00
Ganbold Tsagaankhuu
7717df1279 Add code for enabling second CPU core for A20 SoC.
Enable SMP on Cubieboard2.

Approved by:	stas (mentor)
2014-03-25 01:34:39 +00:00
Luiz Otavio O Souza
855feb6867 Adds the ADC driver for TI AM3xxx SoC family.
The ADC has a 12bit resolution and its raw output can be read via sysctl(8)
interface.

The driver allows the setup of ADC clock, samples average and open delay
(the number of clock cycles to wait before start the conversion).

The TSC_ADC module is set in the general purpose mode (no touchscreen
support).

Tested on Beaglebone-black.

Written based on AM335x TRM.

Reviewed by:	rpaulo
Approved by:	adrian (mentor)
Tested by:	me, Brian J. McGovern, Sulev-Madis Silber (ketas)
2014-03-24 20:06:27 +00:00
Andrew Turner
c9ccb0bb6b Move an else case that was missed in r263676 2014-03-24 08:24:32 +00:00
Andrew Turner
24456bdb9c Reorder the pmap macros so "ARM_MMU_V6 + ARM_MMU_V7" is first. As they are
identical this allows us to build for both v6 and v7 together.
2014-03-23 21:08:18 +00:00
Andrew Turner
0f6e287159 Simplify how we build MACHINE_ARCH. There are 3 options that may be set
however only arm, armeb, armv6, and soon armv6hf will be used.
2014-03-22 15:59:18 +00:00
Bryan Drewery
44f1c91610 Rename global cnt to vm_cnt to avoid shadowing.
To reduce the diff struct pcu.cnt field was not renamed, so
PCPU_OP(cnt.field) is still used. pc_cnt and pcpu are also used in
kvm(3) and vmstat(8). The goal was to not affect externally used KPI.

Bump __FreeBSD_version_ in case some out-of-tree module/code relies on the
the global cnt variable.

Exp-run revealed no ports using it directly.

No objection from:	arch@
Sponsored by:	EMC / Isilon Storage Division
2014-03-22 10:26:09 +00:00