230523, 1123614
Implement a driver for Robert Norton's PIC as an FDT interrupt
controller. Devices whose interrupt-parent property points to a beripic
device will have their interrupt allocation, activation , and setup
operations routed through the IC rather than down the traditional bus
hierarchy.
This driver largely abstracts the underlying CPU away allowing the
PIC to be implemented on CPU's other than BERI. Due to insufficient
abstractions a small amount of MIPS specific code is currently required
in fdt_mips.c and to implement counters.
MFC after: 3 days
Sponsored by: DARPA/AFRL
unmerged BERI DTS files) to head:
Use the OFW compatible string "mips,mips4k" rather than
"mips4k,cp0" for interrupt control using MIPS4k CP0.
Suggested by: thompsa
Implement a MIPS FDT PIC decode routine to use when no PIC has been
configured, which assumes a cascade back to the nexus bus (e.g.,
the on-board CP0 interrupt management parts on the MIPS). If the
soc bus in a MIPS DTS file is declared as "mips4k,cp0"-compatible,
then this will be enabled. This is sufficient to allow IRQs to be
configured on BERI.
Sponsored by: DARPA, AFRL
